SU1427365A1 - Random process generator - Google Patents

Abstract

The invention relates to computing and can be used to solve problems of research and optimize the structure of complex systems. The aim of the invention is to increase the accuracy of the generator. The random process generator contains 1 pulse generator, 2 random numbers sensor, memory block 3, control block 4, counter 5, registers 6.7, frequency divider 8, reversible counter 9, code-voltage converters 10, 11, And 12 elements -14, register 15, trigger 16, block 17 modulo two. 1 hp f-ly, 3 ill.

Description

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The invention relates to a decisive technique and can be used in the construction of simulation equipment for solving research problems, and optimizing the structure of complex systems, for automating tests for vibration, shock, electrical and other types of influences.

The purpose of the invention is to improve the accuracy of the generator.

FIG. 1 shows a structural diagram of the generator; in fig. 2 - the same, control unit; in fig. 3 is a timing diagram of the control unit operation cycle.

The generator contains a 1 pulse generator, a sensor of 2 random numbers, a memory block 3, a control block 4, a counter 5, registers 6,7, a frequency divider 8, a reversible counter 9, pre-code - voltage 10, 11, And 12- elements 14, register.pam 15, trigger 16, block 17 modulo-two adders. The control unit contains a pulse shaper 18, triggers 19-22, elements AND 23-24, element OR 25.

Consider the functioning of the mouth

on the i-th cycle since windows-30 12, and the output of the device saves 40

the duration of the formation of the (i-1) -th pause. The overflow signal: from the counter 5, the i-pause duration code stored in register 6a is stored in this counter, stored at the output of the control unit 3 (Fig. 2), a single potential is established (Fig. 3), which permits the passage of clock pulses the output of the generator 1 pulses through the element 12 on the information input-divider 8 frequency. The division factor of frequency divider 8 is set by the code stored in register 7, and determines the frequency of changing the states of the reversible counter 15 9 and, accordingly, the pulse duration at the output of the device. As the pulses at the input of the reversing counter 9 are received, the latter increases its state, which is converted by the code-10 converter into a continuous electrical signal, the polarity of which is determined by the state of the trigger 16. The code-voltage converter 11 amplifies this voltage in accordance with the code that sets the amplitude value and is stored for the entire time of the process formation in

zero level, cG) —the unit potential from the fifth output of block 4 permits the passage of clock pulses through the element 13 to the counter output of pulse counter 5, which successively reduces its state by one, forming a pause duration; B) —two pulses from the first output of a block of 4 sensors of 2 random numbers form successively two uniformly distributed random numbers specifying the addresses of block 3 of the memory ;. i) impulse. From the second and fourth outputs of block 4, the sequential reading of the addresses generated by the sensor 2 random numbers to the codes defining the values of the pause and pulse duration on the (i + 1) -oM cycle and entering these codes into registers 6 and 7, respectively, as well as setting the equilibrium state of the trigger 16.

50

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When the counter 5 reaches the zero state, the formation of the duration of the i-th pause ends, and the described generation process repeats cyclically.

register 15. A reversible counter 9 sequentially changes its state to the maximum, when an overflow signal occurs, it switches to the countdown mode and sequentially changes the state from maximum to zero. Thus, during the time when the arrival of pulses at the counting input of the reversible counter 9 is allowed, an equilateral triangular pulse is generated at the device output, the polarity of which is equally defined on the (i) -OM device operation cycle, the duration is also specified by the code selected from the sequence of codes for the distribution of durations.

When the reversible counter 9 reaches the zero state at the output of the element 14, a level is set

1 Vno which signals are generated at the outputs of control unit 4 (Fig. 2) according to the timing diagram: and a low level from the fifth output of control unit 4 prohibits the passage of pulses from the output of generator 1 of pulses through the element I

0

15

zero level, cG) - a single potential from the fifth output of block 4 permits the passage of clock pulses through the element 13 at the counting output of the counter of pulses 5, ko-. Secondly, it gradually reduces its state by one, forming the duration of the pause; B) —two pulses from the first output of block 4, the sensor 2 of random numbers generates successively two uniformly distributed random numbers specifying the addresses of memory block 3 ;. i) - pulses from the second and fourth outputs of the 4th dry block, sequential reading of 2 random numbers generated by the sensor to the addresses of the codes specifying the pause and pulse duration values for the (i + 1) -oM cycle and entering these codes, respectively registers 6 and 7, as well as the installation of an equal state of the trigger 16.

0

When the counter 5 reaches the zero state, the formation of the duration of the i-th pause ends, and the described generation process repeats cyclically.

Claims (2)

1. A soldering process generator containing a memory unit, a pulse generator, a random number sensor, a control unit, the first input of which is connected to the counter output, the first output of the control unit is connected to the input Poll sensor of a random number, the second output of the control unit connected to the synchronization input of the first register; the third output of the control unit connected to the synchronization input of the second register; the frequency divider whose input is connected to the counting input of the reversible counter; the first and second converters code — voltage Moreover, the output of the first converter code - voltage is connected to the input of the reference voltage reference of the second converter code - voltage, characterized in that, in order to improve accuracy, three elements AND were entered into it, the memory register, trigger, block of adders module two, with the output of the pulse generator connected to the first inputs of the first and second elements And and to the second input of the control unit, the third input of which is connected to the output of the third element And whose inputs are connected to the corresponding discharge outputs of the counter The first group of inputs of the block of adders modulo two, the second group of inputs of which is connected to the inverse output, the trigger, the direct output of which is connected to the input of the higher bit of the first converter code - voltage, the inputs of the lower order of which are connected to modulo two adders block outputs, the fourth control unit code is connected to the second input of the second element AND whose output is connected to the information input of a frequency divider, the input of setting the division factor of which is connected to the output of the second register ra, whose information input is connected to the information input of the first register and with the output of the memory block, whose aders input is connected to the bit output of a random number sensor, the output of the first bit of which is connected, to the information trigger input, the synchronization input of which is connected to the third output of the control unit and the first reading input of the memory unit, the second reading input of which is connected to the second output of the control unit, the fifth output of which is connected to the second input of the first element And whose output is connected to the counting the counter input whose preset input is connected to the first register code, the output of the memory register is connected to the information input of the second code-voltage converter, the output of which is the output of the generator Torah. 2. The generator according to claim 1, that is, that the control unit contains a pulse shaper, a trigger, two AND elements, an OR element, and the output of the pulse shaper is connected to the counting input of the first trigger, the direct output of which is connected with the information input of the second trigger, the direct code of which is connected to the counting input of the third trigger, the direct output of which is connected to the counting input of the fourth trigger, the inverse output of which is connected to the input of the zeroing of the second trigger, whose output is connected to the first The inputs of the first and second elements are AND, the output of the second element AND is connected to the first input of the OR element, the output of which is the first code of the block; the inverse output of the third trigger is connected to the second input of the first element AND whose output is connected to the second input of the OR element and the fourth output of the block, the inverse output of the first trigger is the third output of the block, the output of the second element I is the second output of the block, the direct output of the first trigger is the fifth output of the block, the zero input of the first trigger ene with the reset input of the fourth flip-flop and is the first input unit, the clock input of the second latch is a second input unit, the input pulse shaper is a third input block.