RU1800617C - Analog-to-digital converter - Google Patents

Abstract

The invention relates to pulse technology, in particular to voltage converters into digital code with an intermediate conversion of voltage to pulse frequency, and can be used in devices for collecting analog information of control and control systems implemented on computer equipment. The disadvantages of those known and close in technical essence and the problem to be solved are analog-to-digital converters (ADCs), which are as follows. that when measuring the input signal during its conversion, multiple switching and subtraction operations are performed, which lead to additional errors as a result of the conversion. The aim of the invention is to increase accuracy. The ADC contains a voltage to frequency converter (VLF), an adder, a counter, read only memory, pulse shapers and a pulse distributor, AND or OR logic elements, triggers and one-shots. The introduction of three analog keys and an integrating element is new, due to which the VLF conversion coefficient is adjusted in the ADC so that the signal to be converted is not switched and subtracted. 2 ill. CO C

Description

The invention relates to a pulse technique, in particular to voltage converters into a digital code with intermediate conversion to a pulse frequency, and can be used in devices for collecting analog information of various systems executed on computer equipment.

The purpose of the invention is to improve the accuracy of the ADC.

Figure 1 shows a block diagram of the proposed ADC; Figure 2 is a timing diagram of its operation.

The converter contains buses 1-4 of the converted voltage 1) x, the result

conversion, its availability and reference voltage U0, a voltage to voltage converter 5, an analog adder 6 and an integrating element 7, from the first to the third analog switches 8-10. in the first two of which the information input is connected to the output when there is a signal at the control input, and in the latter they are all the time connected and open when there is a signal at the control input, read only memory 11, from the first to the third counters 12-14 ; first and second registers 15 and 16: generator 17 and pulse distributor 18, from first to third triggers 19-21, from first to four

oh oh

Ј XI

the first one-shots 22-25, the first and second pulse shapers 26 and 27, of which 33 are a group of AND elements, from the first to the fourth elements OR 38-41, the logical inverter 42.

Figure 2 indicates: 43 - counter overflow pulse 13; 44 and 45 — PNF5 pulses and driver 27; 46, 47 and 48 - signals at 1 outputs of triggers 19, 20 and 21; 49 and 50 - signals at the outputs of the elements IL AND 40 and 34; 51-54-pulses at the outputs of the elements And29,30,32 and 31; 55 and 56 signals of single vibrators 24 and 25; 57.58 and 59 are the pulses of the shaper 27, the first and last bits of the distributor 18; 60-signal at 1 high-order output of counter 12.

In the ADC, bus 1 is connected to the first input of the adder 6, buses 2 are the outputs of the register 1 b, bus 3 is the output of the one-shot 25 and with the first input of the OR element 41, bus 4 is connected to the information inputs of the keys 10 and 9, the output of the first of which is connected to the third input of the adder 6, the output of the second through element 7 with the information input of the key 8, the output of which is connected to the second input of the adder 6, the output of which through the converter 5 is connected to the control input of the key 8, to the first inputs of the elements And 28 and OR 38-41, the output of which is connected to the counting input of the first hundred the last bit of the counter 14, the outputs of the bits of which are connected to the inputs of the register 16, the inputs of the least significant bits - with the outputs of the AND 33 elements, the input of the O code setting - with the second input of the OR 39 element and through the former 27 - with the input of the subtraction mode control counter 14, the input of the register code register 16 and the input and output of the one-shots 25 and 24, the input of the latter is connected to the output of the AND 30 element, 1 by the inputs of the triggers 20 and 21, the first input of the OR element 39 and the write input of the device code 11, the outputs of which are connected to the second inputs of elements And 33, inputs of senior and the best bits of the address are, respectively, with the outputs and inputs of the bits of register 15, the last of which are combined with the outputs of the bits of the counter 12, O and 1, the outputs of the senior bit of which are connected respectively to the O input of trigger 21 and the second input of AND 37, subtraction control input — with the output of the And 34 element and the second input of the And 31 element, the installation input О code — with the output of the And 29 element, the counting inputs of the first and second low-order bits - with the outputs of the And 35 and 36 elements, the first inputs of which are combined and connected to the output of the generator 17, the second at entry AND gate 28 and the counting input of the counter 13,

the overflow output of which is connected through a one-shot 23 to the input of the register code record 15 and with 1 input of the trigger 19, the input of which is connected to the output of the And 32 element, 1 output - with the second input of the And 30 element, the first input of which is connected to the first inputs of And 29 elements , 31 and 32 and through the shaper 26 - with the output of the OR element 38, the second input of which is connected through a single vibrator 22 with the output of the And 28 element, the output of the And 31 element is connected to the first input of the And 37 and O element of the trigger 20, the output of which is connected to the first input of the OR element 40, 1 output - from the second m and the first inputs of the elements And 32 and 34, the second input of the latter is connected to the O output of the trigger 19 and the second input of the OR element 40, the output of which is connected to the second inputs of the elements And 29 and 36 and through the inverter 42 to the second input of the element And 35, inputs the key controls 9 and 10 are connected respectively to the output of the AND element 37 and 1 by the output of the trigger 21, the output of the OR element 39 is connected to the input of the distributor 18, the outputs of the bits of which are connected to the second inputs of the AND elements 33,

ADC works as follows.

The converted voltage Ux is summed with the reference voltage U0 in the adder 6. The voltage Uc Ux + U0 is supplied to the input of the voltage converter to the VLF5 frequency, which has output pulses 44 with the repetition frequency Fc KnUc, where Kp is the VLF conversion coefficient. If the VFD 5 has a current input, the adder 6 can be made on resistors connected to its output and converting the input signals into currents that are summed at the output.

Each conversion Uc occurs during a time li I0, which is generated by the counter 13 and the frequency f of the generator 17.

The pulse 43 overflow counter 13 ends the measurement of Uc in Ti cycle and begins the h cycle of the ADC.

Pulses 43 and 44 are used in the process of generating the result of the conversion, but they do not have synchronization with each other, therefore, the operation of the ADC units can cause malfunctions and errors at the moments of mutual overlap of these pulses. To avoid this, at the moment of coincidence of pulses f and 44, the AND element 28 is triggered and a single-shot 22 is triggered by the rising edge, the output signal of which is combined with the pulse 44 in the OR element 38, increasing its duration. Shaper 26 is triggered at the trailing edge of this signal, the output pulses 45 of which are always shifted relative to the pulses f.

In order to exclude the influence of the change in the conversion coefficient Kp of the VLF5 on the conversion result in the ADC, its adjustment is carried out to ensure the Kp Ko. It is performed during the first two periods of the frequency Fc after the pulse 43, which sets the trigger 19 to 1. Its signal 46 allows the operation of the element And 30 through which the first pulse 52 of the number of pulses 45 passes. From this moment, the first tuning period tci begins.

The pulse 52 sets the triggers 20 and 21 to 1, their signals 47 and 48 enable the operation of the elements And 32 and 34, and using the key 10 disconnect the voltage U0 from the adder 6. The signal from the O output of the trigger 20 until the arrival of pulse 52 passed through the OR element 40 (signal 49) and allowed the operation of the And 29 element. Pulses 45 passed through it, forming pulses 51, which set the O code in counter 12. At the time of pulse 52, it the O code was also set and the counting of pulses f of the generator 17 began, which pass to its counter input through the And element 35, due to the presence of the signal from the output of the inverter 42, which has an inverse value in comparison with the signal 49. After a time interval to, the high order bit of counter 12 will be set (signal 60) and the removal of the signal from its O output will set to O trigger 21. The signal 48 is removed and the voltage Do is reconnected to the adder, which was disconnected from its input by the time t0.

The period tci ends with the end of the pulse 44 of the pulse 53 from the output of the element And 32 formed by the pulse 45. The pulse 53 sets the trigger 19 in O and removes the signal 46. During the time td, a conversion is performed in the IFF 5, which can be described by the expression:

or

KnUxto + Kn (Ux + Uo) (tcl - to) - 1 Kn (Ux + Uo) tc-KnUoto 1.

After tci voltage Do from the adder

6 no longer turns off, and the VFD 5 converts to the frequency Fc - the total voltage Uc (Ux + U0). Each subsequent step of the operation of the IF5 can be described by the expression:

Kn (Ux + U0) tc KnUctc Fctc 1.

th

The period of frequency Fc following tci will be equal to tC2. Therefore, using the transform expressions for tci and tC2 and substituting the second into the first, we get:

tci tc2

- KnUoto 1 OR tc1 tc2 (1 + KnUoto).

Thus, the durations of the periods of these two frequencies have a constant ratio, which does not depend on the magnitude of the converted voltage Ux, but depends on the value of Kp of the IF conversion factor 5.

This is used to evaluate the latter. If it is assumed in the ADC that the conversion coefficient of the VLF 5 should be equal to Ko and, when converting U0, the period of the obtained frequency F0 K0U0 is equal to

equality is valid for this period

K0Uoto 1.

Therefore, at Kp K0, the ratio of the periods tci and tc2. which can serve as confirmation of the correctness of the setting of Kp.

From a change in temperature and from a temporary drift of the VLF parameters, the value of its conversion coefficient will decrease in comparison with K0, i.e. Kn K0 or Kn K0 - - K0 d Ko (1st). In this case, the ratio of periods will vary:

tci tC2 1 + K0 (1-d) Uoto tea (2-d).

40

45

fifty

55

Violation of the ratio gives information 6 of the need to adjust Kp by increasing it to K0. This is realized by comparing tci and 2tc2. During tci, the counter m tcif was received in counter 12 and it was saved after tci ended, since there was no pulse 51 with tci ending due to the absence of signal 49 at the moment of pulse 45. During the time tC2, the gy code obtained in counter 13 is reduced to zero by pulses f. coming from the output of AND element 36, the operation of which is allowed by signal 49, to the counting input of the second least significant bit, counter 12, in which signal 50 turned on the subtraction mode.

To get the About code will be spent

P11 1

time t2 -k- g i.e. time equal to -j- tci,

and the next pulse f will set 1 code in all bits of the counter 12. In this case, the signal 60 from the 1 output of its highest bit allows the operation of the And 37 element.

If tC2 ends with the end of t.2, which corresponds to the equalities tci 2tc2 and Кп Ko, then the pulse 54, which is formed in the element And 31, lasts until the signal 60 is turned on and it does not pass through the element And 37, When Кп К0, when tci 2tc2, the end of ta will occur before the appearance of pulse 54, since it will also pass through the AND element 37, which is a signal to increase the coefficient of Kn in the IFF 5,

It is possible to carry out a change in the coefficient Кп in the VFD, which is made, for example, by using a method of compensating the generated internal charge q in the integrating capacitor charged from the converted voltage, by changing q using an external voltage applied to the input of the VFD. To this end, during the formation time q equal to the pulse duration 44, a voltage l / u is applied to the input of adder 6 from the output of element 7 using the key 8 and having the same polarity with U0 and Ux. Due to this, the output frequency Fc of the VFD 5 is increased, i.e. the coefficient Kp increases.

The voltage in the element 7 appears after the voltage U0 is connected to its input using the switch 9 for the duration of the pulse 54 passing through the element And 37. The input circuit of the capacitor charge of the integrating element 7 has a lower resistance compared to the output circuit , i.e. the discharge time constant of the capacitor of element 7 is significantly greater than the measurement cycle h Uc. Due to this, the voltage Oy formed during charging is maintained for a long time and increases by a small amount when the capacitor is recharged.

Thus, in each step h, the value of Кп is checked, and its change affects the value of Ki, which ensures the equality in the ADC

1 Kn To - For all measures

vani is.

This makes it possible in time, by counting the pulses FC, to obtain a conversion result that will not contain errors from changes in Kp and h, since the latter, and to, is formed using pulses of the generator 17 and has the value Ti 10 N0t0, and the coefficient

Kp Ko 11 “But for this case, the result

This conversion may contain errors, the values of which can be ± 1, due to the non-synchronism of the occurrence of pulses Ij 43 and Fc 44. The magnitude of these errors will depend on the time of the appearance of the first pulse Fc in h and on the time Tkj from. the last pulse Fc at li until the end of li.

If the calculation of pulses Fc in the li clock cycle of the ADC starts with the second of Fc, and the first of them is attributed to the T clock, then when generating the result of the conversion in the h clock, it is necessary to increase it by the value of mon | KoUctkj K0 (UX + U0) Tkj, which takes into account the conversion of Uc during VT (and the result of the previous T step must be reduced by this value. In addition, the result of the TI step must be reduced by nkj + 1

 K0Uc Tkj + 1 K0 (Ux + Uo) Tkj + 1, which takes into account the correction from the transformation Uc during Tk,.

In order to obtain corrections nHj in each Tj cycle, the measurement of tkj and the period Tnj, which refers to the last

in Tj momentum Fcni --2- These measurements are

are filled using the counter 12 and the pulses of the generator 17, arriving at its second least significant bit through the element 36, the operation of which is allowed by the signal 49. The same signal allows the operation of the element And 29 through which the pulses 45 pass and form pulses 51, the last of which the O code is set in counter 12 at the end of the Fc periods, except for the tci period when this does not occur.

With the advent of pulse 43, the code nki 2Tkif accumulated during tni by the counter 12 is written into the register 15 by the pulse of the single-vibrator 23.

With the end of Tni, the code rini 2Tnif obtained in the counter 12 and the code riki of the register 15 are written into the upper and lower bits of the register of the address of the device 11 by the pulse 52.

Using the codes nkj and PRI, it is possible to determine the magnitude of the correction mon |. Given that

KoUcTni 1, but Mon | KoUcThi AND tHi YOU - tki, TO

rinj - ---- Value and it can be

tni

express through gsh and nni: nki

Tnj nkj

rinj

In accordance with this formula, the values of the corrections are calculated for all values of rini and nki. For discreteness of the quantity

corrections equal - nki values will be from

I

vary from 0 to (1 - -).

By

All these values are written in the form of a table to the read-only memory 11, from which they will be read by the codes of the upper and lower bits of the address corresponding to the values nni and pc |.

In order to reduce the volume of memory cells of the device 11 and reduce the number of calculated corrections nni, it is advisable to increase the discreteness by the factor and, in comparison with the least significant digit of the counter 12, and use only the most significant bits of the codes nni and in the address codes. The number of these bits is determined by the received

1

for discreteness

By

After the pulse 52 writes the address codes to the registers of the device 11, the correction code .nHi is set at the outputs of its bits, which is fed to the inputs of the And 33 elements.

The pulse 52 also starts a single-vibrator 24 and it passes through the element OR 39 to the input of the pulse distributor 18, the outputs of which are sequentially in time pulses 58 and 59. These pulses pass through those elements And 33, which are at the inputs from Devices 11 have 1 signals in nHi code bits, to the counting inputs of the corresponding bits of counter 14. Thanks to this, nHi is bitwise summed with the code located in counter 14.

The signal 55 of the one-shot 24 has a duration that overlaps the operation of the distributor 18, and it turns on the subtraction mode in the counter 14. Therefore, the code received during Ti in the counter is reduced by PH

With the end of signal 55, one-shots 25 and shaper 27 are started, pulse 57 of which sets the O code in counter 14 and starts pulse distributor 18 again through element OR 39. Based on its pulses 58 and 59, the code nHi is written to counter 14. The signal 56 of the single-shot 25, having a duration equal to the signal 55, passes through the OR element 41 and writes 1. In the first high-order bit of the counter 14, this is done in order to take into account the shutdown of U0 for the time to in the first period tci of the IFF 5 operation, during whose summation and subtraction of nHi was performed.

In accordance with discreteness - vepo

rini, the weight of the least significant bit of counter 14 should be equal to - if its weight is first

the first high order bit is equal to 1, and the capacity of its lower order bits must be equal to n0 in order to perform the above operations of adding and subtracting nni.

With the end of tci and further with each pulse 44 that pass through the OR element 41, the counter code 14 will increase by one each time. With the end of tm in the counter 14 during this time each time per unit. With the end of tHi, the counter 14 during this time will receive from the IF 5 an integer number of NC pulses 44, which corresponds to the value:

Nc KoUctd - KoUoto + K0Uc (to - tHi - tci +

+ tHH-1) K0 (Ux + Uo) lo - Ko (Ux + U0) tHi + + Ko (Ux + U0) tHi + 1 - 1.

Taking into account that, in counter 14, the operations of summing the amendment Пж K0 (UK + Uo) tHi and adding one were performed, and also taking into account that with the end of tHi, the operation of subtracting the amendment Пж-н KO (UX + UO) T.HH -I that increasing the code from counter 14 to Nc will lead to the result Np, which corresponds to the value Np KoUcTo K0 (Ux + U0) o, since the last three terms in the expression for Nc will be compensated by the operations performed.

Therefore, the code received in counter 14 will be equal to:

HHJ GPG

Mon +1 By

(Ux + Uo) lo.

expression meaning

0 5 0

5

 +

Mon |

Mon j +1

U

No + Uo.

P0 By Uo

If we take the weight of the least significant bit of counter 14 to 1 instead of -, then

The XP code for all its bits will be equal to:

Chp Ncn0 + Pn - PnN-1-GG MoPo + N0n0.

Uo

Therefore, a decrease in Xp by N0n0 gives an exact result of the transformation

X | Xp - N0n0-r -; - N0n0-j-,

where a

U)

K. - quantum ADC. which corresponds to

the lower-order unit of the Xi code.

If the total capacity of the counter 14 is equal to MoPo (the capacitances of the upper and lower bits are equal to N0 and n0, respectively), upon receipt of this value it will overflow, which is not used in the ADC, and the code Xi will be found only in its bits.

In this case, the maximum value of Ux must not exceed the voltage Um (Uo - ty in order to avoid overflow of the counter 14 during the conversion of Um.

The conversion result code Xi from the counter 14 is rewritten according to the rear edge of the signal 55 to the register 16, from the outputs of which it is transmitted via buses 2, and the one-shot 25 is informed of its readiness by the signal 56 transmitted via the bus 3.

Thus, in the proposed ADC for each clock cycle P, the result of the conversion Xi corresponds to measuring the signal Ux during that cycle alone, i.e. the results of successive measurements will correspond to the time steps П of its operation in contact with time.

In contrast to the prototype, in which it is necessary to perform the operation of subtracting the voltage Ux from the voltage Uo to obtain UB (U0 - Ux), and switching at the input of the VLF signals Uc to UB and vice versa in each cycle of its operation, performing these operations in the proposed ADC is not required.

In the description of the prototype for the given example for which the ratios Uo 2Um, To Nm / Fm, where Fm is the maximum frequency of the VLF and Fm 3K0Um, it is shown that at different levels of Ux during the conversion time 0 such

switching Uc and UB will be from-at- Nm at Ux

2

 Um to -s- Nm at Ux 0. In the prototype

The need to obtain UB and the different number of switchings Uc and UB led to additional errors as a result of the transformation Xj. Taking into account these additional errors, the value of the quantum Dp, which corresponds to the low order of register 16 and the code Xp of the conversion result, was selected in it.

In the proposed ADC, the converted voltage Uc (Ux + U0) is permanently connected to the VLF and for only one period tci of tuning Kp in the signal Uc, the voltage Uo is turned off for a while to. Therefore, the absence of operations for obtaining Us and multiple switching of the converted signals at the input of the IFF eliminates from Xj additional errors inherent in the prototype, which increases the accuracy of the proposed ADC,

It should also be noted that the proposed solution allows to reduce the maximum frequency Fm of the VLF operation, since the subtraction operation (n0-Ux) is not performed. Compared with the example in the description of the prototype, for

WHICH Um-Uo And Fm 3K0Um, FOR

this ADC can, for example, take

Um Uo and thereby provide Fm 2 K0Um, i.e. reduce it by 1.5 times. This, in turn, will allow for the parameters T0, f, Um and K0 to be identical with the prototype to reduce additional quantization errors

in the operation of comparing tc and 2tc2, i.e. to increase the accuracy of setting Кп К0. This, in addition to the errors already excluded, makes it possible to further reduce the overall conversion error, taking into account which the ADC quantum value corresponding to the low-order bit of the conversion result code Xj is selected.

All this shows that the proposed

The ADC solves the problem assigned to it and eliminates the disadvantage of the prototype, in comparison with which an increase in the accuracy of its operation is achieved.

Claims (1)

The claims An analog-to-digital converter comprising a voltage to frequency converter, the output of which is connected to the first inputs of the first AND and OR elements, whose second input is connected through the first one-shot to the output of the first And element, and the output through the first pulse shaper with the first inputs of the second, third, fourth and fifth And elements, the output of the first of which is connected to the installation of the code of the first counter in О, the outputs of the bits of which are connected to the inputs of the corresponding lower-order bits of the address of the read-only memory device and the bits of the first register, the code recording input of which is connected through the second one-shot to the overflow output second counter and combined with the installation input in 1 of the first triggers, bit outputs - to the inputs of the corresponding high-order bits of the address of the read-only memory device, the information outputs of which are connected to the first inputs of the corresponding of the sixth AND elements, the input of the address record is combined with the first input of the second OR element, with the input of the third one-vibrator and connected to the output of the third AND element, the second input of which is connected to the 1-output of the first trigger, the output of the third one-vibrator is connected to the write input of the second register code , to the input of the fourth one-shot and through the second pulse shaper - to the installation input in O of the third counter and to the second input of the second OR element, the output of which is connected to the input of the pulse distributor, the outputs of which are connected to the second inputs of the corresponding sixth AND elements, the outputs of which are connected to the inputs of the corresponding lower bits of the third counter, the outputs of the bits of which are connected to the inputs of the corresponding bits of the second register, the outputs of the bits of which are the bus of the result of the conversion, the output of the fourth there is a ready bus, the input bus of the converted voltage is the first input of the analog adder, the output of the fourth element And is connected to the installation input in O of the second trigger, 0-out One of which is connected to the first input of the third OR element, the output is to the first input of the seventh AND element, the second input of the first AND element, the second input of the first AND element is connected to the output of the pulse generator and combined with the counting input of the second counter and with the first inputs of the eighth and ninth AND elements, the second input of which is connected to the output of the third OR element and combined with the inverter input, the output of the eighth AND element is connected to the counting input of the first counter, the tenth AND element, the fourth OR element, and the third trigger, distinguish iys in that, in order to increase accuracy, it entered the three analog switches and the integrating element, whose output is connected to the data input of the first switch, the input - with the output of the second key information input and combined with the input of the third switch of the same name and is the reference voltage bus, the outputs of the first and third switches are connected to the second and third inputs of the analog adder, the output of which is connected to the input of the voltage to frequency converter, the output of which is connected to the control input of the first switch and with the first input of the fourth element OR, the second input of which is connected to the output of the fourth one-shot, the output is with the counting input of the first high-order bit of the third counter, the input of the control of the subtraction mode of which 15 is connected to the output of the third one-shot, the control inputs of the second and third keys are connected respectively to the output of the tenth element And and to the 1-output of the third trigger, the installation input to 20 1 which is combined with the installation input in 1 of the second trigger and with the input of the third one-shot. the input of the installation in O is connected to the 0th output of the high order bit of the first counter, the counting input of the second 25th low order bit is connected to the output of the ninth AND element, the input of the subtraction mode control is connected to the output of the seventh AND element and combined with the second input of the fourth AND element, the output of which is connected to the first input of the tenth element And, the second input of which is connected to the 1-output of the highest order of the first counter, the first input of the seventh element And is combined with the second input of the fifth element I. The second input is combined with the second input third first OR gate and is connected to the 0-output of first flip-flop, a set input of which is connected to the output of the fifth AND gate, the input and the output of inverter 40 are connected respectively to the second inputs of the second and eighth elements I. 4 ;.; 45; W # 7 U: h 48. ; .. W 5/  ss1: 53 # $ h :. . 55 56 57 58  i- n ..a. Fig 2 45