SU1048572A1 - Code/frequency converter - Google Patents

Description

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x The invention relates to computing and automation and can be used in devices where a linear code-frequency conversion with increased accuracy is required over a small time interval of averaging. A code-to-frequency pulse following converter is known, containing registers of a frequency setting code and a code defining a conversion time interval, counters, comparison and reading blocks, control triggers and keys l. This converter provides a linear relationship between the input code and the output pulse frequency, but differs in complexity and low accuracy at averaging intervals smaller than the device's conversion interval. The code-frequency converter containing the first adder, the first output of which is connected, is also known. to the first input of the multiplexer, the second input of which is connected to the input bus of the phase setting, the third input to the control bus, and the output through the register, clocked input of which is connected to the cycles second bus connected to the first input of the first adder, the second input of which is connected to the input bus 2J frequency setting. This converter is characterized by simplicity of the circuit solution, however, it also does not allow to obtain a high conversion accuracy in the averaging interval smaller than the conversion interval. So, during one conversion cycle, tij to 2 7, where LO is the period of the following clock pulses, P is the converter, the output of the converter is F pulses, where F is the number set on the frequency code buses, with the average period G 1 / er - p ---o F In the general form, 21 / P is expressed as an improper fraction with a whole and a fractional part, the presence of which leads to an error. Since the actual follow-up period of the output impulses is each time a multiple of l (the effect of time quantization), the conversion error is expressed in left-wise; The scientific research institute of the periods of an output signal, equal to quantity IQ, corresponding to the whole part of an irregular fraction, and increased by t. Reducing such an error can be achieved by reducing (which results in an increase in the bit size of the P converter, and this, with limited speed of the circuit elements, limits the upper frequency of the conversion. The aim of the invention is to improve the accuracy of the conversion. in the code-frequency converter containing the first adder, the first output of which is connected to the first input of the multiplexer, the second input of which is connected to the input phase setting bus, the third input to the bus control, and the output - through the register, clocked input of which is connected to the clock bus, connected - to the first input of the first adder, the second input of which is connected to the input frequency setting bus, additionally entered the second adder, pulse-width converter and inverter unit, whose input connected to the first output of the first adder, and the output to the first input of the second adder, the second inputs of which are connected to the corresponding buses of the installation of the logical unit, and the output to the first input of the pulse-width converter Atel., the second, the input of which is connected to the second (the output of the first adder, the third input - with the input frequency setting bus, and the output with the output bus. FIG. t is a structural electrical converter circuit; in fig. 2 - a variant of the circuit of the ip-pulse converter; in fig. 3 and - BpeMeHHbte diagrams, which explain, respectively, the operation of the orothoid transducer and the formation of the delay of the output signals at the outputs of two similar transducers. The converter contains an adder 1, outputs connected to the first inputs of the adder 2. through a block of inverters 3 and to the first BxojqaM multiplexer C, the second inputs of which are connected to the phase setting input bus 5, and the control input to the converter control bus 6. The output of the multiplexer U is connected to the first inputs of the adder V via a register 7 "clocked input of which is connected to the clock bus 8 of the converter. The input bus 9 of the frequency setting is connected to the second inputs 10 of the adder 1 and to the inputs 11 of the pulse-width converter (SHIP) 12 and the transfer output of the higher bit of the adder 1 is connected to the input 13 of the CHIP 12. The second inputs of the adder 2 and the transfer input of its first discharge are connected to the bus logical unit and the outputs - to the inputs k of the SHIP 12. The converter operates as follows. Bus 5 is set to zero code. The control bus 6 is set to a low potential controlling the multiplexer. In this case, the phase setting code is transmitted via bus 5 to the inputs of register 7 and, under the action of clock pulses on bus 8, which follow with frequency ig, is rewritten to its output. On the input bus 9, the code F is set corresponding to the selected frequency of the output signal. Since the value of f z, at the output of the transfer of the adder 1 is set to zero potential and SHIP 12 is closed. At the outputs of the adder 2 is set to a number. This stage corresponds to the preparation of the converter. The start of the conversion coincides with the establishment of a high potential on Control Bus 6 and, accordingly, at the control input multiplexer, switching the outputs of adder 1 to the inputs of register 7. At the outputs of adder 1, a sequence of numbers is generated, increasing by the clock pulse acting at input B. According to the K th pulse, the state of the outputs of adder 2, which calculates the difference between 2 and the number at the output of adder 1, is m 2 - (k + 1); Obviously, over the (K + 1) th pulse, overflow of the adder 1 occurs. At the output of the higher-order carryover 13, a unit is established, with the arrival of which, iijun 12 starts the formation of a correction impulse, ,, -h M, the duration of which with - (- o-p. As can be seen from the formula, the number P dictates how many parts it is necessary to allocate the period of such impulses 0, to get the din time correction quantum about itf, -, and the number M - what quantity of quanta 611 n is needed to form the correction impulse to ensure equality BW Ter. (.f T. d). Thus, the first period can be written, IK ,. "). + m.-gp de K. - the number of integer periods. By the next K + 2) -th clock pulse at the outputs of the adder 1, the number 2 F is set to M-i 2. At input 13 of GC12, a zero potential is established and GIP-12 is closed. The formation of a numerical sequence continues, increasing by a P until the next transfer pulse appears at the output of adder 1. You can write an expression for the period l of the general case Mi-Mi.4 where l is the number of periods between two neighboring transfer pulses, M,., is the correction factor for the previous (il) -ro transfer pulse; Mi is the correction factor - “—th transfer pulse, i 1,2, .....” After the conversion interval tj, 2 dT, is resumed, as the circuit returns to the initial state. One of the possible options for building a pulse width converter is shown in FIG. 2. The converter contains the first digital-to-analogue transducer (DAC) 15, an output connected to capacitor 1b, a sequentially connected control key 17 and a discharge current generator (GDT) 18, and an input to buses 11, a second DAC 19, output connected to the capacitor b through the control key 20, the comparison element 21 is zero, the input is connected to the capacitor 16, and the output to the output bus is through the logical element IS-NOT 22, the second input of which is connected to the control input by the key 20 and the input 13 SHIP, output element is NOT connected to the control input audio klyucha- 17. The input 13 to the adder overflow pulses tread 1 (FIG. Per). At the inputs 11 a number is set, differently Fi, while the output of the first D / A converter 15 is affected by the voltage Up. where E is the reference voltage module at the analog input of the first DAC 15. At the inputs 1, the number M is set :, while the voltage at the output,; DAC 19ip || M (Fig. 38), where E ,, the input voltage DAC 19. At the input 13, there is a zero potential, the closing key 20 and the disconnecting key 17, since in this case the logical unit is installed at the output of the NE-22 element. Occurs & capacitor 16 recharge (Fig. 36), small internal resistance of the DAC 19, to a value Uj proportional to Mi, for time 0. Since the voltage 21 | r Oh, then at its output a logical unit of the Gfig is set. 3 b) and the logical element 22 is open. At that moment, when a unit is installed at the input 13 of the GWS, which corresponds to the overflow of the adder 1 (Fig. L), the key 20 is opened and the key 17 is closed, since you are at the element 122, and therefore, at the control input of the key 17 is set zero potential. The generator 18 is turned on and the capacitor 16 is linearly discharged through the generator for a time C, with a discharge current of 1 ii ± R where the proportionality factor is. The voltage on the capacitor 16 during the discharge can be written in the following form AND / L AND 2. E.-Pt Up (thUn - c - 27M-j p-, С is the capacitance of the capacitor where 1b, The capacitor discharge 16. There occurs BEFORE (t) 0.8, this moment at the output of the comparison element 21 is set to zero and a logical unit is set at the control input 17, the key 17 is opened and the discharge of the capacitor 16 is stopped. At that, from the formula (1 discharge time is equal to EZ -M CR. At the time the logical unit is removed from input 13, the recharge and discharge process is resumed. Element 22 produces positive pulses, the interval between the rising edges of which is 4 3) If the output needs to be received; a square wave shape impulses, it is enough to connect a trigger with a counting input, which would be triggered by the rising edge of the pulses from the PLC 12 .. So As the accuracy of the conversion, over a large interval of averaging is determined by the discrete part of the device, then the inaccuracy of the formation of the correction pulse in SHIP 12 will not affect this characteristic, and the accuracy on the small and tervach le averaging will significantly upuchshena. In addition to forming a sequence of output pulses with a period equal to Tgjj, j. While simultaneously operating two code-frequency converters, it is possible to set a delay by two signals at their outputs if the tires on the 5 converters have a number corresponding to the required initial phase. Example: (for the case of a four-bit converter). On the buses of both the transducers, the P0101 number is set) to the tires 5 of the first transducer, the number T 0011 (Sue) is set to the tires 5 of the second Tg 1100 converter (). To shorten the record, the description of the operation of the converters will be kept in decimal terms. In this case, at the initial moment of time, a zero potential acts on the bus 6 and the input buses 5 are connected to the inputs of registers 7. Under the action of the pulses on the bus 8, registers 7 register the numbers 3 and 12, respectively. b from zero to single 0 85728 outputs of multiplexer k are switched from outputs C to outputs of adder 1 and the state of the converters varies according to table 5.

eight

O O 1 O O 1 O

3 8

LZ 2

13 2

7

12

7 12

one

6

T

6

eleven

about 1 about

eleven

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five

about

ten

about about 1 about about 1 about

5 10

15

it

15

four

9 14 9

I

3 8

3

As can be seen from the table, complete; the cycle ends after 2 pulses of: - ow K, after which the initial state is set again. B, for one cycle, at the output of the higher-order carryover, the unit is set P times, with the period D =

one

one

12

15 10

6

one

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four

6

eleven

ABOUT

i o

eleven

one

ABOUT

and

ABOUT

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five

6

ABOUT

five

ten

5 10

I

ten

15 k

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five

12

one

4 11 6

9 14

O 7 2 13 8 3 14

9 1i

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3 8 13 2

one

3

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eight

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13

one

2

7 2 1

ABOUT

9

i

13 8

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7

15

12

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No pulses during a takt takes (values that differ by the amount of one clock IQ.

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In columns 5 and 9 of the table, the underscore: chickpeas are the values that form the values and M; of the correction impulse сh “Let us determine the value Tdp of arbitrary values, for example, K from 12 to 16 in the first transform aarehe. As it was mentioned above, the duration of one intervals should be divided from the tires by the magnitude. In our particular case, Thus, the converter will go to its one state when the high-end transfer unit has a single value ixniuw (U), a at K 15 - the circuit counts 2 values & tn Thus, the value T gbix for the first, v th converter is 3 / fig, and i b, which corresponds to the value tg. A similar value of T, and for the second converter, as. code F spring | is false to both tires 9 (fig. kb and -d). To determine the delay between the outputs, it is necessary to measure the interval between the rising edges of the signals from the transducer outputs. As can be seen from FIG. S II, the delay is 9bt p, which corresponds to; (2 П Thus, the value of the numbers, y-set ≤ lX on tires 5, determines how many utVi intervals a signal with an established initial phase will advance the signal for which T 0 and the difference 2 Tfi determines their mutual delay (Sit - HOMeip converters). Since the value of q If, defining the discreteness of the change in delay is equal to / T, then to set the delay, you must use the formula 4 -Illinjn tj-p to If Tg Tj, the signal with Tj is ahead of the signal with T, and vice versa. i The difference (t g .- Tffli can vary from - (2 - l) to (2 -1), 1 (- 7.% varies from - - Thus, the converter performs linear conversion of the code to the frequency and the conversion is valid at any interval of averaging, as it is provided 1. "2 -5. Same OT equal difference when the multiplexer C is included in the converter, which pre-sets the number T in The register 7 can also be used to delay the signal at any interval of averaging. These properties make it possible to significantly simplify the additional output, filtering and averaging devices necessary for creating tea synthesizers A waveform with a near-sinusoidal waveform, as well as a pulse generator with linear frequency control and with a small dispersion of the tracking period. Approximate economic effect in the implementation of the converter can be 5 thousand rubles per year.

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FIG. 2

Claims (1)

The CODE-FREQUENCY CONVERTER contains the first adder, the first output of which is connected to the first input of the multiplexer, the second input of which is connected to the input bus of the phase setting, the third input is connected to the control bus, and the output through the register, the clock input of which is connected to the clock bus, is connected to the first the input of the first adder, the second input of which is connected to the input bus of the frequency setting, characterized in that, in order to increase the accuracy of the conversion, a second adder, a pulse-width converter and an in ntorov, whose input is connected to the first output of the first adder, and the output ~ to the first input of the second adder, the second inputs of which are connected to the corresponding installation bus of the logic unit, and the output - to the first input of the pulse-width converter, the second input of which is connected to the second output of the first adder, the third input is with the input frequency setting bus, and the output is with the output bus. about »SU (ί» 1048572 1 1048572, 2