SU1522408A1 - Shaft angle digitizer - Google Patents

Abstract

The invention relates to automation and computing and can be used to connect analog information sources with a digital computing device. In order to reduce the dynamic error in the shaft angle converter into a code that contains a pulse generator, a sinusoidal voltage driver, a sine-cosine rotating transformer (SCWT), a switch, a phase-shifting element, a filter, a comparator, an inverter, two triggers, an OR element, three elements And, a pulse counter, a control unit, a time interval code generator, an angle increment code generator, three registers, a multiplication unit, two adders, a prohibition element and a polling bus are entered. At the two switch positions, the output signals of the SCWT are fed to the inputs of the phase-shifting element, as a result of which the instantaneous value of the rotation angle is generated in the counter. In the time interval code generator, a code is generated corresponding to the time interval between the middle of the code generation interval in the counter and the polling pulse. In the angle increment code generator, a difference is generated between the current and previous code values in the counter, which is equivalent to the shaft speed code. In the multiplication unit, the output codes of the two drivers are multiplied, resulting in the release of a dynamic error component that is added to the output counter code. 3 hp f-ly, 2 ill.

Description

Angle increment code 18, registers 19, 20 and 21, multiplication unit 22, adders 23 and 24, prohibition element 25, interrogation bus 26. The control unit 16 comprises a comparator 27, a trigger, 28, elements AND, an impulse counter 31, a decoder 32, impulse drivers 33 and 34. Shaper 17 of the time interval code contains frequency dividers 35 and 36, inverter 37, elements 38 and 39 AND, element 40 OR, pulse shaper 41, counters 42 and 43 pulses. The shaper 18 of the angle increment code contains registers 44 and 45, block 46 of inverters, adder 47..

The Converter operates as follows.

.

The reference voltage U, the sinusoidal voltage driver 2 (Fig. 2, a), whose frequency is 2 times less than the frequency of the pulse generator 1, is supplied to power the sine-cosine rotating transformer 3 and to the comparator 27, which operates when the voltage Uq exceeds zero level The front edge of the output pulse of the comparator 27 sets the B-trigger 28 to state 1. Element 30 And is closed, and element 29 And starts to pass to the input of the counter 31 generator pulses 1. When the counter code changes, the outputs of the decoder 32- pulses. The last time pulse Ug (Fig. 2, b resets the D-flip-flop 28. At this, element 29 And closes, and element 30 And starts to send generator I pulses to the reset input of counter 31. The process repeats with a cycle equal to an integer number of periods eg -.. Uq.

The output signals of a sine-cosine rotating transformer are switched by a two-position switch 4 and fed to a phase-shifting element 5. The switch 4 is controlled by a signal Ug (figure 2, through a pulse shaper 33 of the output voltage Up (figure 2, d) of the phase-shifting element 5 depends on the angle di of rotation of the rotor of the sine-cosine rotating transformer 3, and the phase sign is determined by the position of the switch 4.

Q 5

0

5 s

0

five

The equivalent of the measured angle is taken to be the phase difference of the voltage UpB of the two positions of the switch 4.

Dip converting the phase difference into a time interval, the voltage U. through the filter 6, which blocks the passage of noise, is fed to the comparator 7, which is triggered each time when it exceeds its input voltage of zero. The time interval between the same edges of the output pulses Au (Fig. 2, e) of the comparator 7 in two positions of the switch 4 is proportional to the measured angle oi.

In order to isolate the same edges of the output pulses of the comparator 7, the inverter 8, D-flip-flops 9 and 10, elements 13, 14 I and element P of the FDI are intended. In the initial state, the D-triggers 9 and 10 are reset by the control signal Up and the decoded signal Ug of the element AND OR (FIG. 2, e) has a zero level. After the appearance at the inputs of elements J3, 14 And the control signal UJ-, formed by shaper 34 (FIG. 2, g), elements 13, 14 And otkryshayus, and if the front of the first output pulse of the comparator 7 at time t is positive, D-flip-flop 9 is set to state 1. In this case, element 14 also locks; D-flip-flop 10 is insensitive to signals at its C input, and at output of element 11 of the CID, it can

Q

0

time ment It t II

t set level

By the control signal Ug, the switch 4 is transferred to the second position, and after the control signal reaches the zero level, the positive edge of the first output pulse of the comparator 7 sets the D-flip-flop 9 to the O state at the time t. 11 OR is also set to zero.

If after the occurrence of a signal Ujt; the first is the negative edge of the output pulses of the comparator 7, then the D-flip-flop 10 triggers, and the D-flip-flop 9 remains closed.

In the time interval t - t, the element 12 I is open and the pulses of the generator 1 arrive at the counter 15. If the measured angle ot is a constant value, the code N of the counter 15 is proportional to the measured angle about.

When the shaft rotates, its angular position is measured with a dynamic error L The dynamic error is eliminated as follows.

The counter code 15 is fed to the input of the adder 47. The angle code of the previous conversion cycle is supplied to the other input of the adder 47 via inverter unit 46. The output code UN of the adder 47, proportional to the angular velocity, is written to the register 46 by the control signal Ui (Fig. 2, h). Then, the control signal} (Fig.2, and) records the angle code of the current conversion cycle in register 44.

On the leading edge of the signal Ug, a pulse is generated by the shaper 41, which resets the counter 42. At this, the element 38 AND is opened and the input of the counter 42 through the element 40 OR time clock pulses start from the frequency divider 36 which has a transmission coefficient equal to two. At the moment when the signal Ug ends, element 38 I is closed, element 39 AND opens, and the clock pulses from the .35 frequency divider are sent to the input of counter 42.

The counter code 32 (figure 2, l) at time t is equal to

N,

H

where f is the frequency of the output signals de

letter 35. Upon receipt from the output of the unit

signal u | (Fig. 2, k), fed through the prohibition element 25 to the input of the installation of the counter 43 and the control inputs of the register 20 and 21, the current code of the counter 42 is written to the counter 43, which continuously reads the clock time pulses. In the register 20 from the register 44 the census is with the angle code, and from register 45 to register 21 the AN code equivalent to the angular velocity.

At time t of arrival. 26 of interrogating the signal U. (FIG. 2, n) the prohibition element 25 is closed, eliminating the recording of new codes in the counter 43 and registers 20 and 2, and the time code is recorded in register 19 from the outputs of the counter 43 (FIG. 2, m), proportionally - - 2tc: - te - ti

N,

Code

ten

 , - 15

, 20

25

-

time N from register 19 and code MG, the angle increments per cycle T c conversion from register 21 are fed to the inputs of multiplication unit 22. The output code of block 22 is proportional to the first component of the dynamic error of the converter.

A code N, the angle oL, is fed to the input of the adder 23 from the output of the register 20. The lower bits of the other input of this adder receive the higher bits of the code from the output of register 21. Number. . used low-order bits of the input of the adder 23 is determined by the slope of the phase-frequency characteristics of the filter 6. In the adder 23 is compensated for the dynamic error introduced by the filter 6

H „N, 3 - K & N,

where K is determined by the amount of shift of the high bits of the output code of register 21 at the inputs of the adder 23.

The output codes of multiplication unit 22 and adder 23 are summed at adder 24. The output code of the adder 24 is an output code transforming the bodies and does not contain a dynamic error. This is true if the shaft rotates at a constant angular velocity. With a non-linear change in the angle, an error appears that increases with the conversion cycle. The minimum value of the conversion cycle TC is limited by the time required to calm the transients.

40 reloading the reactive elements of the phase-shifting element 5 and the filter 6 when switching the output voltages of the SCPT 3, in order to obtain a small static error, the time constant 45 of the filter 6. it is necessary to choose as large a value as possible, which leads to the delay of transient processes and, consequently , to the need to increase the cycle of the TC transformation,

50 Thus, when the angle is nonlinear, the limits for the choice of the magnitude of the cycle are limited by the condition of providing acceptable values of static and dynamic errors. Of

Claims (3)

The HS of these considerations selects the transfer factor of the divisor 35. Claims 1, the Converter of the angle of rotation of the shaft in the code containing the generator im30 35 pulses, the output of which is connected to the first inputs of the control unit and the first element I and the input of a sinusoidal voltage maker, the output of which is connected to the input of a sinus-cosine rotating transformer and the second input of the control unit, outputs a sinus-cosine rotating transformer coupled to informational the switch inputs, the switch outputs are connected to the inputs of the phase-shifting element, the filter, the output of which through the comparator is connected to the input of the inverter, the first and second triggers, the direct outputs which are connected to the inputs of the SHI element, and the inverse outputs are connected to the first inputs of the second and third elements, respectively, the output of the OR element is connected to the second input of the first element AND whose output is connected to the counting input of the pulse counter, the first and second outputs of the control unit are connected respectively to the control input of the switch and the installation inputs of the first and second triggers, characterized in that, in order to reduce the dynamic error of the converter, the time code generator the interval is the increment code of the angle increment, three registers, two adders, a multiplication unit, a prohibition element and a interrogation bus that is connected to the control inputs of the prohibition element and the first register, the outputs of the pulse generator, the OR element and the prohibition element are connected to the first, second and third the inputs of the time code generator, the outputs of which are connected by the information inputs of the first register, the third and fourth outputs of the control unit and the group of outputs of the pulse counter are connected respectively the first and second inputs and the group of inputs of the shaper of the increment of the angle code, the first and second groups of slots of which are connected to the information inputs of the second and third registers, respectively, the five output of the control unit is connected to the information INPUT of the prohibition element whose output is connected to the control inputs the second and third registers, the outputs of the first and third registers are connected to the inputs of the multiplication unit. ten 15 20 25 thirty 35 40 45 50 55 the outputs of the second register and the outputs of the higher bits of the third register are connected to the inputs of the first adder, the outputs of which and the outputs of the multiplication unit are connected to the inputs of the second adder, whose outputs are the outputs of the converter, the test output of the control unit is connected to the second inputs of the second and third elements And outputs which are connected to the information inputs of the second and first triggers, respectively, the outputs of the comparator and the inverter are connected to the control inputs of the first and second triggers, respectively, second output controlling unit is connected to the adjusting input of the pulse counter, and the output of the phase-shifting element is connected with the input of the filter. 2. The converter according to claim 1, characterized in that the control unit comprises a comparator, a trigger, two AND elements, a pulse counter, a decoder and two pulse makers, one input of the first element AND and a comparator input are respectively the first and second inputs of the control unit, one input of the first element I is connected to one input of the second element H, the output of the comparator is connected to the control input of the trigger, whose information input is connected to the bus of the logical unit, the forward and inverse outputs of the trigger are connected to others in The signals of the first and second elements And, respectively, the outputs of the first and second elements And are connected respectively to the counting and installation inputs of the pulse counter, the outputs of the bits of the pulse counter are connected to the inputs of the decoder, the first output of the decoder is connected to the input of the first pulse driver, the output of which is the first output the control unit; the second, third, fourth, and fifth outputs of the decoder are the third, third, fourth, and fifth outputs of the control unit, the sixth output of the decoder, respectively; one with a second input of the pulse shaper, which is vkod sixth output of the control unit, and the second output of the decoder is connected to the adjusting input of the flip-flop. 3. The transducer according to claim 1, characterized in that the time interval code generator Fut. , 2