SU1615889A1 - Digital generator - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in devices for generating analog signals of complex shape. The purpose of the invention is to improve the accuracy of the formation of the output signal. The digital generator contains a pulse generator 1, a counter 2 addresses, a storage device 3, a digital-to-analog converter 4, a pulse counter 5, an AND 6 element, a delay element 7 and a counting trigger 8. Introduction of a pulse counter 5, an AND element 6, a delay element 7 and a counting trigger 8 made it possible to increase the accuracy of the formation of analog signals by decreasing the spectral components in the output signal with a frequency of 1 pulse generator. 2 Il.

Description

 FIG. one

The pulse counter 5, the element 6, the delay element 7 and the counting trigger 8 has improved the accuracy of the formation of analog signals for

a decrease in the output signal of the spectral components with a frequency of 1 pulse generator. 2 Il.

This invention relates to an automaton; ike and computing technology and can () be used in devices forming analog signals of a complex law.

The purpose of the invention is to increase the output signal's rotation, i Figure 1 shows the functional diagram of a digital generator; na) ig, 2 - time diagrams, because of the work of the digital oscillator, I Digital generator (fig, 1) contains-) Pulse generator 1, address counter, memory 3, analog converter 4, ft-5 pulse, Element And 6, Element 7 Delay and Counting Trigger 8,

The digital generator (figure 1) works as follows

A functional dependence is preliminarily inserted into the memory device (RAM) 3 as a function of the increments of its values in time. The output signal of the counting trigger Gera 8 sets the operation mode of the counter) and 2 addresses and a counter of 5 pulses, jlycTB, for example, set the sum | u1ir mode. Then, the pulses (Fig. 2a) from generator 1, arriving at the clock input of counter 2 addresses, pull out an increase in the code at its output, and therefore on the address inputs of the charger 3c, if in this memory cell the charger 3 is written The log ,, then the element b and the clock pulse of the generator 1, delayed by the delay element 7 for the time necessary for reading information from the memory 3, is sent to the x input of the pulse counter 5 (fig. 2b), as a result the value of the code at the output of the counter 5 impuces is changed by one, and the voltage to the digital-analogue voltage 4-forming is increased by an amount corresponding to a weight of mpadshe- discharge,

In case j, if in the selected memory cell of memory 3 a level Log is written, 0, then element 6 is closed, the state

five

five

0

five

0

five

0

five

pulse counter 5 and the output voltage of the digital-to-analog converter 4 do not change. Thus, all memory cells of memory 3 are sequentially polled until the last memory address of memory 3 is reached. Since the address width of memory 3 and the address counter size 2 are equal, in this case, the transfer output of address counter 2 is formed LoGr O signal (FIG. 2d), causing switching of the counting trigger 8 (FIG. 2d). The switching of the counting trigger 8 causes the switching of the counting mode of the counter 2 address and the counter of 5 pulses from the summing mode to the subtraction mode.

The next impulse from the output of generator 1 reduces the contents of my address counter 2 by one and removes the transfer signal at its output (fig. 2d). Then the process of decreasing the contents of counter 2 of address continues and, in accordance with the contents of the memory cells of memory 3, decreases and the pulse counter 5, after a corresponding change in the signal level at the output of the digital-analog converter 4. When the zero address of the zero address is reached, one period of output of the digital generator is completed (Fig. 2). ) And counting trigger 8 switches mode of counting in the counters 2 and 5, then the above process is repeated.

The capacity of memory 3 is defined as follows. According to a given periodic function and f (t), the value of the argument t is determined, where the rate of change of the function is maximum. Then, the value of the function f (t) .B is determined to this point and, and an increment is given to the value of and, equal to one discrete output level of the digital-to-analogue converter 4, t, e, and + D + 1 / (2), where k - The size of the digital-to-analog converter A, based on the value of the increment 16

Neither function determines the maximum increment value of the fit argument which causes the function to grow as it is, this will be the value of one discrete for this function, the total number of discretes, and hence the number of memory cells of memory 3, taking into account the reverse operation mode of counters 2 and 5 It is based on the formula p 180 / & tj. The memory capacity of memory 3 is equal to n x 1,

Claims (1)

Improving the accuracy of the formation of the output signal of the digital generator is achieved by reducing the number of changes in the state of the counter 5 pulses, which leads to a decrease in the level of the spectral component with the pulse frequency of the generator 1 in the output signal of the digital generator. The most positive effect is provided by the formation of periodic smooth functional dependencies, the formula of the invention Digital oscillator containing digital analogue converter, output 58896 which is the output pshnoy, pulse generator, the output of which is connected to the clock input of the address counter, the outputs of which are connected to the corresponding inputs of the memory device, characterized in that, in order to improve the accuracy of the output signal, it introduces a pulse counter, a delay element , the element And and the counting trigger, the input and output of which are connected respectively with the transfer output of the address counter and with the inputs of the control of the counting mode of the address counter and the pulse counter, the outputs of the last and which are connected to respective inputs tsifroanalogovo- second transducer element and the output connected to the clock input of counter ten 15 20 pulses, and the first and second inputs connected to the outputs of the memory device and the delay element, respectively, the input of which is connected to the output of the pulse generator,