SU1251329A1 - Pulse frequency-to-digital converter - Google Patents

Abstract

The invention relates to a pulse technique. To a frequency converter containing a reversible counter 8, a delay line 14, a clock pulse generator 1, a pulse distributor 2, four synchronizers 3-6, a switch 10, elements AND 16, 1 8, elements OR 7.9 s, output buses 11, input bus 13, bus Reset 12, in order to expand its functionality, the second 15 and third 17 delay lines and trigger 20 are introduced, the input bus through the second delay line 15 connected to the first input of the first element 16 and to the input of the third delay line 17, the output of which is connected to the first the second element 18 and the bus frequency conversion 19 is connected to a single trigger input mode 20, speed speed conversion 21 is connected to the trigger input of mode 20 trigger, the zero output of which is connected to the second inputs of the first 16 and second 18 elements and the output of the first element and connected with the second input of the fourth synchronizer 6, the output of the second element And is connected to the second input of the second synchronizer 4. 1 Il. With you ate oe to

Description

The invention relates to a pulse technique and can be used in communication systems of computing computers with control objects, in frequency stabilization systems and speed changes of frequency, for processing signals from frequency sensors.

The aim of the invention is to enhance the functionality of the converter by introducing a frequency change rate conversion into the code.

The drawing shows a structural electrical converter circuit.

The converter contains a clock pulse generator 1, the output of which is connected to the input of the distributor 2 pulses, the first four outputs of which are connected to the first inputs of synchronizers 3-6, respectively, the outputs of the first 3 and second 4 synchronizers through the first element OR 7 are polarized to the summing input of the reversible counter 8 , the outputs of the third 5 and fourth 6 synchronizers through the second element OR 9 are connected to the subtractive input of the reversible counter 8, the sign and information outputs of which are through the switch I O is connected to the OUTPUT buses 1, the control input of the switch 10 is connected to the fifth output of the distributor 2, the bus 12 Reset is connected to the installation input of the reversing counter 8, the input bus 13 is connected to the second input of the first synchronizer 3, through the first delay line A to the second the input of the third synchronizer 5 and through the second delay line 15 - with the first input of the first element I 16 and with the input of the third line

17 delays, the output of which is connected, is connected to the first input of the second element I 18, Eina Frequency conversion 19 is connected to the zero input of the mode trigger 20, the conversion speed bus 21 is connected to the single input of the mode trigger 20, the single output of which is connected to the second inputs of the first I6 and second

18 And elements, the output of the first element And 16 is connected to the second input of the fourth synchronizer 6, the output of the second element And 18 is connected to the second input of the second synchronizer 4.

Synchronizers 3-6 carry out a temporary binding of pulses to fixed points in time and can be implemented according to well-known schemes. The converter works in the following way.

V.Reg5me Frequency conversion converter works similarly to the prototype. At the initial moment of time

a signal is simultaneously given

to pin frequency conversion

19 and the initial setup signal to reset the I 2,

The initial setup signal is supplied with a duration longer than the delay time in the first delay line 14, for its complete zeroing. Trigger

The 20 modes are set to the zero state, and the And 16 and 8 elements for

0 covered After the termination of the signal Reset the reversible counter 8 will begin to sum up to the pulses of the frequency being converted, coming 1e from the input 3 to its totalized input

5 After the first synchronizer 3 and the first element I-tllH 7. Through the delay time in line 14 of the delay to the computing input of the reversible counter 8 through the third synchronizer 5 and

0 the second element OR 9 will begin to receive the impulses of the frequency being converted from the bus 13 and at the input frequency unchanged on the reversible counter 8 will be added and subtracted

5 the same tslslo imzulsov. The readings of counter 8 will not change and will correspond to the input frequency. With an increase in the input frequency readout counter reading

Q 8 will increase and decrease with decreasing, i.e. the reversible counter 8 will continuously monitor the input frequency value, With the help of a clock generator,

5, the distributor 2 pulses, the synchronizers 3 and 5, and the switch 10 are separated in time between the counting moments on the reversible counter 8 and the counting moments from

tQ information on the output bus 11,

In the mode Converting speed, the converter performs a continuous conversion to the speed code for changing the input frequency. For this purpose, on the Speed conversion bus 2, a mode setting signal is given, mode trigger 20 is set to unit state 31

elements 16 and 18 are uncoupled. At the same time, Reset 12 is given an initial setup signal with a duration of 6 times the total delay time in delay lines 15 and 17 for complete cleaning. The input frequency from the bus 13 through the first synchronizer 3 and the first element OR 7 is fed to the summing input of the reversing counter 8, which, after the end of the signal Reset begins to count the input pulses. Through the delay time in the 14 and 15 delay lines, provided that they are equal simultaneously on two lines, i.e. at double the frequency with respect to the input frequency, pulses will begin to flow to the subtracting input of the reversible counter 8, which, moreover, at one time, the delays are nullified. By this time, i.e. after two delay times, the input frequency of the reversing counter 8 also receives a doubled input frequency, as well as a subtracting input.

Thus, the zero state of the counter 8 is preserved. The code at the output of counter 8 is additional, therefore the zero state of counter 8 corresponds to the absence of the rate of change of the input frequency. Positive code values correspond to an increase in frequency, and negative values -. NIN - decrease the frequency. From the above, it can be seen that at any constant input frequency at the output of counter B in the steady state, i.e. after two delay times, there will always be a zero code.

Now consider the operation of the converter with a constant increase in the input frequency, i.e. at a constant positive rate of change. In this case, the reversible counter 8 should show a constant positive value corresponding to the given rate of change of frequency. Indeed, if the input frequency increases all the time, the difference between the input frequency and its delayed value, i.e., will remain constant all the time. the frequency difference between the frequency and the frequency at the output of the delay line 15 will be constant. Further, this frequency difference is continuously converted into a code. Input difference conversion

329.4

delayed and delayed frequencies using two delay lines 14 and 7 and a reversible counter 8, the input frequency directly supplied to the summing input of counter 8 and, through the delay time in delay line D, to the subtracting input of counter 8, and delayed in delay line 15 input frequency: directly fed to the subtracting input of the counter 8 and after the delay time in the delay line I7 - to the summed 1 input of the counter 8 f Readout-reversing counter 8 continuously monitor the value of the difference of the input frequency and its delayed wow value Moreover, the sign code of the reversible counter 8 corresponds to the sign of this frequency difference. Thus, the greater the rate of change of frequency, the greater the difference between the frequency itself and its delayed value, i.e., the readings of counter 8 continuously dissipate the rate of change of the input frequency. In this case, the sign of the code corresponds to the sign of the rate of change of frequency, i.e. when the frequency is increased, the sign of the output code is positive, and when decreasing, it is negative.

The development of frequency hopping, when the rate of change of frequency is infinitely large, takes place after a time not exceeding the total delay time s lines 15 and 17 of delays, and is limited by the capacity of the reversing counter 8.

Thus, the functionality of the proposed converter is expanded in relation to the prototype by introducing a conversion mode into the code of the rate of change of frequency. In this case, the frequency conversion to the code and the speeds of the frequency change to the code are performed on the same reversible counter, and both conversion modes are carried out continuously, which makes it possible to eliminate the time reference of the conversion points.

Claims (1)

Invention Formula A pulse frequency converter into a code containing a clock pulse generator, the output of which is connected to the distributor impulse input, the output signals of which are connected to the first inputs of four synchronizers, respectively, the first and second synchronizers output through the first I.PI element connected to to the summing input of the reversible counter, the outputs of the third and fourth synchronizers through the second element OR are connected to the subtractive input of the reversible counter, the sign and information outputs of which are The switch is connected to the output buses, the switch control input is connected to the fifth output of the pulse distributor, the reset bus is connected to the installation input of the reversible counter, two AND elements, the first delay line, in order to expand the functional potential of the switch , the second and rpo / ri ft delay lines and the trigger of the mode are introduced, the trunk bus is connected to the second input of the first synchronizer and through the first delay line to the second input of the third synchronizer, and through the second delay line from the first m input of the first element And with the input of the third delay line, the output of which is connected to the first input of the second element, the bus frequency conversion is connected to the single input of the mode trigger, the bus speed conversion is connected to the zero input of the mode trigger, the zero output of which is connected to the second inputs of the first and The second element And, the output of the first element And connected to the second input of the fourth synchronizer, the output of the second element And connected to the second input of the second synchronizer.