SU1418906A2 - Frequency-to-number converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in communication systems of computers with control objects for processing signals from frequency sensors. The purpose of the invention is to expand the functionality. To do this, in the frequency converter in the code containing the trigger mode 1, the clock generator 2, the frequency divider 3, the distributor 4, the first to fourth elements And 4-8, the first and

Description

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the second synchronizers 13, 14, the first counter 23, the first switch 26 and the first delay element 29, allowing, depending on the mode, to convert either the frequency or the period of this frequency into the code, entered from the fifth to the eighth elements 9-12, the third and fourth synchronizers 15 and 16,

The invention relates to a pulse technique, can be used in communication systems of computers with control objects, in frequency stabilization systems, for processing signals from frequency sensors, and is an improvement of the device according to

The purpose of the invention is to enhance the functionality by introducing the conversion of the period difference and the frequency difference into a code.

The drawing shows the structures - on the converter circuit.

The converter contains trigger 1 mode, clock generator 2, divider 3 frequencies, distributor 4 pulses, first through eighth elements AND 5-12, first through fourth synchronizers 13-16, first through sixth elements OR 17-22, first, second and the third reversible counters 23-25, the first, second and third switches 26-28 and the first and second delay elements 29-30.

The converter works as follows.

In the conversion mode to the code of two frequencies and their difference, a signal is sent to the bus Frequency, the trigger 1 of the mode is set to the zero state. A reset signal is sent to the Reset bus with a duration exceeding the maximum delay time of the first 29 or second 30 delay elements dp of their complete cleaning. Upon termination of the signal on the bus. Reset, continuous conversion into the frequency code of the pulses arriving at the input conversion into the difference code of the frequencies begins. Converting the third to sixth elements OR 19-22, the second and third counters 24 and 25, the second and third switches 27 and 28, and the second delay element 30 to the frequency code that arrives at the first input shis, which allows you to further convert the difference between the periods and frequency with the development of the sign of the difference, 1 Il.

well, is performed using the first delay element 29 and the first reversible counter 23, the frequency supplied to the second input bus using the second delay 30 and the third reversing counter 25, and the difference of these frequencies with the difference sign

29 and the second 30 delay elements and the second reversible counter 24, B

In this mode, the trigger 1 of the mode is set to the zero state and the elements AND 5, 7, 10, and 12 are open. The first frequency from the first input bus through

the open element And 7, the element OR 17 and the synchronizer 13 is fed to the summing input of the reversible counter 23 and the same frequency through the element 29 of the delay and the synchronizer

14 is fed to the subtracting input of the reversible counter 23; The clocking frequency to the delay element 29 is supplied from the clock generator 2 through the open element AND 5 and the element OR 18, information is removed from the counter 23 by means of the switch 26; Regardless of the first frequency, the second frequency is second input bus through the open element and

10, the element OR 19 and the synchronizer 15 are fed to the summing input of the reversible counter 25 and the same frequency through the element 30 of the delay and the synchronizer 16 is fed to the subtracting input of the reversible counter 25. The clock frequency per element

30 delays come from the clock generator 2 through the open element And 12 and the element OR 20, the information from counter 25 is removed using the switch 28. In addition to receiving codes proportional to two

the input frequencies on the reversible counter 2A generates a code proportional to the difference of these frequencies, since the summing input of the reversible counter 24 from the synchronizer 13 through the OR 21 element receives the first frequency and from the synchronizer 16 delayed by the delay element 30 the second frequency and its subtracting input from the synchronizer 15 through the element OR 22 enters the second frequency and from the synchronizer 14 delayed at the element 29 of the delay the first frequency. Dp of obtaining the sign of the difference, the code of the reversible counter 24 is selected additional. The removal of information from the counter 24 is performed using the switch 27.

In the conversion mode, the period code and period difference signal is sent to the bus. The period sets (trigger 1 of the mode to one state and elements 6 and 8, 9 and 11 are opened). The converter starts on the trailing edge of the bus signal Reset. The first frequency from the first input bus through the open element AND 8 and the element OR 18 enters the clock input of the delay element 29, and the second frequency from the second input bus through the open element AND 1I and the OR element 20 enters the clock input of the delay element 30. At the input element 29 delay through the open element AND 6 and the element OR 17 and the input element of the delay element 30 through the open element AND 9 and the element OR 19 enters the clock frequency of the generator 2 divided by the frequency divider 3. Thus, the summing input of the reversible counter 23 through the synchronizer 13 and the summing input of the reversible counter 25 through the synchronizer 15 receives the clock frequency from the divider 3 frequencies, and the subtractive input of the reversible counter 23 from the output of the delay element 29 through the synchronizer 14 receives the first input frequency and to the subtractor 1st the input of the reversible counter 25 from the output of the delay element 30 is fed through the synchronizer 16 to the second input frequency; therefore, a code proportional to the period of the first frequency from the first input bus is generated on the counter 23, and a code is generated on the counter 25

proportional to the period of the second frequency from the second input band.

The conversion of the period difference into a code is performed using the first 29 and second 30 delay elements and the reversible counter 24 simultaneously with the conversion to the code of the periods of two frequencies. The summed input of the reversible counter 24 via the OR element 21 from the synchronizer 13 receives the clock frequency from frequency divider 3 and from the synchronizer 16, the frequency from the frequency divider 3 delayed on delay element 30. The subtracting input of the reversible counter 24 through the OR element 22 from the synchronizer 15 receives the clock frequency from the divider 3 frequencies and from the synchronizer 14, the frequency delayed by the delay element 29 from the divider 3 frequencies. The non-delayed pulses from the divider 3 frequency do not affect the readings of the reversible counter 24,

5, since they are added and subtracted with the same frequency on this counter. Only the pulses coming from delay elements 29 and 30 have an effect on the meter 24.

As the delay times in these elements are so controlled by the input frequencies in the input layers. With equal frequencies on these tires in elements 29 and 30, the delay time is the same and the counter is 24-zero. When the frequency period on the first input bus is less than the frequency period on the second input bus, the delay time in the delay element 29 is shorter than the delay time in the delay element 30, therefore, more counts are fed to the subtracting input of the reversible counter 24 than on its summation the input and counter readings 5–24 will be negative and directly proportional to the difference in the periods. When the period of the frequency on the first bus input is greater than the period of the frequency on the second input bus, the delay time Q in the delay element 29 is longer than the delay time in the delay element 30, therefore, the summing input of the reversing counter 24 receives more pulses than its SP deducting the input and counter readings are 24 positive and directly proportional to the difference of the periods. The generation of the period difference code on the counter 24 is due to this.

that the delayed clock pulses from the divider 3 from the output of the delay element 29 controlled by the first input frequency are sent to the subtracting input of the reversible counter 24, and the same clock pulses from the divider 3 from the output of the delay element 30 controlled by the second input PURITY are fed to the summing the reverse counter code 24, i.e. on the reversible counter 24, a code proportional to the period of the second input frequency is continuously subtracted from the code proportional to the period of the first input frequency. At the same time, the sign of the reversible counter code 24 is positive when the frequency on the first input bus is higher than the frequency on the second input bus in frequency conversion mode, and also positive when the frequency period on the first input bus is greater than the period period on the second input bus in period conversion mode. The magnitude of the delays in the elements 29 and 30 of the delay should be equal. Frequency divider 3 is used in the period conversion mode in order to ensure that the clock frequency of the delay element is always exceeded over the frequencies at the inputs of the delay elements in order to eliminate the suppression of information pulses moving along the delay elements.

The signal from the third output of the distributor 4 is fed to the control inputs of the switches 26-28 and implements (the codes are read from the reversible counters 23-25 to the output buses at times when the inputs of the counters 23-25 do not have input pulses.

Claims (1)

Invention Formula Frequency converter to auth code St. No. 1229959, characterized in that, in order to extend the functionality by converting the difference of frequencies and periods into a code, the fifth, sixth, seventh, and eighth elements of AND, the third, fourth, fifth, and sixth elements of OR, the third, and the fourth synchronizers, the second element of VNIIPI Order 167/56 five Q 0 five 0 five 0 five five delays, second and third reversible counters, second and third switches, the outputs of which are the outputs of the difference and the second output bus, respectively, and the information inputs connected to the corresponding outputs of the second and third reversing counters, respectively, the summing input of the second reversible counter , the first input of which is connected to the output of the first synchronizer, and the second is combined with the summing input of the third reversing counter and connected to the output of the third synchronizer, the first input of which through the second delay element is combined with the first input of the fourth synchronizer and connected to the output of the fourth OR element, the first and second inputs of which are connected to the outputs of the fifth and sixth elements AND, respectively, the first inputs of which are combined with the first inputs of the seventh and eighth elements And, respectively, and are connected to the first and second outputs of the mode trigger, respectively, the second input of the fifth element And is connected to the output of the frequency divider, the second input of the sixth element And the volume The second input of the seventh And element is the second input bus, the second input of the eighth And element is combined with the input of a frequency divider, and the output is connected to the first input of the fifth OR element, the second input of which is connected to the output of the seventh And element, and the output is the clocking input of the second delay element, the second input of the third synchronizer is connected to the fourth output of the pulse distributor, the first output of which is connected to the control inputs of the second and third switches, and the fifth output is connected to the second input quarter synchronizer, the output of which is connected to the subtractive input of the third reversible counter and the first input of the sixth OR element, the second input of which is connected to the output of the second synchronizer, and the output to the subtractive input of the second reversible counter, which zero input combined with the zero input of the third reverse counter connected to bus reset. Circulation 928 Subscription