SU1238222A1 - Rulse frequency multiplier - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in automation and measuring devices. The purpose of the invention is to improve the measurement accuracy: - it is achieved by introducing into the multiplier a second logic element (LE) I 7, a differential frequency driver 9, a control unit 11 and an initial setting bus 12. In addition, the multiplier contains a reversible counter 1, a counting unit 2, tires — an output 3 and a multiplying frequency 10, a frequency divider 4, a pulse generator 5, the first LE AND 6, LE OR 8. In the counting block 2, there is an element 13 of the comparison code, a pulse counter 14 and a pulse shaper 15. The composition of the differential frequency generator 9 and the control unit 11 is shown in the functional diagrams provided in the description of the invention. This frequency multiplier steadily works in the range of multiplied frequencies, bounded below by the magnitude Pwhmin-fni / K and above Fex.Mat «; fm / 3K, where f gi - the frequency of the pulses of the generator 5; K is the division factor of divider 4. The frequency of occurrence of phase fluctuations at the output of the multiplier at the maximum input frequency is 3 times smaller than the prototype and at the minimum input frequency is less than K times. 1 hp f-ly, 3 ill. u (L y 00 00 y 1C y

Description

The invention relates to a pulse technique and can be used in automation and measuring devices.

The aim of the invention is to improve the accuracy.

FIG. 1 shows the electrical structural diagram of the device; in fig. 2 is an electrical functional circuit of a differential frequency driver; in fig. 3 is an electrical functional circuit of the control unit.

The pulse frequency multiplier contains a reversible pulse counter 1, the outputs of which are bitwise connected to the code inputs of the counting unit 2, the output of which is connected to the output bus 3, the divider 4 frequencies, the generator of 5 pulses, the output of which is connected to the first inputs of the first and second elements 6 and 7 And, the output of the first of which is connected to the first input of the element 8 OR, the differential frequency driver 9, the first input of which is connected to the bus 10 of the frequency to be multiplied and the first input of the control unit 11, the second input to the output of the splitter 4 part Ata, the reset input of which is connected to the reset input of the reversible counter of pulses 1 and the first output of control unit 11, the counting input with the output of element 8 OR, the second input of which is connected to the output bus 3, and the reset input of the counting unit 2, whose counting input connected to the output of the second element 7 AND, the second input of which is connected to the second output of the control unit 11, the third output of which is connected to the second input of the first element 6 AND, the fourth output to the third input of the differential frequency generator 9, the first and second outputs of which on respectively connected to a control and counting inputs of a reversible counter 1 pulse, the third output - to a second input of the control unit 11, a third input coupled to the bus 12, the initial installation.

The counting unit 2 consists of a code comparison element 13, a pulse counter 14 and a pulse driver 15, the output of which is connected to the output of the counting unit 2, the input is connected to the output of the code comparison element 13, the first and second groups of inputs of which are connected one by one respectively to the code input of the counting unit 2 and with the outputs of the counter 14 pulses, the counting input and the reset input of which are connected to the same inputs of the counting unit 2.

Shaper 9 differential frequency contains two inverters 16 and 17, three trigger 18, 19 and 20, three elements AND NOT 21, 22 and 23 and the element OR NOT 24, and the first input 25 of the former 9 is connected to the first input of the first element AND- HE 21, with the R inputs of the first and second triggers 18 and 19 and through the first inverter 16 with the C input of the third trigger 20, the direct output of which is connected to the second

the input of the first element AND-NOT 21, the output of which is connected to the first input of the second element 22 AND-NOT, the second input of which is connected to the output of the third element 23 5 AND-NOT, with the C-input of the second trigger 19 and the first input of the element 24 OR- NOT, the second input of which is connected to the inverse output of the second trigger 19, the D input of which is connected to the first output 26 of the driver 9, to the direct output of the first trigger 0 18 and to the first input of the third AND-23 element, the second input of which is connected to the second input 27 of the driver 9, with the R-input of the third trigger 20 and through the second The second inverter 17 has a C input of the first trigger 18, the inverse output of which is connected to the D input of a third trigger 20, the inverse output of which is connected to the D input of the first trigger 18, the S input of which is connected to the third input 28 of the racer 9 and the third input of element 24

20 OR NOT, and the second 29 and third 30 outputs of the imaging unit 9 are connected to the outputs, respectively, of the second element 22 AND-NOT and element 24 OR-NOT.

The control block 11 (Fig. 3) contains an element 31 AND-NE, two elements 32 and 33

 OR NOT, two elements 34 and 35 OR, two triggers 36 and 37, inputs 38, 39 and 40 are the first, second and third inputs of the control unit 11, respectively, the first, second, third and fourth outputs of which are outputs 41, 42, 43 and 44, with the first input 38 being connected to the first input of the first element 32 OR — NOT and to the first input of the element 31 NAND, the output of which is connected to the C inputs of the first and second triggers 36 and 37 and to the first the input of the second element 33 OR-NOT, the output of which is connected to the first output 41, the second input to the second output 42, to the first input the house of the first element 34 OR, the second input of which is connected to the output of the second element 35 OR, the first and second inputs of which are connected respectively to the second and third inputs 39 and 40, and to the R input of the first trigger 36, the D input of which is connected to the third the input of the second element 33 OR-NOT, with the third output 43 and with the direct output of the second trigger 37, the D-input of which is connected to its inverse output and to the second input of the first element 32 OR-NOT whose output is connected to the fourth output 44 , R-input of the second trigger 37 is connected

cQ with the output of the first element 34 OR, and the inverse output of the first trigger 36 is connected to the second input element 31 AND-NOT. The pulse frequency multiplier works as follows.

The device is reset to the initial state by a pulse of the initial installation (INU) arriving at the second input of the block 11 via the bus 12. At the same time, zero levels are set at all outputs of the block 11. Elements b and 7 are closed, and the generator 5 pulses do not pass to the inputs of unit 2 of element 8. On the output bus 3, there are no multiplied frequency pulses.

The first input pulse of the multiplied frequency, which enters bus 10, passes to the first output of block 11, the zero divider 4 and counter 1 are set to zero. On the falling edge of the first input pulse, unit levels are set at the third and fourth outputs of block 11. The first of them opens element 6 to pass pulses from the output of generator 5 to the input of element 8, and the second maintains a unit level at the first output of driver 9, which ensures the operation of counter 1 in the mode of counting pulses, while the device operates in the mode of measuring the following period input frequency pulses.

The pulses of the generator 5 through the element 8 are fed to the input of the divider 4 and to the reset input of the block 2, set the counter 14 of the block 2 to zero. At the output of block 2, there are no pulses, from the output of divider 4, the pulses go to the second input of the imaging unit 9 and from the second output of the last to the counting input of counter 1. The division factor of divider 4 is chosen equal to the multiplication factor of the device, therefore for one period of the frequency to be multiplied the arrival of the second input pulse bus 10) to the input of the counter 1 receives the number of pulses

 gi r

- -J7- 1 in, IV

where GGI - the frequency of the pulse generator 5; K - division factor of divider 4;

Tvh - the period following the input pulses.

Thus, by the time the second pulse of the second pulse arrives at the first input, the counter 1 is recorded with a certain drawback, the period followed by the multiplied frequency pulses in the binary code.

On the trailing edge of the second input pulse, coming through bus 10, zero levels are set at the third and fourth outputs of block 11, and a single level is set at its second output. Thus, starting from this moment, the pulses of the generator 5 pass to the counting input of the block 2 and do not pass to the first input of the element 8. The zero level at the fourth output of the block 11 transfers the driver 9 to the frequency subtraction mode. The pulse frequency multiplier goes into multiplication mode.

If the first input of the imaging unit 9 receives another two input pulses, between which no pulse from the output of the divider 4 has passed, then the first output of the imaging device 9 will be zero, and at its second output it will appear

0

five

pulse decreasing the contents of counter 1 by one.

If from the output of divider 4 to the second input of the imaging unit 9, another two 5 impulses are received, between which none of the input pulses have passed, then the first output of the imaging equipment 9 will have a unit level, and at its second output there will appear an impulse increasing the counter 1 per unit. At the output of block 2, an impulse appears each time when the contents of counter 1 and the contents of counter 14 of block 2 coincide in magnitude. These pulses go to the bus 3 of the device through element 8 — to the counting 5 input of the divider 4 and to the reset input of the block 2, setting the counter 14 to the zero state. Thus, the system consisting of the counter 1, the divider 4, the driver 9, is a closed loop of automatic frequency control on bus 0 (under the influence of input pulses coming in the first input of the driver 9).

If the second input of the imaging unit 9 receives another sequence of three pulses from the output of the divider 4, between which none of the input pulses passed, then the third output of the imaging unit 9 has a pulse arriving at the second input of the block 11 and operating similarly to the IGU. and the whole frequency multiplier p of pulses to the initial state. In addition, the driver 9 is two-step in principle. At its first input 25, the input multiplied frequency of the Fax is received. On the leading edge of each FBX pulse, the flip-flops 18 and 19 are set to zero, and on the trailing edge of this pulse, the trigger 20 is set to one. If, prior to the arrival of the next FBX pulse, the next pulse from the output of divider 4 does not arrive at input 27, then this second pulse FBX through the open element 21 and in series with it the connected element 22 passes to the second output 29 of the driver 9 and enters the counting input of the counter 1, reducing its content by one, since at this moment at the output 26 of the imaging unit 9 5 there is a zero level providing the subtraction mode at the control input of the counter 1.

If the input 27 of the imager 9 receives two additional pulses from the output of generator 4, between which not a single pulse of the input multiplied frequency FBX passed, then, similarly to the one described above, the first one of them sets “O flip-flop 20” to its The back-front translates trigger 18 into “1. 5 The second pulse of divider 4 through series-connected elements 23 and 22 passes to output 29 of generator 9, increasing by one the contents of counter 1, since at output 26 of generator 9 at this moment there is a single level ensuring the operation of counter 1 in summation mode. At the same time, this second impulse from the output of the divider 4, with its falling front, sets to “1 trigger 19.

If by the moment of arrival at the input 27 of the third pulse from the output of divider 4 to

Rvhmaks. At the same time, the frequency of occurrence of phase fluctuations at the output of the proposed multiplier with a maximum input frequency is 3 times less in comparison with the prototype and with a minimum input frequency - less than K.

Claims (2)

Claims 1. Pulse frequency multiplier, co15 the input 25 of the imaging unit 9 is still not 10 holding a reversible pulse counter, no impulse input frequency will come FBX, then this third pulse passes on output 29 shaper 9 and, moreover, through element 24 (in multiplication mode) passes to exit 30 shaper 9, the drive unit 11 to its original state, similar to inu. Thus, the presence pulse output 29 shaper 9 there is a sign that 1 piece 2gvh. This feature in the device is used by JQ as the end of the FBX burst input signal. A single level is fed to the input 28 from the output of block 11 in the period measurement mode of the multiplied frequency FBX and the zero level in the frequency multiplication mode. The unit level holds in one state the trigger 18 of the generator 9 in the measurement mode of the input frequency period Rin, providing the first output 26 of the generator 9 to a unit level and closing element 24 on one of the inputs. Thus, the pulses from the output of the divider 4 in the mode the measurements are passed from the input 27 through the element 23 and the element 22 to the output 29 of the generator 9 and then to the counting input of the counter 1, at the control input of which there is a single level, providing 35 summation mode. Upon the arrival of the second input pulse Pw, the measurement mode is terminated, the trigger 19 is set to the zero state, and at the input 28 of the imaging unit 9 a zero level is set. Q In multiply mode, the differential frequency shaper operates as described above. Consideration of the operation of the imaging unit 9 shows that its output 29 is the output of the signals of the difference frequency — Vdel - - Rvc; its output 26 is the output of the sign of this difference frequency. Indeed, if affairs - Rvh O, then at the exit 26 there is a single level. On the contrary, if Gdel is Rvh; o, then at the exit 26 the zero level takes place. Finally, if it is 2Px, then an output signal appears at its output 30, carrying this feature. Thus, a pulse frequency multiplier ensures stable operation in the range of multiplied frequencies, whose outputs are serially connected to the code input of the counting unit whose output is connected to the output length, frequency divider, pulse generator whose output is connected to the first input of the first element I, output which is connected to the first input of the OR element, and a frequency multiplying bus, characterized in that, in order to improve accuracy, an initial installation bus, a second AND element, a control unit and a frame are inserted into it differential frequency equalizer, the first input of which is connected to the bus of the frequency to be multiplied and to the first input of the control unit, the second input to the output of the frequency divider, the reset input of which is connected to the reset input of the reversible pulse counter and the first output of the control unit OR, the second input of which is connected to the output bus, and to the reset input of the counting unit, the counting input of which is connected to the output of the second element AND, the first input of which is connected to the output of the pulse generator, the second to the second the output of the control unit, the third output of which is connected to the second input of the first element I, the fourth output - to the third input of the differential frequency former, the first and second outputs of which are connected respectively to the control and counting inputs of the reversible pulse counter, the third output - to the second input of the control unit , the third input of which is connected to the bus installation. 2. A multiplier according to claim 1, characterized in that the differential frequency driver contains two inverters, three triggers, three AND-NOT elements and an ILI-NE element, the first input of the differential frequency shaper connected to the first input of the first AND-NOT element, with The R inputs of the first and second triggers and through the first inverter with the C input of the third trigger, the direct output of which is connected to the second input of the first AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the second input of which is connected to the output of the third element AND- NOT, with С the input of the second trigger and the first input of the element OR NOT, the second input of which is connected to the inverse output of the second trigger, the D input of which is connected to the first output of the differential frequency former, to the direct output of the first 45 50 55 Mr. bottom value Rvhmin and top Rvhmaks. At the same time, the frequency of occurrence of phase fluctuations at the output of the proposed multiplier with a maximum input frequency is 3 times less in comparison with the prototype and with a minimum input frequency - less than K. Claims 1. A pulse frequency multiplier comprising a reversible pulse counter, five Q 5 5 Q the outputs of which are bitwise connected to the code input of the counting unit, the output of which is connected to the output length, a frequency divider, a pulse generator, the output of which is connected to the first input of the first AND element, the output of which is connected to the first input of the OR element, and a frequency multiplier, different By the fact that, in order to increase the accuracy, the initial setup bus, the second element I, the control unit and the differential frequency generator, the first input of which is connected to the frequency bus and to the first input of the control unit, are entered into it. The second input is with the output of the frequency divider, the reset input of which is connected to the reset input of the reversible pulse counter and the first output of the control unit, the counting input is connected to the output of the OR element, the second input of which is connected to the output bus, and the counting input of which is connected to the output of the second element I, the first input of which is connected to the output of the pulse generator, the second to the second output of the control unit, the third output of which is connected to the second input of the first element I, the fourth output to the third input of the difference frequency, the first and second outputs which are respectively connected to the control and counting inputs of the reversible pulse counter, the third output - to a second input of the control unit, a third input coupled to the bus initial installation. 2. A multiplier according to claim 1, characterized in that the differential frequency driver contains two inverters, three triggers, three AND-NOT elements and an ILI-NE element, the first input of the differential frequency shaper connected to the first input of the first AND-NOT element, with The R inputs of the first and second triggers and through the first inverter with the C input of the third trigger, the direct output of which is connected to the second input of the first AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the second input of which is connected to the output the third element AND- NOT, with С the input of the second trigger and the first input of the element OR NOT, the second input of which is connected to the inverse output of the second trigger, the D input of which is connected to the first output of the differential frequency former, to the direct output of the first five 0 five trigger and with the first input of the third element AND-NOT, the second input of which is connected to the second input of the differential frequency former, with the R input of the third trigger and through the second inverter with the C input of the first trigger, the inverse output of which is connected to the O input of the third trigger, the inverse output of which is connected to the D input of the first trigger, the S input of which is connected to the third input of the differential frequency former and the third input of the OR-NOT element, while the second and third outputs of the differential frequency former are connected to the outputs corresponding to correspondingly to the second element NAND and the element ORNE. 25 (pus.Z