SU930687A1 - Majority-redundancy rate scaler - Google Patents

Description

(54) MAJORITY-RESERVED DIVIDER OF THE FREQUENCY OF FOLLOWING THE PULSES

I

The invention relates to a pulse technique and can be applied in digital systems of automation, data transmission, communication, time storage, mainly at the highest demands, to their reliability, speed, and stability of the phase of the output pulses.

A device for dividing a sequence of pulses is known, which contains three channels of division, each of which consists of a majority element and series-connected iT flip-flops.

The disadvantage of this device is limited speed.

The closest in technical essence to the invention is the majority-redundant follower frequency multiplier, containing N division channels, each of which consists of L / series-connected triggers, the counting input of the first of which is connected to the input bus of the majority element, whose input connected to; the output of the last trigger of this

Nala and the same inputs majoritarian. elements of the remaining channels, and the output / stroke - with the first input of the coincidence element of the same channel, the second input of which is connected to the output of the last trigger, and the output with the installation inputs of the previous triggers and additional majority elements and elements of the match 2.

A disadvantage of the known device 10 is the limited speed with low phase stability of the output pulses.

The purpose of the invention is to increase the device speed and the phase stability of the output pulses.

ts

To this end, a major-preserved pulse frequency divider containing N division channels, each of which consists of a pulse counter, the counting input of which is connected to the input bus and the majority element, the corresponding input of which is connected to the output of the pulse counter of this division channel

and with the same inputs of the major elements of its division channels, and the output with the first input of the matching element of the same channel, a channel non-phase analyzer is introduced, each of the N inputs of which is connected to the same inputs of the majority elements, and the output with the outputs of the matching all channels of the division the second inputs of which are connected to the input bus, with the installation inputs of the pulse counters of all division channels and with the reset input of the channel non-phase analyzer.

The drawing is a block diagram of the device.

It contains a channel non-phase analyzer 1, counters 2-1-2-1 impulses, majority elements 3-1-3-N, matches 4-1-4-N,

Figures 5 and 6 denote the input and output tires.

The analyzer 1 is reset by the output pulse of the device simultaneously with the preset division factor. Consider the operation of the device under the following conditions:

- full skew (phased M or more channels, where M is the threshold of majority elements 3-1-3- {0;

-particle dephasing (phasic (M - 1) or less channels);

- lack of skew.

In the case of absence or partial channel skewing, input pulses from bus 5 are fed to the inputs of all N division channels. In the counter 2 of each bundle, the division factor K is set. In counters 2-1-2-N, the state preceding the counting is recognized. When this state is reached, the majority of the division channels at the outputs of the major elements 3 appear, which is fed to the first input of the matching element 4 of this channel. The next count pulse from the bus 5 passes through the elements 1 4-1-4-N to the output bus 6 of the device, the installation inputs of the counters 2-1-2-M and to the reset input of the analyzer 1. In this case, the analyzer does not affect the operation devices.

Suppose that a complete skew of division channels has occurred. In this case, there will be no state at the inputs of the majority elements 3-1-3, in which a signal appears at its outputs. Such a state can be observed. gj the moment the device is turned on or

failure x more than (M - 1) channels. Then, as the counters 2-1 - 2-N input pulses arrive at the inputs, the state preceding the count

However, the outputs of these counters are recognized at different times. The input of the analyzer 1 pulses. The output pulse of the analyzer 1 is fed to the installation input of the counters.

2-1 - 2- N and to the analyzer reset input 1. Further operation of all division channels will be in phase.

From consideration of the operation of the device, it follows that the output impulse of the device undergoes a delay in only one element of the match, and therefore the speed of the device is determined by the speed of the low-order counter cell, and the instability of the delay

equal to the instability of the response delay of only one match element.

Formula of invention

The major backup pulse frequency divider containing N division channels, each of which consists of a pulse counter, the counting input of which is connected to the input bus, and a major element, the corresponding input of which is connected to the output of the pulse counter of the division channel and the same elements of the remaining 1 dividing channels, and the output with the first input of the coincidence element of the same dividing channel, characterized in that, in order to increase the device’s speed and stability and the phases of the output pulses, it introduced not-in-phase analyzer channels, each of the K input of which is connected with, the majority of elements of the same name input, and an output - to the outputs of the coincidence of all elements dividing channels second. the inputs of which are connected to the input bus, with the installation inputs of the pulse counters of all the division channels and with the reset input of the channel non-synchronous analyzer.

Sources of information taken into account in the examination

1. USSR author's certificate i№; 429536, cl. H 03 K 23 / OO, 1973.

2. USSR author's certificate No. 664299, cl. H 03 K 23/00, 1975.

Claims (1)

Claim A majority-reserved pulse frequency divider containing N division channels, each of which consists of a pulse counter, the counting input of which is connected to the input bus, and a majority element, the corresponding input of which is connected to the output of the pulse counter of this division channel and the same inputs of the majority elements of the remaining channels of division, and the output is with the first input of the coincidence element of this same division channel, characterized in that, in order to increase the speed of the device and the stability of s output pulses, it introduced not-in-phase analyzer channels, each of the M inputs being connected to. the inputs of the majority elements with the same name, and the output - with the outputs of the matching elements of all the division channels, the second, the inputs of which are connected to the input bus, with the setting inputs of the pulse counters of all the division channels and with the reset input of the channel non-phase analyzer.