SU1721825A1 - Synchronous frequency divider by 55 - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital equipment, namely in frequency synthesizers. The divider consists of the neck of the K-triggers, the three logical elements AND, and the logical element OR. The purpose of the invention is to increase the reliability and stability of the operation of the divider by simplifying the circuit. This is achieved through the introduction of the element OR or the elimination of the three AND elements, as well as a change in the communication circuits between the elements. The divider contains K-triggers 1-6, the elements And 7-9, the element IL-10, the tire 11 reset, the bus 12 clock pulses and output tires 13-15. 2 Il.

Description

1

VI

Yu

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Yu

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The invention relates to digital technology and can be used, for example, to build chronizers, digital frequency synthesizers, electromusical instruments and other devices.

Known frequency divider at 55, built on a fanless circuit containing eight IK-flip-flops.

The disadvantage of this divider is a large number of elements and circuits, which leads to low reliability and stability of the circuit. In addition, this divider has low speed, because it is built on an asynchronous scheme.

Closest to the proposed is a synchronous frequency divider at 55, containing six IK-flip-flops and six I elements, in which the counting inputs C of all IK-flip-flops are connected to the device's clock bus, the R-inputs of all the flip-flops are connected to the reset bus, the outputs of the sixth trigger form the output buses of the device, the direct output of the first trigger is connected to the 1 input of the second trigger, the direct output of which is connected to the first inputs of the first, second and third elements AND, the outputs of the third, fourth, fifth and sixth elements AND are connected with 1 inputs, respectively, of the sixth, fourth, fifth, and third triggers, the inverse output of the first trigger is connected to the first inputs of the fourth, fifth, and sixth elements of AND, and the second inputs of the first, second, and third elements of AND, the direct output of the second trigger is connected to The K input of the third trigger, the direct output of which is connected to the 1 input of the first trigger, the K input of which is connected to the inverse output of the second trigger, the K input of which is connected to the inverse output of the third trigger, with the second inputs of the fourth and fifth elements And with the third inputs of the first, second and third elements And, the output of the first element And connected to the K-input of the fourth trigger, the direct output of which is connected to the second input of the sixth element And, and the inverse output - with the third input of the fifth element And the fourth inputs of the second and third elements And, the output of the second element And connected to the K-input of the fifth trigger, the direct output of which is connected to the third input of the fourth element And, and the inverse output with the fifth input of the third element And, the output of which is connected to - the entrance of the sixth trigger ra, the inverse output of which is connected to the fourth input of the fifth element I.

The disadvantages of the known divider are low reliability and stability of operation due to the complexity of the circuit.

The aim of the invention is to increase the reliability and stability of operation by simplifying.

In the frequency divider containing the first, second, third, fourth, fifth and sixth IK-triggers, C- and R-inputs of which

0 are connected respectively to the clock pulse bus and to the reset bus, the first, second and third elements I, the first and second output buses, which are connected respectively to the forward and inverse outputs of the sixth trigger, the I and K inputs of which are connected to the output of the third element AND, the inverse output of the first trigger is connected to the first input of the second element AND, the output of which is connected to the i-input of the fifth trigger, an OR element is entered, the output of which is connected to the 1 input of the third trigger, the first input and with K-in ohm

5 of the third trigger, and the second input is the output of the first element I, the first input of which is connected to the forward output of the second trigger, the second input to the forward output of the sixth trigger, and the third input to the forward

0 output of the fifth trigger, the third output bus and the first input of the third element And, the second input of which is connected to the output of the second element And and the K-input of the fifth trigger, 1 input of the first trigger is connected

5 with - and K-inputs of the second trigger and inverse output of the fourth trigger, the direct output of which is connected to the second input of the second element And and the K-input of the first trigger, the inverse output of the second trigger And connected to the third input of the second element with a direct output of the third trigger and the I and K inputs of the fourth trigger.

With such a connection scheme, logical

The 5 equations for the I and K inputs of all the triggers are as follows:.

And jq4; l2 Q4, l3 QivQ2 QsQe; U Cb: Is 61 Q2 Cb CM; le is qs; Ki CM; K2 W: Ks Qi; K4 Qs; .

0 FIG. 1 shows the scheme of the proposed frequency divider; figure 2 - diagrams of his work.

The frequency divider contains the first 1, second 2, third 3, fourth 4, fifth 5 and

5 sixth 6 IK-triggers, first 7, second 8 and third 9 elements AND, element OR 10, reset bus 11 and clock bus 12, which are connected respectively to the R and C inputs of all the triggers, output buses 13 and 14, which are respectively the direct and inverse outputs of the sixth trigger,

output bus 15, connected to the direct output of the fifth trigger and allowing to obtain a variable division factor for the first half of the cycle, equal to 55 pulses, 28, and for the second - 27.

Triggers 1-6 switch under the effect of a negative signal differential on clock bus 12 at the time it changes from a high level (logical unit) to a low level (logical zero).

The operation of the proposed frequency divider is determined by the logical equations for the I and K inputs of the IK flip-flops and occurs in the following order.

By the Reset signal, arriving in the form of a pulse on bus 11, all the triggers are set to the initial zero state, and the outputs (direct) of the triggers take the zero value (Fig. 2, the diagrams with. I,,,, and).

The logical equations determine the states of the 1st K-inputs of the flip-flops: And 1, 2 1, C-0, ls 0, le-0, Ki-0, Ka-1. Кз-1, Кл О, КБ 0, Кб 0.

Since the IK-trigger on the input pulse on the clock bus 12 when and does not change its state, when and switches to the opposite state, when and switches to the state of logical one, when and switches to the state of logical zero, then by the first input the first, second and third triggers are switched to the logical unit state, and the fourth, fifth and sixth state do not change, the outputs and trigger inputs take the following values: QI 1, Q2 1, Oz 1, Q4 QQs 0 , About Oh ,, ,,,,,, FIR,,, and (figure 2, diagrams n ri).

Upon the arrival of the second clock pulse on the falling edge, its state changes the second and fourth triggers: the second switches to the logical zero state, and the fourth to the logical one state, and the outputs and trigger inputs take the values,,,,,,,, ,,,,,,,, and (FIG. 2 diagrams, with).

Considering the operation of the proposed divider in the same way, all the states of the outputs and inputs of each IK-flip-flops 1-6 are obtained for all i.

After 54 pulses, the divider is in a state where,,,,,,,,,, ls-1,,,,,, and Ке 1 (figure 2, diagrams with).

In these states of the I and K inputs of the IK flip-flops, after the next 55 input pulse arrives, the third, fourth, fifth, and sixth flip-flops switch and the divider returns to the initial state. With continuous input pulses, the divider cycle is repeated every 55 times 0 pulses.

The cycle of operation of the fifth trigger (Fig. 2) repeats also over the interval of 55 pulses, but it performs the first period when divided by 28 (chart with) - differential

5 voltages from high to low, and the second period - by 27 (figure 2 with). If it is necessary to divide the input pulses with repeating frequency 28, 27, it is necessary to use the output bus 15.

The use of the proposed synchronous frequency divider by 55 allows to simplify the functional scheme of the divider into two logical elements (17%) and ten circuits (22%), increase reliability by simplifying the scheme, increase the stability of the divider by reducing parasitic capacitances due to the reduction in the number of elements and chains

0 resulting in a decrease in communication links and the number of their intersections, to reduce power consumption by reducing the number of elements.

Claims (1)

Invention Formula 5 Synchronous frequency divider by 55, containing the first, second, third, fourth, fifth, and sixth IK triggers, the C and R inputs of which are connected respectively to the bus clock and bus 0 reset, the first, second and third elements And, the output of the last of which is connected to the I- and K-inputs of the sixth IK-flip-flop, the inverse output of the first IK-flip-flop is connected to the first input of the second element And, the output 5 of which is connected to the 1-input of the first IK-flip-flop, characterized in that, in order to increase the reliability and stability of the operation by simplifying, an OR element is introduced into it, the output of which is connected to 0 1-input of the third IK-trigger, the first input -with the first input of the second element And and with the K-input of the third IK-trigger, the second input - with the output of the first element And, the first input of which is connected to the direct output 5 of the second IK-flip-flop, the second input-with the direct output of the sixth IK-flip-flop, the third input - with the direct output of the fifth IK-flip-flop and the first input of the third element And, the second input of which is connected to the output of the second element And and K -input of the first IK-flip-flop, 1-input of the first IK-flip-flop is connected to I- and K-inputs of the second IK-flip-flop and with the inverse output of the fourth IK-flip-flop, the direct output of which is connected to the second input of the second element I and to the K-input the first IK-flip-flop, inverse output of the second IK-flip-flop is connected to the third input of the second element I, the fourth input of which is connected to the direct output of the third IK-trigger and to the I- and K-inputs of the fourth 15 B 1 2 34f676SlO 12/4 1B 18 20 22 24 2S 28 Zy 32 34 3S 38 4v 44 2 50 S2 K Hi PP PP PP PP PP c, p g-1 gp p g-In p I-1 p p I-in a3 11 P I I P I I P I 1 P I a ,, L I1 P I1 P I-1 P I1 P P P P XL P11 P P P11 05. Q6P P P XL P11 P P P11 X one