SU789767A1 - Digital measuring in balanced bridge - Google Patents

Description

The invention relates to a measurement technique and can be used in the measurement of non-electric quantities using tensoris tori. Known digital measuring unbalanced bridge containing; a bridge circuit, one arm of which is formed by a measuring resistor, for example, a strain gauge, an unbalance amplifier included in the measuring diagonal, an integrator connected in series and a limiter amplifier, a time interval adjuster connected to the output of the amplifier-limiter, with a time interval meter and control inputs two keys l. A disadvantage of this device is the nonlinearity of the dependence of the output code on the working resistance of the resistance strain gauge. Also known is a digital measuring unbalanced bridge containing a bridge circuit, one arm of which is formed by a measuring resistor, an imbalance amplifier connected to the measuring diagonal, a current source that changes its polarity, one output of which is connected by one vertex of the power diagonal, an integrator whose input connected to the output of the unbalance amplifier, an amplifier-limiter, whose input is connected to the integrator's output, and the output is connected to the control input of the current source, a time interval sensor connected to the output of the limiter amplifier, with a time interval meter and with control inputs of two switches 21. The device has the following disadvantages: for rigid functional connection of the code with the measured increment of resistance, you must either use an exemplary resistor or perform a preliminary measurement of its resistance J not provides a direct measurement of the relative change in resistance of the measuring resistor; As part of the time meter interpBanoB, it is necessary to have a high-precision reference frequency generator, the pulses of which fill the measured time interval, since the accuracy of the reference frequency setting determines the measurement accuracy by the device;

The need to use the current source as the source of power for the bridge circuit leads to the complexity of the latter.

The purpose of the invention is to increase the accuracy of measuring the relative value of the resistance of the measuring resistor.

This goal is achieved by the fact that a digital measuring unbalanced | in bridge consists of a bridge circuit, one arm of which is formed by a measuring resistor, for example, a strain gauge, power source, one output of which is connected to one vertex of the power diagonal, unbalance amplifier, one input of a cohort. first connected to the first vertex of the measuring diagonal connected to the common point of the constant resistors of the bridge circuit, a serially connected integrator and an amplifier-limiter whose output is connected to the control input of the power source, two keys, a time interval sensor connected to the output of the limiter amplifier and the control inputs of the keys, a time interval meter containing a pulse generator and the series-connected AND circuit and the counter whose JQ control inputs are connected to sensor time intervals, equipped with a voltage divider formed by three series-connected resistors connected to the tops of the diagonal and power supply and having two outputs at the points of connection of two adjacent resistors, a digital-to-analog converter, the input of which is connected to the output of the unbalance amplifier, and the output is connected to the input of the integrator, a register, the outputs of which are connected to the control inputs of the digital-analog converter, a third key, a digital memory block, the inputs of which are connected to the output of the counter, and the outputs 45 are connected to the inputs of the register and the counter, while the second input of the imbalance amplifier is connected via keys, respectively, to the second vertex of the measuring diagonal and the outputs of the voltage divider regular enrollment is made as a power source voltage, the other output of which is connected to the other diagonal vertex power to the sensor and the time interval jj shafts, the output of the AND circuit is connected to. the counter input through a frequency divider, the control. The inputs of which are connected to the sensor of time intervals, the main: equalizing inputs of the register and the digital memory block are connected to the sensor of time intervals.

The temporal spacing sensor contains a strobe driver, the second and third counters, whose inputs are interconnected and connected to 65

a AND-OR circuit with a pulse generator, the fourth counter, two outputs of which are connected to the control inputs of the second and third counters, and the input is connected via the OR circuit to the outputs of the second and third counters and the output of the one hundred percent counter. one of the inputs of the exclusive OR circuit and through the matching circuit with the input bus of the time interval sensor connected to the output of the limiter amplifier, and the output connected to another input of the exclusive OR circuit, and the C input connected to the input of the fourth counter, l a magic unit, the inputs of which are connected to the outputs of the fourth counter, to the output of the exclusive OR circuit, to the output of the operating mode setter and to the input bus of the time interval sensor connected to the power source, while the outputs of the logic unit are connected to the output busbars of the time interval sensor, one control The input of the AND-OR circuit is connected to the output of the gate driver, and the second input with the output of the circuit is exclusive OR.

FIG. 1 shows a digital measuring unbalanced bridge; in fig. 2 - time interval sensor; in fig. 3 is a timing diagram of the integrator output voltage. The digital unbalanced measuring bridge contains a bridge circuit consisting of an active strain gauge 1, a compensation strain gauge 2, exemplary resistors 3 and 4, a voltage divider formed by resistors 5, 6, and 7, a power source 8 included in a single diagonal bridge circuit, an amplifier 9 imbalances, one input of which is connected to the common point of resistors 3 and 4, and the other input through keys 10, 11 and 1 is connected, respectively, to a common point of strain gauges 1 and 2, to a common point of resistors 5 and b and to a common point of resistors 6 and 7. After orally connected digital-to-analog converter 13, consisting of discharge resistors 14, 15 and discharge switches-16, integrator 17, amplifier-limiter 18, register 19, whose outputs are connected by control inputs of switch 16, meter 20 time intervals consisting of a serial connection of the pulse generator 21, the circuit 22 I, a 23 hour divider; the tots and a reversible binary-decimal counter 24, a digital block 25; a memory whose inputs are connected to the outputs of the decimal counter 24, and the outputs are connected to entrances and the register 19 and the counter 24, the sensor 26 of the time intervals, the input buses 27, | 28 and 29 of which are connected, respectively, to the output of the limiting amplifier 13, with one vertex of the diagonal of the bridge circuit, and the output of the generator 21, and the output tires 30 -40 are connected to the control inputs of the keys 10, 11, 12, register 19 of the circuit 22 I, frequency divider 23, counter 24 and digital memory block 25 Time interval sensor 26 contains a gate driver 41 connected to the industrial voltage network, reversible counters 4.2 and 43, the inputs of which are interconnected and Without circuit 44 AND-OR connected to input bus 29, counter 45, the counting input of which is connected via circuit 46 OR to the outputs of counters 42, 43 and driver 41, flip-flop 47, whose D input is connected to one input of circuit 48 exclusive OR and through the matching circuit 49 with the input bus 27. The trigger output 47 is connected to another input of the circuit 48, and the counting input is connected to the output of the circuit 46. The outputs of the counter 45, the master 50 operating modes, the circuits 48 are connected to the inputs of the logic block 51. Two outputs of counter 45 are connected to the control inputs of counters 42 and 43, installation inputs sche tors 42, 43 and 45 through a driver 52 coupled short pulses output shaper 41.Upravl yuschi input circuit 44 are connected respectively to the output of the circuit 48 and forms rovatel 41, a control input connected to torogo start button 53. The input bus 28 is connected to one and the inputs of the logic unit 51, the outputs of which are connected to the output buses 30-40. The device has two modes of operation set by setter 50. The first mode is carried out with the strain gauge 1 unloaded, i.e. in the absence of deformation. In this mode, the analog-to-digital conversion algorithm is organized so that the output code displays the value of YOU R1 the original resistance of the active strain gauge 1; 2 resistance of the compensation strain gauge 2. In the second mode, the strain gauge has a working increment of resistances. In this mode, the output code reflects the value of Ra. .U R 9. where lK is the working increment of the resistance of the strain gauge 1. In each mode of operation, the device has two stages of analog-to-digital conversion. At the first stage, intermediate code 2 is formed. Here is k -V i where b and b are the coefficients; intermediate code in the first mode of operation; . - intermediate code in the second mode of operation. Counter 24 has a high bit that displays the integer part of the generated code, and consists of one trigger, and several binary-decimal decades, representing the fractional part of the code. The choice of the number of such decades depends on the measurement accuracy. Since, in tensometry, usually, the unit of discreteness is the relative units of strain, in this case it is necessary to have five decades. In this case, the generated code will be a decimal number with five decimal places. The device implements the analog: digital conversion by the push-pull integration method, which consists in first applying the unbalance voltage of the bridge circuit amplified by amplifier 9 to the integrator 17 input, which is integrated over a time interval equal to the mains voltage period 1 t - t 5 (Fig .G) Then, the input voltage, torus 17, is supplied with a reference voltage, also amplified by an amplifier 9 opposite to polarity. The time interval from the moment t-, to the moment t, when the output voltage of the integrator 17 becomes zero, is proportional to the ratio of the unbalance voltage and the reference voltage. U T K-UO-TJ, where they are the voltage unbalance; Uo is the reference voltage, K is the resulting gear ratio of the amplifier 9, the digital-to-analog converter. l 13 and the integrator 17. We express the unbalance voltage through the elements of the bridge circuit. Uy or where where Ug is the voltage of the power supply source 8; Rj is the resistance of the resistor 3; R4 is the resistance of resistor 4. At R, R4, we get (- |) Rg - RI 8 2 () The reference voltage Uo is formed by an auxiliary bridge formed by resistors 3, 4 and resistors 5, b and 7. In this case, the key 10 is open, and one of the keys 11 and 12 is closed. The choice of key 11 or key 12 determines only the sign Uo, and absolute

its magnitude is the same in both cases. This is ensured by the equality

(one)

R,

gn

where R f is the resistance of the resistor 5, R 1 is the resistance of the resistor 7. With the key 11 closed, we have

about (1h

, 2, and with a closed key 12

-i

and. (

8 Rj + Rfc + R ii. II R7- R5 + Rfe

UQ - Ug

2 ()

II 11 ".b 8 2 (Rj)

Taking into account the condition (1), we obtain

Rfe

and

8 2 (Rg + R6 + R)

6

and ® 2 (R + R + R,)

Thus, the reference stresses and o and DO are equal in absolute value and opposite in sign.

If you enter the designation

1 t

R6

2 (,)

the support voltage will be

| and

m

The frequency divider 23, depending on the potentials on the output buses 35 and 36 of the sensor 26 time intervals, has three division factors

V-l

Si b

TO

To simplify the frequency divider, m is a multiple of

m. 2,

where P is an integer.

The value of P, in turn, choose

proceeding from the fact that

- and, „,

and,

where is the maximum unbalance voltage of the bridge circuit. To ensure high resolution of the device, it is necessary that both o and u are as close as possible to each other.

The discharge resistors 15 of the digital-to-analog converter form bits of binary-decimal decks.

The conductivity of each of the resistor 15 corresponds to the weight value of the corresponding binary-decimal bit. The conductivity of resistor 14 is equal to the total conductivity of resistors 15.

and

(2)

 S d.

 9 ° i -.- f 1

where d is the conductivity of the 15th discharge resistor.

In the initial state, when the register 19 is set to zero, the resistor 14 is connected to the input bus of the D / A converter connected to the output of the amplifier 9, and the resistors 15 are connected to the zero bus (case). In this case, the transfer coefficient of the digital-to-analog converter is

on 9

in view of the relation (2)

TO

by

The device works as follows.

The first mode of the device.

5 From the output of the setpoint 50, the potential of the logical unit enters the input of the logic unit 51. The device is started by pressing the button 53. The feedformer 41 generates a single strobe, the fronts of which coincide with the moments of the two nearest voltage transitions from one polarity (positive) to another (negative ), i.e. the duration of the strobe is equal to the period of the mains voltage. During strobe action

circuit 44 is open, and generator 21 pulses arrive at the inputs of counters 42 and 43. On the leading edge of the strobe, the driver 52 produces

0 on the first output a short pulse setting counters 43 and 45 to the homing state. On the output bus 30 in Wits, the potential of the unit and the key 10 is closed. Outputs first

J bit counter 45 sets counter 43 to add mode, and counters 42 sets to subtract mode. Upon expiration of the strobe, at time t (Fig. 3), the code 43 will be fixed in the counter 43

NO - TO,

where f is the frequency of the generator 21; T is the duration of the period of network voltage 5. The sign of the integrator's output voltage is determined by the unbalance voltage sign. At time ty: 1. The counter 42 is set to zero by the driver 52, at the second output of which a reset pulse is emitted along the front of the strobe. At the same time, the trailing edge of the gate through the circuit 46 acts on the counting inputs of the counter 45 and trigger 47. 2. At the output of the trigger 47, a potential is logically equal to the potential from the output of circuit 49, which is determined by the state of the limiting amplifier 18. 3. Since at both inputs of the circuit 48 there will be identical potentials (two zero or two units), then at its output a logical unit arrives at the inverting control input of the circuit 44, which will now be closed at both control inputs. 4. Under the action of the logical unit at the output of the circuit 48, the logic unit 51 generates at one of the output buses 31 and 32 the potential of the unit, which opens one of the keys 11 or 12. The logic for selecting the key, taking into account the designation of the direct and inverse inputs of the amplifier 9, is determined by the equation 48 V X 1, if the key ll is closed, 1, if the key 12 is closed; 1, if a unit signal is present at the output of circuit 48; Xg 1, if the pole of the power supply 8, connected to the sensor 26 time intervals, is positive; X q - 1 if the output voltage of amplifier 9 is positive. As a result, at time t, and also at time t-, tg, t-,, t, the formation of the reference voltage DO, the polarity of which is opposite to the polarity of the voltage unbalance TC, occurs. In the interval, the output voltage of the integrator 17 will decrease in absolute value to zero. At the time t2, the following occurs: 1. Change in the polarity of the output voltage of the amplifier-limiter 18 and the circuit 49. 2. At the output of the circuit 48, the voltage is low. the potential is zero, since its inputs will have different potentials. 3. A short pulse is generated on the bus 39, setting the counter 24 to zero. Register 19 is also set to zero. On bus 37, the addition mode of counter 24 is set. 4. Scheme 44 is opened for the generator 21 pulses on the inverse control input. 5. On the output buses 35 and 36, the division factor of frequency divider 23 is equal to Kg. 2. 6. Locking key 10, the logic of which is described by the expression "where is HOR 1, when binary number 00 is recorded in counter 45. 7. Under the influence of the output voltage difference of amplifier 18, source B will change the polarity of the voltage, and therefore , in the time interval T tl, the unbalance voltage will be opposite in sign to the unbalance voltage in the tf-t interval. In the interval T 2 2, the pulses of the generator 21 arrive at the inputs of the counters 42, 43 and through the divider 23 to the input of the counter 24. The counter code 42 increases from zero, the counter code 43 working on subtraction decreases from N (J and at time t, j will become zero, successively t is -1 f At time t occurs: 1. The potential difference from the output of counter 43 through circuit 46 affects the counting inputs of counter 45 and trigger 47. As a result, double number is written to counter 45 01, and the output of the trigger 47 sets the potential, logically equal to the output the potential of circuit 49. 2. Potential 1 is established at the output of circuit 48, circuit 44 is closed, and code NO is fixed in counter 42. Counter 42 is set to subtract mode, and counter 43 is added to add mode. or 12, in accordance with q expression (3), and a reference voltage is connected to the input of amplifier 9, the polarity of which is opposite to the polarity of the unbalance voltage. 5. The counter 24 is set to the addition or subtraction mode, which is determined by the logical equation X24 X48 ( X8- X + Xg-X,, (5) where X2., If the counter 24 is set to mode dix. 6. The division factor of splitter 23 is set to K o-t. In the interval Tj, - t - t, the output voltage of the integrator 17 decreases from absolute value to zero. At time t, the limiting amplifier 18 will change its polarity, under the influence of which the source 8 will change its polarity of the supply voltage. Further, in the intervals T t - t and T4 tf, - tj, the device operates in the same way as in the intervals T t a 4 3 ° of the other polarity of the source voltage 8, and in minute tj- in the counter 45 will be written double number 10. For intervals T. and T we have the relation T - C t T, -UX o Uo or, taking into account the expressions for U t-t and i-. Jk g about 821R + R, j) m -r-Ri R-1 TO- 2 (R; + R,) x | -g in the time interval T. the counter operates in the add mode, and the frequency divider 23 has K (2. Consequently, during the specified interval the code i will be written in the counter In the interval T K t, and during that interval in the counter 24 will go to The number of pulses .A and the counter 24 at time t forms the algebraic difference between the codes N and N2. The mode of operation of the counter 24 in the interval Ta, chosen according to expression (5), is ultimately determined by the numerator in the expression (6), so that with R, R 7 About the counter 24 works on the subtraction, and when, - - About the counter 24 works on the addition. In a way, at time t, a code m –y –N -1t –Rl) T7 ml-ma-5o is formed in the counter 24; the code 2N will be fixed in the counter 24 in the interval tg-t in the counter 24; , fT,,. At time J: b, the second analog-to-digital conversion begins. this moment, as well as later, at block tg, logic block 51 generates a blocking signal, where 1, if binary number 10 is written in counter 45, binary number 11 is written in counter 45. At XjfA 1, the action of the logical equation is canceled (4), and instead of the key 10, one of the keys 11 or 12 remains closed, the one that was closed until t (,. The logic of the key 10 operation based on the expressions (4) and (7) takes the form 48 -lt 00В the time t, moreover, occurs: 1. Code N4 is entered into digital memory block 25, and counter 24 is reset to zero 2. By bus 34 cx The terminal 22 is closed for the generator pulses 21. 3. The source 8 will change the polarity of the voltage. 4. The output of the circuit 48 is at a potential zero and the circuit 44 will open for the pulses of the generator 21. The formation of the time interval Tg. TO begins, during which to the amplifier inputs 9 is connected to the reference voltage DO At time tf; 1.B counter 45 will write the binary number 11. 2. In the register 19 of block 25, the code N. is entered. 3. Scheme 22 is opened for generator 21 pulses. 4. The division factor of divider 23 is set to Cd 1. 5. The trigger of the older bit of counter 24 is set to e Init and the remaining bits to zero. 6. Counter 24 is set to add mode. Otherwise, the same thing happens at times t. Usually in strain gauges it is practically easy to ensure that 0.95 C1.05. Nominal requirement for setting the oscillator frequency 21 where fv, is the nominal frequency of the oscillator 21. If the frequency deviation f is assumed from the nominal frequency within fH + 5% f -) fH - 5%, which allows to apply the simplest oscillator circuit 21, then taking into account the expression (8) we get the ORT. Condition (9) allows to perform a digital-to-noise converter of four decades formed by resistors 15 and 14. When entering the N code into the register 1, the counter of the counter 24 performs the role of a sign. If i, then the resistor 14 does not change its state, and the discharge resistors 15 are switched in accordance with the fractional part of the N code. If 1, then simultaneously with the switching of the resistors 15, its state and the resistor 14 change. As a result , the transfer coefficient of the digital-non-threshold converter with the MD code entered into register 19 will be OQ-V.SQ.O. (, -r L. P o where a o 1, if the sign resistor 14 remains in the initial state MD 1; 1, if the resistor i of the discharge changes its state. If N d 1, then go + go (N4-1 2 (jo If, From this, when entering the registration code 19, the return of the digital-to-analog converter to the original Kfj paBHO K (N4-l) 1 2 4 / i ratio The intervals T and Tg are a repetition of the intervals Tj and Tfe with a different power polarity Therefore, putting T Tg in the counter 24 is written, the code, R-R, -And + G because the high-level trigger of the counter 24, previously set to 1 with the arrival of the first counting pulse will be set to the state O, and with the arrival of the second pulse, if d-71, the state 1 is set again, the code Мв, is entered into the digital memory block 25, and the device in the first mode ends. operation mode of the device. In this mode, there are the following differences in the operation of the device. This leads to the fact that in the intervals and the counter 24 operates in the opposite mode X, + X g X Ie in the second reztas, one of the signals; Catch Xg or Hf is inverted. At time tj in the counter 24, form the algebraic sum of the codes H and N4. I v, q, 5 g N, -N.N. - .. th (v R Vft-i, respectively, Rt + uf -l At times t, tg from block 25. The direct code NBUK is entered into register 19, and at time t the inverse code moments t-, t (), similar to the first mode, code N is entered into register 19. As a result, at intervals tg-t (, we get the ratio Code in counter 24 at time tio, determine. Ra .. UR, Ua uRv RU, Since the value of cf R - TO with a positive uR trigger highlight of counter 24 will be in the unit state. If 1 bR is negative, the specified trigger will be in zero state. Thus, the state is The first trigger displays the sign of the measured value cTR. Thus, the proposed device allows you to directly measure the increment of the resistance of the measuring resistor. At the same time, the output code does not depend on the accuracy of the reference frequency. As the voltage integration time is equal to the period of the mains voltage, measurement error is eliminated due to interference in the resistive sensor circuit. The errors due to the offset of the zeros of the amplifier 9, the amplifier-limiter 18 and the integrator 17 are eliminated due to the fact that the formation of both intermediate and output codes is carried out twice with a change in the polarity of the supply voltage of the bridge circuit. The inaccuracy of the installation of this voltage does not lead to measurement error due to the fact that the reference voltage is formed from the same voltage. The measurement accuracy is determined only by the resistive elements, namely, the manufacturing accuracy of the bridge circuit resistors, the voltage divider and the multiplying digital-to-analog converter. In addition to measuring the relative increment of resistance, the device allows you to measure the resistance ratio of the strain gauges 1 and 2. Formula 1 of the invention. A digital unbalanced measuring bridge containing a bridge circuit, one arm of which is formed by a measuring resistor, for example, a strain gauge, power supply, one output which is connected to one vertex of the power diagonal, the unbalance amplifier, one input of which is connected to the first vertex of the measuring diagonal, connected to the common point of the constant resistor In the bridge circuit, the serially connected integrator and the amplifier-limiter, the output of which is connected to the control input of the power source, two keys, a time interval sensor connected to the output of the amplifier-limiter and control inputs of the keys, a time interval meter containing a generator pulses and a series-connected AND circuit and a counter, the control inputs of which are connected to a time integral sensor, characterized in that, in order to improve the accuracy of measuring relative air traffic In addition to measuring voltage, it is equipped with a voltage divider formed by three successively connected resistors connected to the tops of the power diagonal and having two outputs to the connecting point of adjacent resistors, a digital-to-analog converter whose input is connected to the output of the unbalance amplifier, and the output is connected to the input the integrator, the register whose outputs are connected to the control inputs of the digital-analog converter, the third key, the block of digital memory, the inputs of which are connected to the outputs the counter, and the outputs are connected to the inputs of the register and the counter, a frequency divider connected between the output of the AND circuit and the input of the counter, while the second input of the unbalance amplifier is connected via keys, respectively, to the second vertex of the measuring diagonal and the voltage divider outputs, the power supply is the form of a voltage source, another output of which is connected to another vertex of the power diagonal and to the time interval sensor, the control inputs of the register, frequency divider and digital memory block are connected to the time sensor ennyh intervals. 2. The device according to claim 1,0 t l that the time sensor contains a gate driver, the second and third counters, whose inputs are interconnected through an AND-OR circuit with a pulse generator, the fourth counter, two outputs of which are connected to control inputs of the second and third counters, and the input through the OR circuit is connected to the outputs of the second and third counters and the output of the gate generator, a trigger, the D input of the KOTODoro is connected to one of the inputs of the exclusive OR circuit, and through the matching circuit with the input bus of the time sensor intervals connected to the output of the amplifier limiter, and the output is connected to another input of the exclusive OR circuit, and the C input is connected to the input of the fourth counter, a logic unit whose inputs are connected to the outputs of the fourth counter, to the output of the exclusive OR circuit, to the output of the mode setter operation and to the input bus, a time sensor connected to a power source, while the outputs of the logic unit are connected to the output time sensors of the time sensor, one control input of the AND-OR circuit is connected to the output the gate strobe, and the second input - with the output of the circuit exclusive OR. Sources of information that have been taken into account in the examination 1. USSR author's certificate No. 423055, .G 01 R 17/10, 1971. 2. USSR author's certificate 611157, G 01 R 17/10, 1975.

2f

Claims (2)

Claim 1. A digital measuring unbalanced bridge containing a bridge circuit, one arm of which is formed by a measuring resistor, for example, a strain gauge, a power source, one output of which is connected to one vertex of the power diagonal, an unbalance amplifier, one input of which is connected to the first vertex of the measuring diagonal, connected to the common point of the constant resistors of the bridge circuit, series-connected integrator and amplifier-limiter, the output of which is connected to the control input of the power source, two switches a, slots sensor coupled to the output of the amplifier and limiter. control inputs of keys, a time interval meter containing a pulse generator and subsequently connected circuit I and a counter, the control inputs of which are connected to a time interval sensor, characterized in that, in order to improve the accuracy of measuring the relative increment of the resistance of the measuring resistor, it is equipped with a voltage divider formed by three series-connected resistors connected to the vertices of the power diagonal and having two outputs at points; the connection of adjacent resistors, a digital-to-analog converter, the input of which is connected to the output of the unbalance amplifier, and the output is connected to the integrator input, a register, the outputs of which are connected to the control inputs of the digital-to-analog converter, with a third key, a digital memory unit, the inputs of which are connected to the outputs of the counter, and the outputs are connected to the inputs of the register and counter> a frequency divider connected between the output of the circuit And and the input of the counter, while the second input of the unbalance amplifier is connected via keys, respectively From the second vertex and the diagonal measurement voltage divider outputs, the power supply is configured as a voltage source, the other output of which is connected to the other diagonal vertex power to the sensor and control slots register input, a frequency divider and a digital storage unit connected to the sensor slots. 2. The device according to π.Ι, which means that the time interval sensor comprises a strobe driver, a second and third counters, the inputs of which are interconnected via an AND-OR circuit with a pulse generator, a fourth counter, two outputs of which are connected to the control inputs of the second and third counters, and input through an OR gate connected to outputs of the second and third counters and the output of the gate, trigger, D-input kotooogo connected to one of the inputs of the circuit '' exclusive-OR ^'1 and via a matching circuit with an input bus vre sensor intervals connected to the output of the amplifier of the limiter, and the output is connected) with the other input of the circuit exclusive OR, and the C-input connected to the input of the fourth counter logic block, the inputs of which are connected to the outputs of the fourth counter, to the output of the circuit exclusive OR, to the output of the mode dial and to the input bus of the time interval sensor connected to the power source, while the outputs of the logic unit are connected to the output buses of the time interval sensor, one control input of the AND-OR circuit is connected to the output of the the gate, and the second input - with the output of the circuit exclusive OR.