SU762167A1 - ANALOG DIGITAL 1 - Google Patents

Description

The invention relates to measuring equipment and can be used in digital measuring instruments and ^{1 * * *} information-measuring systems.

An analog-to-digital converter is known that contains a switch, cf- ^{5 * * * *}

leveling device, sawtooth generator, two triggers, three

valve, delay line, pulse generator, reversible counter and control device £ΐ], ^{10 * * * *}

The disadvantages of the device are the need to determine the correction code before each conversion of the input voltage, which reduces the number of conversions per unit of time, as well as the impossibility of correcting the ^zero offset

when converting bipolar input voltage.

An analog-to-digital converter is known that contains a switch, the information inputs of which are connected to sources of positive and negative reference voltage, as well as

"''-•I'·

to the inputs of the measured voltage and zero potential, and the control inputs to the outputs of the decoder, the output of the switch is connected to the input of the integrator, the output of which is connected to the input of the null organ, the output of the null organ is connected to the inputs of the shaper and the key, the output of which is connected to the non-inverting input of the integrator amplifier and to one plate of the capacitor, the other plate of which is connected to the zero potential bus, the output of the shaper is connected to the first input of the decoder and to the first input of the control device, the first output of which is connected to one input of the valve, the other input of which is connected to the output of the reference frequency pulse generator, and the output is to the input of the pulse counter, the output of which is connected to the first inputs of the code reading valves | the second inputs of which are connected to the second output of the control device, and the outputs are to the output of the converter, the remaining two outputs of the control device

The signals are connected to the inputs of two triggers, the outputs of which are connected to the second and third inputs of the decoder [2^|.

The disadvantage of the device is its low performance. ₅

The purpose of the invention is to increase performance.

The stated objective is achieved by the fact that in an analog-to-digital converter containing a positive reference voltage source, a negative reference voltage source, a switch, an integrator, a null-organ, a key, a shaper, a reference frequency pulse generator, a valve, a pulse counter, code reading gates,

additional valves, a summing counter, a subtracting counter, code rewriting valves, a pulse generator and a resistor, | wherein the third output of the control unit 20 is connected to the first control input of the switch, to the control input of the key and to the preset input of the subtracting counter, the fourth output of the control unit is connected 25

.. £ -£ф<эр _Ы m control input" of the switch, with the input of the preliminary setup of the pulse counter and with the control input of the code rewriting gates, the inputs of which are connected to the output of the subtracting counter, and the outputs - to the input of the preliminary setup of the summing counter, the output of the summing counter is connected to the input of the pulse former, the output of which is connected to the second input of the control unit, the fifth and sixth outputs of the control unit are connected to the third and fourth control inputs of the switch, the seventh output of the control unit is connected to the first 40 input of the first additional valve, the second input of which is connected to the output of the reference frequency pulse generator, and the output - to the input of the subtracting counter, the eighth output of the control device is sub- 45 keys to the first input of the second additional valve, the second input of which is connected to the output of the reference frequency pulse generator, and the output - to the input of the summing counter and the third input 50 house of the control unit, the non-inverting input of the integrator is connected to the first terminal of the resistor, the second terminal of which is connected to the zero potential bus.

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"7" Fig. 1 shows the structural

electrical circuit of the device; on

Fig. 2 - timing diagram of its operation.

The device contains a positive reference voltage source 1, a negative reference voltage source 2, a switch 3, an integrator 4, a zero-organ 5, a former 6, a resistor 7, a key 8, a control unit 9, a valve 10, a summing counter 11, a pulse former 12, code rewriting valves 13, a valve 14, a subtracting counter 15, a reference frequency pulse generator 16, a valve 17, a pulse counter 18, and code reading valves 19.

The device operates as follows.

During the time interval defined by block 9, the measured voltage supplied to the device's input is integrated using integrator 4. The voltage at integrator 4's output is then converted into a time interval using the reference voltage, and counter 18 is filled with reference frequency pulses during this interval. The corresponding sources 1 and 2 are connected depending on the signal at the output of generator 6. The code at counter 18's output will then be proportional to the measured voltage.

Automatic zero-level correction of the integrator is performed in the digital-to-analog converter. The zero-level offset voltage of integrator 4 is periodically converted into an intermediate parameter—a time interval—which is in turn converted into a two's complement code using counter 15, which functions as an analog-to-digital converter and storage register. The code at the output of counter 15, corresponding to the offset voltage of integrator 4, is converted into a corresponding time interval during each input voltage measurement using counter 11, which functions as a digital-to-analog converter. This time interval is algebraically summed with the time interval corresponding to the voltage at the output of integrator 4.

During the time interval obtained as a result of summation, counter 18 is filled with pulses of the reference frequency, and at the output of counter 18, a code for the converted voltage is formed without an error from the zero offset of the integrator.

When the device is operating, two conditions are possible

polarity ratio variants им5 762167

the variable voltage and the bias voltage of the integrator, which correspond to two algorithms for the converter operation.

Option 1. The converted voltage and the integrator bias voltage have the same polarity.

The zero correction cycle begins with the formation of a signal at the third output of block 9, which is fed to switch 3 at the control input of key 8 ₁₀

and to the preset input of the subtracting counter 15. In this case, the switch 3 connects the input of the integrator 4 to the zero potential input, the key 8 closes the feedback circuit from the output ₁₅ of the null-organ 5 to the non-inverting input of the integrator 4, which is connected through the resistor 7 to the zero potential, and the digits of the subtracting counter 15 are set to the "1" state. The voltages ₂₀ at the outputs of the integrator 4 and the null-organ 5 change in accordance with the timing diagram (Fig. 2). Depending on the state of the output of the generator 6, which is remembered by the block 25 9 until the next correction cycle, the latter, upon completion of the signal at its third output, forms a signal at one of its outputs. With a positive polarity of the bias voltage of integrator ₄ , block 9 generates a signal at its fifth output and connects, using switch 3, the input of integrator 4 to source 1, while the capacitor of integrator 4 discharges according to a _linear law (see Fig. 2). In addition, block 9 also generates a signal at its seventh output by opening valve 14 and thereby allowing reference frequency pulses to enter the input of subtractive counter _15. Signals from the seventh and fifth outputs of block 9 are removed when the last signal (voltage drop) from the output of generator 6 arrives at the first input. Generator ₆ changes the state of its output at the moment the voltage at the output of integrator 4 is zero, which is fixed by null-organ 5. Thus, the duration of signals at the fifth ₅ θ and seventh outputs of block 9, as can be seen from the timing diagram of the device operation (see Fig. 2), is proportional to the bias voltage of integrator 4.

In this case, in the subtracting counter 15 ₅₅

(The capacity of which, like the capacity of the summing counter 11, is determined by the maximum possible value of the integrator's bias voltage and is significantly less than the capacity of counter 18) an additional time interval code proportional to the bias voltage of integrator 4 is recorded. This completes the correction cycle. The need for the next correction cycle is determined primarily by the temperature and time drift of the integrator's bias voltage.

The input voltage conversion cycle begins with the formation of a signal of a certain duration at the fourth output of block 9, which is fed to switch 3, to the preliminary setup input of pulse counter 18 and to the control input of valves 13. In this case, integrator 4 integrates the converted voltage (see Fig. 2), the bits of counter 18 are set to the "0" state, and an additional code for the correction time interval is written into the summing counter 11. Upon completion of the signal at the fourth output of block 9, a signal is formed at its eighth output (see Fig. 2), which goes to the control input of valve 10 and thereby allows the flow of reference frequency pulses to the input of summing counter 11. In addition, depending on the polarity of the converted voltage and its relationship with the polarity of the bias voltage (depending on the state of the output of shaper 6 in the conversion cycle and its relationship with the state of the output of the latter in the correction cycle, a signal is formed either at the first or at one of the outputs - the sixth or fifth of block 9. For the case under consideration (the bias voltage of integrator 4 and the converted voltage have positive polarity), block 9 simultaneously forms signals at its first and eighth outputs. The signal from the first output of block 9 goes to the control input of valve 17 _, thereby allowing the flow of reference frequency pulses to the input of counter 18 (see Fig. 2). When the summing counter 11 overflows, the shaper 12 generates a pulse signal at its output (see Fig. 2) and thus completes the formation of the correction time interval. At the end of this interval, the signal is removed from the eighth output of block 9 and a signal is generated at its sixth output, which goes to switch 3 and connects the input of integrator 4 to source '2. In this case,

762167

The transformation is carried out by means of a linear discharge of the capacitor, the voltage at the output of the integrator 4 into a time interval proportional to it (see Fig. 2), the end of which is recorded by the _zero -organ 5. A change in the state of the output of the zero-organ 5 causes a voltage drop at the output of the generator 6, which is fed to the first input of the block 9. In this case, signals are taken from the first and sixth outputs of the block 9 and a signal is formed at its second output.

At this point, the conversion cycle ends: the input of integrator 4 is disconnected from source 2, the supply of 15 pulses of the reference frequency to the input of counter 18 ceases, and the result of the conversion is output through valves 19, to the control inputs of which the enabling signal is supplied from 20 the second output of block 9. In this case, the voltage code at the output of integrator 4 is corrected in counter 18 by the value of the bias voltage of integrator 4 (see Fig. 2). 25

Option 2. The converted voltage and the integrator bias voltage have different polarities (the converted voltage has a negative polarity, and the bias voltage has a positive polarity).

The input voltage conversion cycle in the variant under consideration differs from that described above in that, upon completion of the integration of the converted voltage, block 9 forms a signal instead of the sixth at its fifth output (see Fig. 2), thereby connecting source 1 to the input of integrator 4. In this case, the signal at the fifth ⁴⁰ output is formed simultaneously with the signal at the eighth output of block 9, and the signal at the first output in relation to the above-mentioned signals with a delay T^ _o p , equal to the duration of the correction time interval, which ensures the correction of the voltage code at the output of integrator 4 and by the value of the bias voltage of the latter (see Fig. 2).

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The operation of the device with a negative polarity of the integrator bias voltage is carried out in accordance with the two options discussed earlier.

Thus, the device provides a sufficiently long storage time for the correction signal value. This

The time is determined by the drift of the reference frequency pulse generator frequency.

The frequency drift of the quartz resonator included in the reference frequency pulse generator is several orders of magnitude smaller than the offset voltage drift of the amplifier included in the integrator. Consequently, the period of the device's zero-level correction signal determination cycles is determined by the amplifier's offset voltage drift and is significantly greater than that of the conventional device (in which the correction signal is determined before each conversion), thereby improving the performance of the analog-to-digital converter.

Claims (1)

Claim An analog-to-digital converter containing a switch, the information inputs of which are connected to the outputs of the sources of positive and negative reference voltages, the switch output is connected to the integrator's input, the output of which is connected to the zero-organ input, the output of the zero-organ is connected to the inputs of the driver and the key, the output of which connected to the non-inverting input of the control unit, the first output of which is connected to the first valve input, the second input of which is connected to the output of the reference frequency pulse generator, and the output - to the input of the pulse counter, the output of which is connected to the first inputs of code-reading gates, the second inputs of which are connected to the second output of the control unit, characterized in that, in order to improve performance, two additional valves are added, sum-. A counting counter, a counting counter, code census valves, a pulse driver and a resistor, the third output of the control unit is connected to the first control input of the switch, to the control input of the key and to the preset input of the counting counter, the fourth output _ of the control unit is connected to the second control input of the switch , with the input of the pulse counter presetting and with the control input of the code census gates, whose inputs are connected to the output of the subtracting counter, and the outputs to the input are preceded The luminescent meter is installed, the output of the summing meter is connected to the input of the pulse shaper, the output of which is connected to the second 762167 the fifth and sixth control unit inputs, the control unit outputs are connected to the third and fourth control inputs of the switch, the seventh control unit output is connected to the first input of the first auxiliary valve, the second input of which is connected to the output of the reference frequency generator, and the output to the summing counter and the third input of the control unit, the non-inverting input of the integrator is connected to the first output of the resistor, the second output ten which is connected to the ground zero potential ...........