JPH0339415B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D-A conversion circuit and a D-A conversion method for converting a quantized digital signal into an analog signal, and particularly relates to a digital audio disk (DAD) and a digital analog signal. It is used in audio equipment such as audio tapes, and its purpose is to reduce distortion and speed up operation.

Generally, an analog audio signal is sampled and the quantized digital signal is recorded on a DAD or digital audio tape. For reproduction, the recorded digital signal is extracted and converted into an analog signal.

Conventionally, there is a method for converting a digital signal into an analog signal by using a ladder type resistance circuit or the like to synthesize weighted electrical quantities, such as current or voltage. A DA converter using this method generates noise when reproducing a very low level signal. In other words, when reproducing a small level, the input digital signal constantly goes back and forth between "011...111" and "100...000", so the resistor that generates the weighted amount of electricity is turned off each time. Therefore, the error in the resistor appears as noise. Furthermore, when the number of bits of digital signals increases and high resolution is required, it is necessary to adjust individual resistors such as ladder-type resistor circuits to accurate values by precise trimming, which requires technical difficulties. This has been a cause of the high cost of high-resolution D-A converters.

Furthermore, conventionally, an integral type D-A converter is formed as shown in FIG. In FIG. 1, an operational amplifier 1, a capacitor 2, and an input resistor 3 form an integrator. A reference potential source 4 is connected to the input resistor 3 via a switch means 5, and switch means 6 are also provided at both ends of the capacitor 2. The opening and closing of the switch means 5 and 6 are controlled by a control circuit 7. In particular, the closing time of the switch means 5 is determined by a time generating circuit 8 to which the digital signal is applied. Determined by the time created based on the value. That is, first, by closing and opening the switch means 6, the electric charge of the capacitor 2 is discharged, and the operational amplifier 1 is discharged.
Set the output voltage to 0 volts. Then, at the same time as the switch means 5 is closed, the time generating circuit 8 counts the clock pulse CLK applied from the outside,
When the counted contents match the applied digital signal, the switch means 5 is opened. Therefore,
During the counting time, the integrator integrates the voltage of the reference potential source 4, a voltage proportional to the counting time is generated at the output of the operational amplifier 1, and DA conversion is performed. However, in this integration method, if the resolution of the digital signal is n bits, a maximum of 2 ⁿ -1 clock pulses are required, so the higher the resolution, the longer it takes to obtain the output and the operation becomes slower. There was a drawback.

The present invention has been made in view of the above-mentioned points, and uses a plurality of continuously connected integrating circuits, divides an n-bit digital signal to be converted into N groups, and divides the n-bit digital signal to be converted into N groups. A weighted electrical quantity corresponding to a bit is created by an integrating circuit, and the electrical quantity is further integrated over time corresponding to the data of the corresponding group using a subsequent integrating circuit for each group. According to
The present invention provides a DA conversion circuit and a DA conversion method for obtaining analog signals. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The digital signal to be converted consists of 16 bits _D1 to _D16 , and this digital signal is divided into two groups of 8 bits D1 to _D16 . ₈ , _D9 to _D16 . Integrating circuits I ₁ and I ₂ each consist of operational amplifiers 9 and 10, resistors 11 and 12 connected to one input terminal thereof, and capacitors 13 and 14 connected between one input terminal and output terminal. ,
Further, switch means 15, 1 for discharging the accumulated charges are provided at both ends of the capacitors 13, 14.
6 is provided. Integrating circuits I ₁ and I ₂ are continuously connected via switch means 17 , and reference potential source 19 is connected via switch means 18 to integrating circuit I ₁ .

The control circuit 20 controls the switching means 15, 16, based on the outputs of the time generating circuit 21 and the counter 22.
The opening and closing of 17 and 18 is controlled according to a predetermined procedure. The time generating circuit 21 counts the applied reference clock pulse CLK and outputs each of the two divided digital signal groups _D1 to _D8 and _D9 .
~ corresponds to the least significant bit of D ₁₆ , i.e. D ₁ and D ₉ ;
Create weighted times T ₁ and T ₂ in the ratio ^1:28 . For example, time T ₁ is the reference clock pulse
If CLK is 1 clock, _T2 is ²⁸ clocks. 23 is the lower 8 bits of the digital signal D ₁ to _{D 8}
A latch circuit 24 stores the upper eight bits D ₉ to D ₁₆ of the digital signal, and the digital signal to be converted is divided and stored in the latch circuits 23 and 24. Furthermore, the digital signals stored in the latch circuits 23 and 24 are
It is controlled by the control circuit 20 and sent to the counter 22 via the multiplexer 25 according to a predetermined procedure. The counter 22 is, for example, a subtraction counter or a counter with coincidence detection, and is based on the applied reference clock pulse.
When the number of CLKs equal to the data value represented by the transmitted digital signal is counted, an output is issued to the control circuit 20. That is, it creates a time corresponding to the data value of the digital signal.

Figure 3 is a timing diagram showing the operation in the block diagram shown in Figure 2, where Figure 3A shows the output voltage _V1 of the integrating circuit _I1 , Figure 3B shows the output of the integrating circuit _I2 Indicates voltage V ₂ . The operation of FIG. 2 and the DA conversion method will be explained below based on FIG. 3.

First, the 16-bit digital signal to be converted is
_D1 to _D16 are the lower 8 bits _D1 to _D8 and the upper 8 bits
D ₉ to _{D 16} are divided into two, each with a latch circuit 23 and 2.
4 is stored. Next, the control circuit 20 switches the switch means 1 between timing _t1 and timing _t2 .
By closing and opening 5 and discharging the charge in the capacitor 13, the output voltage of the integrating circuit _I1 is
Set V ₁ to OV, that is, the initial state. Then, at timing _t2 , the switch means 18 is closed,
While connecting the reference potential source 19 to the integrating circuit _I1 ,
The time generating circuit 21 is operated to count ²⁸ reference clock pulses CLK to create time _T2 . meanwhile,
The integrating circuit _I1 performs an integrating operation of the reference potential source 19,
Its output voltage V ₁ rises with a slope determined by resistor 11 and capacitor 13 . On the other hand, control circuit 2
0 is before the time generation circuit 21 counts 2 ⁸ CLK.
The switching means 16 is opened and closed between timings _t3 and _t4 , and the capacitor 14 is discharged to initialize the integrating circuit _I2 . At timing _t5 , when the time generating circuit 21 outputs an output indicating the end of ²⁸ CLK counting, the control circuit 20 switches the switch means 1.
At the same time, the switch means 17 is closed and the integration circuit _{I 2 is} closed.
Apply the output voltage of integrating circuit _I1 to . The output voltage V ₁ of the integrating circuit I ₁ at this time is an electrical quantity weighted corresponding to the 9th bit D ₉ of the digital signal,
This output voltage V ₁ is converted into a digital signal by integrating circuit I ₂ .
D/A conversion of the upper 8 bits is performed by integrating the time corresponding to the data values _D9 to _D16 .
That is, at timing _t5 , the digital signals _D9 to _D16 stored in the latch circuit 24 are applied to the counter 22 via the multiplexer 25, and the counter 22 receives the same number of data values as the reference clock pulse CLK. It counts, and outputs an output indicating the end of counting to the control circuit 20, for example, at timing _t6 . Then, the control circuit 20 switches the switch means 1
7 is opened to stop the integrating operation of the integrating circuit _I2 . Therefore, the output voltage _V2 increased by integrating the output voltage _V1 becomes an analog quantity corresponding to the upper 8 bits _D9 to _D16 .

Next, between timings _t6 and _t7 , the switch means 15 is opened and closed, and the integration circuit _I1 is initialized. Then, at timing _t7 , the switch means 18 is closed, and the time generating circuit 21 generates 1CLK.
At the time of counting, that is, at timing _t8 after time _T1 , the switch means 18 is opened. Therefore, the output voltage V ₁ at this time is a weighted electrical quantity corresponding to the first bit D ₁ of the digital signal.
Also, at timing _t8 , the switch means 17
By closing the integration circuit _I2 , the upper 8 bits _D9 to _D16 held by the previous integration operation are
The output voltage V ₁ weighted corresponding to the first bit is integrated and added to the electrical quantity corresponding to the first bit. At this timing _t8 , the digital signals _D1 to _D8 stored in the latch circuit 23 are sent to the multiplexer 2.
5 to the counter 22, and the counter 2
2 counts the same number of reference clock pulses CLK as the data values of digital signals _D1 to _D8 , timing _t9
At this point, the switch means 17 is opened and the integral operation is stopped. Therefore, the output power _V2 of the integrating circuit _I2 at this time is output as an analog signal obtained by converting the digital signals _D1 to _D16 .

In this way, by creating a weighted time corresponding to the least significant bit of each group by the time generation circuit 21 and using that time as the integration time of the integrating circuit _I1 , the least significant bit of each group Create a weighted electrical quantity corresponding to
DA conversion is performed by integrating with I ₂ . Also, one period of D-A conversion is _t1 to _t9 , and the reference clock required for the integration time excluding the extremely short initialization time is ²⁸ + 1 + D _{1 to 8} + D _{9 to 16} CLK , and the maximum is 769CLK. On the other hand, according to the conventional integration method shown in Fig. 1, a maximum of 2 ¹⁶ CLK,
In other words, 65536 CLK are required. Therefore, the conversion time for one cycle is significantly shortened compared to the conventional one, resulting in a DA converter circuit capable of high-speed operation. Furthermore, the control circuit 20, time generation circuit 21, latch circuits 23, 24, multiplexer 25, and counter 22 that control the switch means 15, 16, 17, and 18 can all be configured by digital circuits.
This eliminates the need for special circuits or analog circuits that require precision, making the circuit easier to integrate.

In the embodiment shown in FIG. 2, the 16-bit digital signals D ₁ to D ₁₆ to be converted are divided into two
There are four groups of 4 bits each, namely D ₁ to D ₄ , D ₅ to D ₈ , D ₉ to _{D 12} ,
It can also be divided into D ₁₃ to D ₁₆ . in this case,
The time generation circuit 21 generates a time _T1 corresponding to the first bit _D1 (for example, one CLK), a time T2 corresponding to the fifth bit D5 (for example, _four CLK2), and a time _T2 corresponding to the fifth bit D5 (for example, ^four CLK2).
The time T ₃ (e.g. ⁸ CLK2) corresponding to D ₉ and the 13th
Time T ₄ corresponding to bit D ₁₃ (for example, CLK2 ¹²
), and the latch circuit 2
3 and 24 are four latch circuits composed of 4 bits. Then, for each group, integrate circuit I ₁
A weighted electrical quantity is created based on times T ₁ , T ₂ , T ₃ , and T ₄ , and the electrical quantity is integrated over time corresponding to the data value of the group using an integrating circuit I ₂ , and the results are added. By doing so, DA conversion is performed. Also, when dividing into three groups, D ₁
Even when the number of bits in each group is different, such as _{.about.D.sub.5} , _D.sub.6 to _D.sub.10 , and _D.sub.11 to _D.sub.16 , DA conversion can be performed using the same procedure.

Note that the switch means 15, 1 shown in this embodiment
6, 17, and 18 are electronic switches such as analog switches using C-MOS transistors.

As described above, according to the present invention, by taking advantage of the feature of the integration method, that is, its excellent linearity, and further controlling the integration time by temporal weighting to create a weighted electric quantity, A D-A conversion circuit with reduced distortion can be obtained, and by dividing an n-bit digital signal into arbitrary groups of arbitrary number of bits and performing conversion for each group, even in the case of high resolution. Conversion time is shortened and high-speed operation can be performed. Furthermore, there is also the advantage that no special circuit is required, making it easier to integrate the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram explaining the operation of the block diagram shown in FIG. 9, 10... operational amplifier, 11, 12... resistor, 1
3, 14... Capacitor, 15, 16, 17, 18
...Switch means, 19...Reference potential source, 20...Control circuit, 21...Time generation circuit, 22...Counter, 2
3, 24...Latch circuit, 25...Multiplexer.

Claims (1)

[Claims] 1. An integrating circuit that is continuously connected in multiple stages, a reference potential source for applying a reference voltage to the first stage of the integrating circuit, and between the reference potential source, the first-stage integrating circuit, and each integrating circuit. Interposed switch means and n to be converted
A memory circuit that divides and stores a digital signal of bits into arbitrary N groups, a counter that counts the contents of the memory circuit using a reference clock pulse, and a time corresponding to the least significant bit of each divided group as a reference. A time generation circuit generated by a clock pulse, and the opening and closing of the switching means are controlled based on the count time of the counter according to the N groups of digital signals and the time generated by the time generation circuit. a control circuit, generating a weighted quantity of electricity for each group by an integrating circuit before the final stage based on the time generated by the time generation circuit, and generating a count time of the counter according to each group. A D-A conversion circuit characterized in that the weighted electric quantity is integrated by an integrating circuit in the final stage based on the above-mentioned, and a desired analog signal is obtained. 2 Divide the digital signal consisting of n bits to be converted into an analog signal into N groups, and apply the weighted electrical quantity corresponding to the least significant bit of each group before the final stage of an integrating circuit connected in multiple stages. The electrical quantity generated before the final stage is integrated in the final stage integrating circuit for a time based on the data value of the group, and the electrical quantity for each group is held in the final stage integrating circuit. A D-A conversion method, characterized in that the output of the final stage integrating circuit is extracted as an analog signal.