JPS5817728A - Composite type analog-to-digital converter - Google Patents

Abstract

PURPOSE:To remarkably decrease the conversion time, by constituting the titled converter with a plurality of charge balancing type A/D conversion circuits and sample hold circuits of the same number and an A/D conversion circuit at the final stage. CONSTITUTION:First, a charge balancing type A/D conversion circuit 22 is operated in a prescribed time for conversion, an output signal of an integrator included in the circuit 22 is picked in a sample hold circuit 23 and this voltage is stored. Next, a charge balancing type A/D conversion circuit 24 is operated for a prescribed time and the output value of the cicuit 23 is converted to a digital value. Further, a sample hold circuit 25 picks up an output signal of the integrator included in the circuit 24 and this voltage is stored. Then, an A/D conversion circuit 26 is operated for a prescribed time, and an output value of the circuit 25 is converted into a digital value. Further, a digital value synthesis circuit 27 gives a weight to output data of the circuits 22, 24, and 26 and sums the result to obtain the final digital value, which is outputted to an output terminal 28. Thus, the conversion time can remarkably be decreased without losing the conversion accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION In recent years, with the spread of digital devices such as computers, the need to digitize physical quantities such as voltage, current, and temperature has rapidly increased.

Techniques for digitizing these analog quantities have been around for a long time, and the methods can be broadly classified into three types. These are called an integral method, a feedback comparison method, and a non-feedback comparison method.

Of these methods, the present invention basically belongs to the integral method, but it belongs to a new method consisting of a plurality of conversion circuits, and the number of conversions ranges from 218 to 221, which is the most accurate analog method in the current technology. -Relating to digital converters.

Conventionally, the integral method has been widely used for high-precision conversion. This is because highly accurate analog-to-digital conversion is possible. However, when performing analog-to-digital conversion with 218 conversions using the conventional integration method, it usually takes about 1 degree of time, and if the number of conversions is 221, it takes about 10 seconds. In fields such as chemistry, medicine, and measurement, there is a strong desire to complete conversion in a shorter time than this, but it is difficult to meet these demands with conventional analog-to-digital conversion technology.

SUMMARY OF THE INVENTION In response to these demands, an object of the present invention is to provide a novel analog-to-digital converter that is highly accurate and has significantly shorter conversion time than the conventional integration method.

FIG. 1 is a diagram illustrating the operating principle of a charge-balanced analog-to-digital converter, which is often used as a high-precision analog-to-digital converter.

In FIG. 1, the analog input signal is added to 1.

This analog input signal passes through a resistor 2, an input switch 3, and is applied to the (-) input of an integrator 4. A reference current is applied to the (-) input of this integrator 4 from a reference power supply 9 through a resistor 8 and a switch 7. The output of the integrator 4 is applied to one input of the voltage comparator 11.
A constant voltage is applied from the comparison voltage source 10 to the other inputs of the . The output of voltage comparator 11 is applied to the D input of D-type flip-flop 12. The Q output of this flip-flop 12 is applied to one input of an AND gate 13. The output of the AND gate 13 is output to the output terminal 14 and controls the switch 7.

A clock signal of a constant frequency is applied from a clock input terminal 15 to the other input of the large CK input AND gate 13 of the D-type flip-flop 12.

The operation shown in FIG. 1 will be explained with reference to FIG. 2.

Before starting analog-to-digital conversion, the input switch 3 is in the OFF state and the integrator reset switch 6 is in the ON state. In this state, the output signal of the integrator becomes zero volts, and since a constant negative voltage is applied to the (-) input of the voltage comparator 11, the output of the voltage comparator 11 becomes high level. Since the clock signal is continuously applied to the clock input terminal 15, the Q output of the D-type flip-flop 12 is at a high level. As a result ANI) Gate 13
The output becomes low level, and the switch 7 continues to be in the OFF' state.

Immediately after starting the conversion (the starting point is shown as To in FIG. 2), the integrator reset switch 6 is turned off.
The input switch 3 is turned on.

Therefore, the analog input signal is integrated by the integrator 4. Over time, the output voltage of integrator 4 continues to drop (here, assuming the analog input signal is of positive polarity) and eventually becomes lower than the voltage level of comparison voltage source 10 (designated as Vc in FIG. 2). In this state, the output of the voltage comparator 11 goes low, and the Q output of the D-type flip float 12 goes low at the rising edge of the clock signal.

Next, when the clock signal becomes a low level, the output of the AND gate 13 becomes a high level, and the switch 7 is turned on. This ON state lasts as long as the clock signal is at a low level. When the switch 7 is in the ON state, a current having a polarity opposite to that of the analog input signal (here, negative polarity) flows from the reference voltage source 9 through the resistor 8 to the input of the integrator 4, thereby increasing the output of the integrator 4. (This interval is shown as 1 in Figure 2) As a result, at the rising edge of the next clock, the integrator 4
output becomes higher than the comparison voltage VC, the D input of the D-type flip-flop 12 changes to a high level, and therefore the Q output also changes to a high level. In this state, even if the clock signal becomes low level next time, the output of the AND gate 13 continues to be low level. That is, the switch 7 is not turned on and the output of the integrator continues to fall. (The interval between 1 and 2 is shown as tc4 in FIG. 2) At the next rising edge of the clock signal, the output of the integrator 4 is lower than the comparison voltage VC, so the output Q of the D-type clip-flop 12 remains low. , turn on switch 7.

As a result of this operation, the amount of charge due to the analog input signal input to the integrator 4 and the amount of charge due to the reference power source are kept in equilibrium.

(From here on, this analog-to-digital conversion method is called the charge balance method.) - After continuing the above operation for a certain period of time (indicated by T in Figure 2),
Turn input switch 3 and switch 7 off. (This section is shown as 1 in FIG. 2) Next, the integrator reset switch 6 is turned on, and this conversion operation is completed.

The number of times the switch 7 is in the ON state during this conversion operation is the output digital value.

Now, in order to double the number of conversions in this charge-balanced analog-to-digital converter, the clock signal frequency must be doubled.
Either it needs to be doubled or the conversion time needs to be doubled. If the clock signal frequency is doubled, the conversion nonlinearity error will be doubled if the circuit configuration is the same. However, it is common sense that if the number of conversions is doubled, the conversion nonlinearity error must be halved. For this reason,
If the circuit configuration is the same, doubling the number of conversions will halve the clock signal frequency and quadruple the conversion time. In other words, this type of analog signal has a large number of conversions.
The conversion time of digital converters becomes unbearably large. To solve this problem, we made improvements to the circuit configuration, especially the widening of the integrator's bandwidth and the faster switching speed of the switch.

Even if maximum efforts are made to improve the circuit configuration, it is difficult to increase the clock signal frequency higher than 200 kilohertz in a converter with 218 conversions at the current level of technology.

If the clock signal frequency is 200 kilohertz, the conversion time for this converter with 218 conversions is about 1.31 seconds.

There are some differences between other integral type analog-to-digital converters (older ones), such as single-sweep type analog-to-digital converters, double-integrating type analog-to-digital converters, etc., but roughly speaking, In other words, the same can be said of the charge-balanced analog-to-digital converter described above.

However, despite the technical difficulties, there is a strong demand from various fields for a larger number of conversions and a shorter conversion time.

The most difficult of these was 221 conversions (approximately 2×10') and a conversion time of 2 milliseconds. In order to realize an analog-to-digital converter that satisfies this performance using the charge-balanced type described above, the clock signal frequency must be 1.
000 MHz.

It is easy to understand that this is not possible.

An object of the present invention is to make it possible to realize an analog-to-digital converter with high precision and short conversion time, which is impossible to achieve with the conventional technology.

To achieve this objective, the present invention combines one analog-to-digital converter with one or more charge-balanced analog-to-digital converters.
It consists of a digital conversion circuit, the same number of sample and hold circuits, and an analog-to-digital conversion circuit placed at the end (the conversion method may be arbitrary). The analog input signal is connected to the input of the first analog-to-digital conversion circuit, the output of the integrator of this conversion circuit is connected to the input of the first sample-and-hold circuit, and the output of this sample-and-hold circuit is connected to the input of the second analog-to-digital conversion circuit. Connect to the input of the analog-to-digital converter circuit. Similar connections are then made up to the analog-to-digital conversion circuit placed at the end. In this state, the output signal of the integrator of the first analog-to-digital conversion circuit at the end of its operation is extracted and held in the first sample-and-hold circuit, and the output signal of this sample-and-hold circuit is transferred to the second analog-to-digital conversion circuit. The analog-to-digital conversion circuit converts it into a digital value. The output signal of the integrator of this second analog-to-digital conversion circuit at the end of conversion is extracted and held in the second sample-and-hold circuit, and the output signal of this sample-and-hold circuit is used for the next analog-to-digital conversion circuit. Convert it to a digital value using a digital conversion circuit. This operation is repeated sequentially up to the last analog-to-digital conversion circuit. Through this operation, each analog-to-digital conversion circuit divides and converts a portion of the digital output that is finally required.

That is, the first analog-to-digital conversion circuit converts the most significant part of the digital output, and the second analog-to-digital conversion circuit converts the most significant part of the digital output.
The digital conversion circuit converts the next most significant part of the digital output, and the last analog-to-digital conversion circuit converts the least significant part of the digital output.

When the operation of each of these analog-to-digital conversion circuits is completed, the output data of each conversion circuit is weighted and added to obtain a final digital output.

Now, the principle of this operation will be explained with reference to FIG.

The output voltage V of the integrator at the end of conversion time T1 in FIG. 2 represents the amount of residual charge remaining without being digitized in the analog input signal input to the integrator.

This V corresponds to the remainder in division in mathematics. In division, the remainder is multiplied by the base number (10 times if it is a decimal number)
After expanding the above V by an appropriate multiple, so that if we continue the division, we can obtain a lower division result.
Digitization by the second analog-to-digital conversion circuit yields a lower-order digital value. In addition, these two
After expanding the output voltage of the integrator at the end of conversion of the th analog-to-digital conversion circuit by an appropriate multiple,
Digitization by a third analog-to-digital conversion circuit yields a lower-level digital value.

The fact that this operation can be repeated an arbitrary number of times can be easily understood from the previous example of division in mathematics. After digitization is completed in all conversion circuits, the desired digital output is obtained by adding weights to the output digital values of each female switching path and adding them together.

In order to expand the above-mentioned V by an appropriate multiple, it is sufficient to amplify (1) using an operational amplifier. Furthermore, it is well known that the same effect can be obtained by simply reducing the resistance value of resistor 2 in FIG. 1 without using an operational amplifier.

Now, let us compare the conversion times of a conventional charge-balanced analog-to-digital converter and an analog-to-digital converter according to the present invention. Now, assuming that the number of conversions is N1 and the frequency of the clock signal is Fc, and the analog-to-digital converter according to the present invention is composed of M conversion circuits, the conversion time is approximately as follows.

Conversion time in the conventional method TA TA = "- [: seconds] ...... (1) Fc Conversion time in the method of the present invention Ts + 4'1 High-precision analog-to-digital conversion as described above in these formulas Let us apply an example of the numerical values required for the converter.Assuming that the number of conversions in this converter is 2211, the clock signal frequency is 200 kHz, and the number of conversion circuits used in the converter of the present invention is 3, the conversion using the conventional method is Time T = 10.486 seconds; conversion time Tm = 0.00064 seconds according to the method of the present invention.

Based on these values, if the present invention is used, the conversion time can be reduced to 1/10000 or less without impairing conversion accuracy, and the above-mentioned object of the present invention can be achieved.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 3, 21 is an analog signal input terminal, 22 is a first analog-to-digital conversion circuit, 23 is a first sample-and-hold circuit, 24 is a second analog-to-digital conversion circuit, and 25 is a second sample.・Hold circuit,
26 is a third analog-to-digital conversion circuit, 27 is a digital value synthesis circuit, 28 is a digital output terminal, 29
3 is a conversion start signal input terminal, and 30 is a control circuit. Here, each of the 22 and 24 analog/digital conversion circuits is based on a charge balance method, and the 26 analog/digital conversion circuits are based on a charge balance method.
Digital conversion circuits may be based on a charge balance method;
It may also be based on other conversion methods.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4.

When a conversion start signal is applied to the conversion start signal input terminal 29, the control circuit 3o controls each analog signal 22, 24, and 26.
A control signal is sequentially sent to the digital conversion circuit, each of the sample/hold circuits at 23 and 25, and the digital value synthesis circuit at 27, causing each of them to perform the following operations.

First, the first analog-to-digital conversion circuit 22 starts the conversion operation at T in FIG. ), and the conversion operation is terminated after a certain period of time (T in FIG. 4).

) together with the first sample and hold circuit 2
3 extracts the output signal of an integrator (not shown) included in the first analog-to-digital conversion circuit 22 and holds this voltage.

Thereafter, the second analog-to-digital conversion circuit 24 is caused to start a conversion operation, and the output signal of the first sample-and-hold circuit 23 is converted into a digital value. After a certain period of time, the conversion operation of the second analog-to-digital conversion circuit 24 is terminated (shown as T7 in FIG. 4). - Next, the second sample-and-hold circuit 25 extracts the output signal of the integrator (not shown) included in the second analog-to-digital conversion circuit 24, and holds this voltage.

Thereafter, the third analog-to-digital conversion circuit 26 is caused to start a conversion operation (shown as T2 in FIG. 4), and the output signal of the second sample-and-hold circuit 25 is converted into a digital value. The conversion operation of the third analog-to-digital conversion circuit 26 is terminated after a certain period of time.
). After that, the digital value synthesis circuit 27 receives 22
．． The output data of each of the analog-to-digital conversion circuits 24 and 26 are weighted and added to obtain a final digital value, which is output to the digital output terminal 28.

In FIG. 4, the next conversion start signal is T,. It has been added in After this T1°, the above-described operation is repeated.

Now, the first analog-to-digital conversion circuit 22 has T,
TI after that point. No action has been taken until now. That is, T. It is possible to move forward up to 18 points in time. This means that the conversion time of the embodiment of FIG. 3 is (T
, -T,).

Now, in the embodiment shown in Fig. 3, a sample-and-hold circuit is placed between each analog-to-digital converter circuit, but the function of this sample-and-hold circuit can be added to the analog-to-digital converter circuit by making some improvements. can be set. This can be done by turning off both the input switch 3 and the switch 7 at the end of the conversion in FIG. 1 (since the switch 6 is in the OFF state during the conversion).
The output signal of the integrator 4 at the end of the conversion can be held by itself. Using this principle, the sample and
The hold circuit can be omitted.

The fifth example shows an example in which this sample-and-hold circuit is omitted.
As shown in the figure.

This embodiment will be described in detail below with reference to the drawings.

In FIG. 5, 41 is an analog signal input terminal, 42 is a first analog-to-digital conversion circuit, 43 is a second analog-to-digital conversion circuit, and 44 is a third analog-to-digital conversion circuit.
Digital conversion circuit, 45, digital value synthesis circuit, 4
6 is a digital output terminal, 47 is a conversion start signal input terminal, and 48 is a control circuit. Here, each of the analog-to-digital conversion circuits 42 and 43 is based on a charge balance method, and the analog-to-digital conversion circuit 44 may be based on a charge balance method or another conversion method.

Next, the operation of the embodiment shown in FIG. 5 will be explained with reference to FIG.

When a conversion start signal is applied to the conversion start signal input terminal 47, the control circuit 48 controls each of the analog signals 42, 43, and 44.
Control signals are sequentially sent to the digital conversion circuit and 45 digital value synthesis circuits to cause each to perform the following operations.

First, the first analog-to-digital conversion circuit 42 is caused to start a conversion operation (T in FIG. 7 is closed), and the conversion operation is ended after a certain period of time. (Indicated as T in Figure 7)
After that, this first analog-to-digital conversion circuit 42
An integrator (not shown) included in the converter is operated to hold its output signal at the end of the conversion. Then the second
The analog-to-digital conversion circuit 43 of the first analog-to-digital conversion circuit 42 starts a conversion operation (indicated as T in FIG. Make it convert.

After a certain period of time, the second analog-to-digital conversion circuit 43
The conversion operation is completed (shown as T2 in FIG. 7).

After that, this second analog-to-digital conversion circuit 43
An integrator (not shown) included in the converter is operated to maintain its output signal at the end of the conversion. Next, the third analog-to-digital conversion circuit 44 is caused to start a conversion operation, and the output signal of an integrator (not shown) included in the second analog-to-digital conversion circuit 43 is converted into a digital value. After a certain period of time, the conversion operation of the third analog-to-digital conversion circuit 44 is terminated (indicated by T3 in FIG. 7). Thereafter, the digital value synthesis circuit 45 receives 42.
The output data of each of the analog-to-digital conversion circuits 43 and 44 are weighted and added to obtain a final digital value, which is output to the digital output terminal 46.

In FIG. 6, the next conversion start signal is added at Tlo.

This T. Thereafter, the above-described operation is repeated.

The first analog-to-digital conversion circuit 42 does not perform any operation after time T2 until TIO.

That is, T. can be moved forward to time T2. This shows that the conversion time of the embodiment of FIG. 5 can be defined as ('r2-'ro).

For a better understanding of the invention, embodiments will now be described with reference to detailed drawings.

In FIG. 7, 21 is an analog signal input terminal, 22 is a first analog-to-digital conversion circuit, 23 is a first sample-and-hold circuit, 24 is a second analog-to-digital conversion circuit, and 25 is a second sample・Hold circuit,
26 is a third analog-to-digital conversion circuit, 27 is a digital value synthesis circuit, and 28 is a digital output terminal. Further, 51 is an input switch control signal connection point, 52 is an integrator reset signal connection point, 53 is a sample/hold signal connection point, 54 is an input switch control signal connection point, 55 is an integrator reset signal connection point, and 56 is a sample/hold signal connection point. 57 is an input switch control signal connection point, 58 is an integrator reset signal connection point, 59 is a clock signal connection point, and 60 is a counter reset signal connection point, and these connection points are shown in FIG. are connected to each connection point with the same symbol.

In FIG. 7, the second analog-to-digital conversion circuit 24, the second sample-and-hold circuit 25, and the third analog-to-digital conversion circuit 26 are omitted to simplify the drawing. , the inside of 24 and 26 is 22
It is the same as the analog-to-digital converter circuit. However, for 24, the input voltage has the opposite polarity to 22.26, so some changes are made, such as reversing the polarity of the reference type source, but the basic circuit configuration is the same as 22.26. . ' In Figure 7, 71 is the resistor, 72 is the input filter, and 7 is the resistor.
3 is an integrator, 74 is an integrating capacitor, 75 is an integrator reset switch, 76 is a reference current switch, 77 is a resistor, 78 is a reference power supply, 79 is a comparison voltage source, 8o is a voltage comparator, 81 is a D type Operation of the embodiment of FIG. 7 will be a flip-flop, 82 is an AND gate, 83 is a sampling switch, 84 is a capacitor, 85 is a buffer amplifier, 131, 132, 133 is a counter, and 134.135 is an OR gate. will be explained with reference to the operation explanatory diagram of FIG.

Before starting conversion, the reset switch (75) of the integrators 22, 24, and 26 is in the ON state, and the integrator switch (72) is in the ON state.
) is in the OFF state, and the sampling switch (83) at 23.25 is in the ON state.

When the conversion starts here, 1. )
, the integrator reset switch 75 is in the OFF state, the power switch 72 is in the ON state, and the sampling switch 83 is in the ON state.
is in the OFF state. As a result, the first conversion operation is started, and the analog voltage applied to the analog signal input terminal 21 is converted into digital data by the same operation as explained in FIGS. 1 and 2. The converted digital data is obtained as the output K pulse train of AND gate 82. This pulse train is applied to the OR gate 1 while the first conversion operation is being performed (from t8 to t in FIG. 9).
34 and is counted by a counter 131. At the end of the first conversion operation (shown as tl in FIG. 9), the digital value corresponding to the analog voltage applied to the analog input terminal 21 is the output of the counter 131 (A, B, . . .
・Appears in H).

1 in Figure 9. At the point in time, the input switch control signal 51 goes low, turning off the input switch 72 and passing the reference current switch 76 through the AND gate 82.
is also turned off. Therefore, the output voltage of the integrator 73 at the end of the conversion is held in the integrator. This voltage is t in Figure 9.
Since the sampling switch 83 is turned on between , and 12, the signal is stored in the capacitor 84, and is held in the capacitor 84 even after the sampling switch 83 is turned off at time t2. The output voltage of the integrator 73 at the end of the first conversion operation, which is held in the capacitor 84, is passed through the buffer amplifier 85 while the second conversion operation is being performed (from t2 in FIG. 9). t3) is applied to the second analog-to-digital conversion circuit 24 as an analog signal to be converted to digital.

At time point 12 in FIG. 9, the input switch control signal 54 changes to high level, the integral reset signal 55 changes to low level, and the second conversion operation is started.

During this conversion operation, the pulse train appearing at the output of the AND gate of the analog-to-digital conversion circuit 24 is output from the OR gate 1.
35 and enters a counter 132 where the number of pulses is counted. When the number of pulses is greater than 2' (64), a carry signal is generated at the output terminal F of the counter 132, and this carry signal passes through the OR gate 134 and is counted by the counter 131.

The end point of the second conversion operation (shown as t3 in Figure 9)
54 input switch control signal becomes low level, 24
The output voltage of the integrator inside is maintained. This is similar to the operation of the integrator 73 at time t1.

In addition, the operation from t3 to t14 in FIG. 9 is similar to the operation from t to t2 in the same figure described earlier, so that the output voltage of the integrator at the end of the second conversion operation is transferred to the sample and hold circuit. 25, this voltage is held while the third conversion operation is performed.

At time t4 in FIG. 9, the input switch control signal 57 is at a high level, the integrator reset signal 58 is at a low level, and the third conversion operation is started.

During this conversion operation, the pulse train appearing at the output of the AND gate of the analog-to-digital conversion circuit 26 is
The number of pulses is counted here. When the number of pulses is greater than 2' (64), a carry signal is generated at the output terminal F of the counter 133, and this carry signal passes through the OR gate 135 and is counted by the counter 132.

At point to in FIG. 9, the series of analog-to-digital conversion operations is completed, and each circuit is reset to its initial state (before the start of the first conversion operation, that is, the state on the left side of 1g in FIG. 9), The signal (available from the converting signal output terminal 61 of FIG. 8) goes low, indicating to external equipment (eg, a computer) that the analog-to-digital conversion is complete. The external device knows from this signal that the conversion has ended and reads the digital output data from the digital output terminal 28.

Next, the operation shown in FIG. 8 will be explained.

In FIG. 8, 29 is a conversion start signal input terminal, 30 is a control circuit, 51 is an input switch control signal connection point, 52 is an integrator reset signal connection point, 53 is a sample/hold signal connection point, and 54 is an input switch control point. Signal connection point, 55
is an integrator reset signal connection point, 56 is a sample/hold signal connection point, 57 is an input switch control signal connection point, 5
8 is an integrator reset signal connection point, 59 is a clock signal connection point, 60 is a counter reset signal connection point, and each connection point from 51 to 60 is the connection point with the same symbol in FIG. 7 described earlier. Connected to points. Further, 61 is a signal output terminal during conversion.

In FIG. 8, 140 is an oscillator, 141 is a timer circuit, 142 is an initial state setting circuit, 143 is an OR gate, 1
44 is a D-type flip-flop, 145 is a trigger type monostable circuit, 146,147°148.149,150,1
51, 152, 153 are OR gates, 154, 156,
157,158°159.160 are flip-flops. The operation of the embodiment shown in FIG. 8 will be explained with reference to the explanatory drawing in FIG. 9 (p. 7).

In FIG. 8, when the power is turned on, the initial state setting circuit 142 operates to reset the flip-flop 144. When the flip-flop 144 is reset, the output Q of the flip-flop 144 is at a low level.
Timer circuit 141 is also reset, and all seven flip-flops 154 to 160 are also reset.

In this state, the timer circuit 141 does not operate, and 51 to 5
The signals at each connection point up to 8 are held at the level prior to (on the left side) the time indicated as 18 in FIG. 9, and this state continues until a conversion start signal is applied to the conversion start signal input terminal 29.

Now, when a conversion start signal is applied to this input terminal 29, the flip-flop 144 is inverted and its output Q goes high. Now the timer circuit 141 starts operating,
After the set time elapses, each output terminal "v' ++
' 2 + ' 3 v t 4 °t° (This situation is shown as the timer circuit output signal in FIG. 9.) Also, the flip-flop 144
The inversion of is the flip-flop 154, 155, 156
, 157° 158, 159, 160 are released from the reset state, and each of these seven lip-flops
The counter 131 shown in FIG.
, 132, 133 are reset.

When the timer circuit 141 starts operating, a negative pulse is first generated at the output t8, and the flip-flops 154 and 15
5,156 is set.

This changes the input switch control signal at 51 to a high level, and the integrator reset signal at 52 and sample and hold signal at 53 to a low level. This situation is shown in FIG. 9, showing signal changes at different times.

Now, this condition continues until a negative pulse occurs at the output t1 of the timer circuit, but when a negative pulse occurs at the output t1 of the timer circuit, the flip-flops 154 and 156 are reset and the input switch control signal 51 changes to a low level, and the sample-and-hold signal of 53 changes to a high level.

This situation is shown in FIG. 9 as a signal change at time t1.

Similarly, every time a negative pulse is generated at each output of the timer circuit, each flip-flop is set or reset, and the signal at each connection point 51 to 58 changes as shown in FIG.

Now, when the output t of the timer circuit 141 and the K negative (7') pulse are generated, the D-type flip-flop 144 is reset, the signal at the conversion signal output terminal 61 changes to low level, and the external device is notified that the conversion has finished. Let me know. , timer circuit 1411 flip-flops 154, 155,
156, 157, 158°, 159, and 160 are also reset and return to the initial state.

The series of operations of the control circuit 30 is thus completed, and the initial state continues until the conversion start signal is applied to the conversion start signal input terminal 29 again.

Next, the embodiments shown in FIGS. 10 and 11 will be described in detail.

FIG. 10 is a diagram obtained by removing the first sample/hold circuit 23 and the second sample/hold circuit 25 from FIG. 7.

Since the reference numerals in FIG. 10 are the same as those in FIG. 7, their explanation will be omitted.

The operation of the embodiment shown in FIG. 10 will be explained with reference to the operation diagram shown in FIG. 12.

Before starting conversion, integrator reset and
Switch (75) is in ON state, also 22, 24, 26
The input switch (72) is in the OFF state.

When the conversion is started (shown as IS in FIG. 12), the integrator reset switch 75 is turned OFF and the input switch 72 is turned ON.

As a result, the first conversion operation is started, and the analog voltage applied to the analog signal input terminal 21 is converted into digital data by the same operation as explained in FIGS. 1 and 2. The converted digital data is obtained as an output of the AND gate 82 as a pulse train. this·(
While the first conversion operation is being performed (from 1S to t in FIG. 12), ! It passes through an OR gate 134 and is counted by a counter 131. At the end of the first conversion operation (indicated as t in FIG. 12), the digital value corresponding to the analog voltage applied to the analog signal input terminal 21 is output from the counter 131 (A, B...・H)
appears in

At time t in FIG. 12, the input switch control signal 51 becomes low level, the input switch 72 is turned off, and the reference current switch 76 is also turned off through the AND gate 82. Therefore, the integrator 7 at the end of conversion
The output voltage of 3 is held and is output as a hexaanalog signal which is converted into a digital signal while the second conversion operation is being performed (from t to t2 in FIG. 12).
It is added to the digital conversion circuit 24.

1 in Figure 12. At the point in time, the input switch control signal (54) applied to the analog-to-digital converter 24 is at a high level, the integrator reset signal (55) is at a low level, and the second
The conversion operation is started.

During this conversion operation, the pulse train appearing at the output of the AND gate passes through the OR gate 135 and enters the counter 132;
The number of pulses is counted here. This number of pulses is 26
(64) When the number is greater than the output terminal F of the counter 132
A carry signal is generated at , and this carry signal is sent to OR gate 1.
34 and is counted by a counter 131.

At the end of the second conversion operation (shown as 12 in FIG. 12), the input switch control signal 54 goes low, the integrator output voltage at the end of the second conversion operation is held, and the third conversion operation is applied to the third analog-to-digital conversion circuit 26 while this is being performed.

At time t2 in FIG. 12, the input switch control signal (57) applied to the analog-to-digital converter 26 becomes high level, the integrator reset signal (58) becomes low level, and the third
The conversion operation is started.

During this conversion operation, the pulse train appearing at the output of the AND gate enters a counter 133, where the number of pulses is counted. When the number of pulses is greater than 2' (64), a carry signal is generated at the output terminal F of the counter 133, and this carry signal passes through the OR gate 135 and is counted by the counter 132.

At time t in FIG. 12, the series of analog-to-digital conversion operations is completed, each circuit is reset to the initial state □ (the state before the start of the first conversion), and the conversion signal (the first
During conversion signal output terminal 61 in FIG. The external device knows the end of conversion from this signal and reads the digital output data from the digital output terminal 28.

Next, the eleventh operation will be explained.

In FIG. 11, 29 is a conversion start signal input terminal;
is a control circuit, 51, 54.57 is an input switch control signal connection point, 52, 56.58 is an integrator reset signal connection point, 59 is a clock signal connection point, and 60 is a counter reset signal connection point. Each connection point is connected to each connection point with the same reference numeral in FIG. 10 described above. Further, 61 is a signal output terminal during conversion.

In FIG. 11, 160 is an oscillator, 161 is a timer circuit, 162 is an initial state setting circuit, 163 is an OR gate,
164 is a D-type flip-flop, 165 is a trigger type monostable circuit, 166.167° 168 is an OR gate, 16
9,170,171°172.173 are flip-flops.

The operation shown in FIG. 11 will be explained with reference to the operation diagram shown in FIG. 12. - In FIG. 11, when the power is turned on, the initial state setting circuit 162 operates and the flip-flop 164
Reset. When this flip-flop 164 is reset, the timer circuit 161 does not operate and the 5
The signals at the connection points 1, 52, 54, 55° 57.58 are held at the level before (on the left) the time point shown as ts in FIG. continues until added.

Now, when a conversion start signal is applied to this input terminal 29, the flip-flop 164 is inverted and its output Q goes high. Now the timer circuit 161 starts operating,
After the set time elapses, the lip output terminal'S f tI
A pulse of quality is generated sequentially from t'2 to t'e. (This situation is shown in FIG. 12 as a timer circuit output signal.

) Also, what is the inversion of flip-flop 164? The reset state of the lip-flops 169, 170, 171, 172° 173 is released so that each of these clip-flops can operate according to the output pulse from the timer circuit 161, and the triggered monostable circuit 165 is triggered to generate a pulse with an extremely short time width to reset the counters 131, 132, 133 in FIG.

When the timer circuit 161 starts operating, a negative pulse is first generated at the output ts, and the flip-flop 7''169,1
70 to the set state. This causes the input switch control signal at 51 to go high and the integrator reset signal at 52 to go low. This situation is shown in FIG. 12 as a signal change at time ts.

Now, this state is the output t of the timer circuit 161.

This continues until a negative pulse is generated in the timer circuit 161.
When a negative pulse occurs at the output t, the flip-flop 169 is reset and 171 and 172 are set. This changes the input switch control signal 51 to low level, the input switch control signal 54 to high level, and the integrator reset signal 55 to low level. This is the first
This is shown as the change at the 17th point in Figure 2.

Similarly, every time a negative pulse is generated in each output of the timer circuit, each flip-flop is set or reset, and the signals at each connection point of 51, 52, 54, 55°57.58 are shown in Figure 12. Change as shown.

When a negative pulse is generated at the output t0 of the timer circuit 161, the D-type flip-flop 164 is set, and the signal at the converting signal output terminal 61 changes to a low level, notifying the external device of the end of the conversion.

Also, a timer circuit 161, a clip flop 169°1
70, 171, 172, and 173 are also reset and return to the initial state. The series of operations of the control circuit 30 is thus completed, and the initial state continues until the conversion start signal is applied to the conversion start signal input terminal again.

In the embodiments shown in FIGS. 7 and 8 described above, the number of conversions is 220 (
A high-accuracy, high-speed analog-to-digital converter with an input current of 1×10 6 ), a nonlinear error ILSB (approximately 1 millionth of the full scale), and a conversion time of 2.6 milliseconds can be obtained. The breakdown of the conversion time in this example is as follows: clock frequency 20
0 kilohertz, and the first conversion operation (t, and 1 in Figure 9)
．． 1.28 mIJ seconds for the second conversion operation (between t2 and t3 in the figure), and 0.64 mIJ seconds for the third conversion operation (between t4 and t in the same figure). 0.64 mIJ seconds, sampling operation (between t and t2 and between t3 and t4 in the same figure)
0.02 milliseconds are allocated for each time (during the period). Also the first
In the embodiments shown in FIGS. 0 and 11, a high-accuracy, high-speed analog-to-digital converter with a conversion count of 220, a nonlinear error IL8B, and a conversion time of 2.56 mIJ seconds can be obtained. The breakdown of the conversion time in this example is as follows:
kilohertz, 1.28 ms for the first conversion operation (between 1Fl and t in Figure 12), 0.64 ms for the second conversion operation (between tl and t2 in the same figure), and 0.64 ms for the second conversion operation (between tl and t2 in the same figure). 3 conversion operation f
0.64 milliseconds are assigned to the interval (between t2 and t3 in the figure).

If an analog-to-digital converter with the same number of conversions and nonlinear errors as those in these examples is realized using conventional technology,
The conversion time is approximately 5.24 seconds (time to count 220 200 kHz clocks).

Compared to the conversion time +b'l in the conventional technology, the conversion time in the present invention is 1/1985 (in the embodiments shown in FIGS. 7 and 8) and 1/2047 (in the embodiments shown in FIGS. 10 and 11). Examples).

Furthermore, in the embodiments of FIGS. 7 and 8, as shown in FIG. 9, the first analog-to-digital conversion circuit 22 does not perform any operation after time t2. Therefore, it is also possible to start a new analog-to-digital conversion at time t2. In this way, the conversion time is effectively 1.3 microseconds, which is still one half of the time previously mentioned.

Further, in the embodiments shown in FIGS. 10 and 11, as shown in FIGS. 12 and 12, the first analog-to-digital conversion circuit 22 does not perform any operation after time t2.

Therefore, it is also possible to start a new analog-to-digital conversion at time t2. In this way, the conversion time is effectively 1.92 milliseconds, which is 1/33 of the above value.
become.

In the above embodiment, an analog input signal is converted into a digital value by three sets of analog-to-digital conversion circuits, but this is not limited to three sets. An arbitrary number of two or more sets can be selected in consideration of the required number of conversions, required conversion time, etc.

In the embodiments shown in FIGS. 7 and 8 and the embodiments shown in FIGS. 10 and 11, the analog signal is converted into the upper 8 pits in the first conversion operation, the middle 6 pits in the second conversion operation, and the upper 8 pits in the second conversion operation. Although the lower 6 bits are converted into digital values in the conversion operation, this combination is not limited to this.

Any combination can be selected by considering the number of conversions required.

In addition, in these implementations, the synthesis of digital values was configured by combining three sets of counters, but if this analog-to-digital converter is used in computer application equipment,
It is also possible to have a computer perform these nine functions. Similarly, the functions of the control circuits in the embodiments of FIGS. 9 and 11 can also be performed by a computer, but this does not change the essence of the invention.

As described above, according to the present invention, the conversion time can be reduced to 1/2000 or less compared to the conventional method without impairing conversion accuracy.

That is, the present invention makes it possible to realize a high-precision, high-speed analog-to-digital converter that was not possible with the conventional technology, and can greatly contribute to the advancement of technology in fields such as chemistry, medicine, and measurement.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the operating principle of a charge-balanced analog-to-digital converter, Fig. 2 is an operating waveform diagram of Fig. 1, Fig. 3 is an illustration of an embodiment of the present invention, and Fig. 4 is a diagram illustrating the third embodiment of the present invention. FIG. 5 is an explanatory diagram of another embodiment of the present invention. FIG. 6 is an explanatory diagram of the operation of the embodiment of FIG. 9 is an explanatory diagram of the actual cape example Ω operation in FIGS. 7 and 8, FIGS. 10 and 11 are detailed diagrams of other embodiments of the present invention, and FIG. FIG. 12 is an explanatory diagram of the operation of FIG. 21... Analog signal power terminal, 22... First analog-to-digital conversion circuit, 23... First sample-hold circuit, 24... Second analog-to-digital conversion circuit, 25 ...Second sample and hold circuit, 26...Third analog-to-digital conversion circuit, 27...Digital value synthesis circuit, 28...Digital output terminal, 29...Conversion start signal input terminal , 30
...Control circuit. , 1st eye no ¥, 2nd eye 3rd eye February' 11 13 Kaya 1 mouth 1a 7/ 7J 7
7 7tagin M□

Claims (1)

[Claims] 1. One or more charge-balanced analog-to-digital conversion means, the same number of sample-and-hold means, and one optional conversion type analog-to-digital conversion means;
In a composite analog-to-digital converter comprising a digital value synthesis means for synthesizing the digital outputs of all the analog-to-digital conversion means described above, the charge-balanced analog-to-digital conversion means and the sample-hold means are converted into an analog signal. - The digital conversion means are arranged alternately in front, and the arbitrary conversion type analog-to-digital conversion means is arranged after the last sample and hold means, so that the analog input signal is converted to the first analog-to-digital conversion means. the output of an integrator included in this first conversion means is connected to the input of a first sample and hold means, and the output of this first sample and hold means is connected to a second analog-to-digital conversion After that, the same connection is repeated between the sample/hold means and the analog/digital means until the last analog/digital converting means, and the analog input signal is transferred to the first analog/digital converting means. At the end of this conversion, the output of the integrator included in this converter is extracted and held by the first sample and hold means, and the output signal of the first sample and hold means at this time is converted into a digital value. The second analog-to-digital conversion means converts it into a digital value, and thereafter the same operation is repeated between the sample and hold means and the analog-to-digital conversion means until the last analog-to-digital conversion means, and each of the above-mentioned analog and digital A composite analog-to-digital converter, characterized in that the digital outputs of the digital converting means are synthesized by the digital value synthesizing means to obtain a digital output corresponding to the analog input signal. -2. In the composite analog-to-digital converter according to claim 1, a function is added to the charge-balanced analog-to-digital conversion means to turn off all input signals of the integrator; By turning off all input signals of the integrator at the end of conversion of the analog-to-digital conversion means and causing the integrator to hold its own output signal at the end of conversion, the sample and hold means is unnecessary. A composite analog-to-digital converter characterized by the following.