JPS58186216A - High speed comparator circuit - Google Patents

Abstract

PURPOSE:To obtain a continuous comparated output signal in high speed, by operating two differential amplifying circuits alternately in a sufficiently long period, operating two latch circuits with clocks of the same phase in high speed and multiplexing alternate output. CONSTITUTION:An input signal from a terminal I and a comparison signal from a terminal 2 are given to a differential amplifier 30 and given to a latch circuit 31 via capacitors 20, 21. Further, an input of a differential amplifier 32 is short- circuited with a switch 15 and the input signal is cut off with a switch 14. Since switches 16, 17 are set on, an offset voltage of the differential amplifier is stored in capacitors 22, 23. Input terminals 46, 47 of the latch circuit are grounded in this case. A multiplexer 34 in figure is controlled so as to connect terminals 3 and 5, and terminals 4 and 5 in the opposite state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the connection of a comparator circuit consisting of a latch circuit and a 111 IIN circuit having an input offset voltage reduction circuit that reduces the input offset voltage by utilizing the voltage storage function of a capacitor. -It is.

Conventionally, in this woodcutter comparator circuit, the first stage differential increase -
Since the input offset voltage of the first path determines the degree of voltage, the capacitor is charged with the offset voltage during the standby period.
During operation, the voltage stored in the capacitor is subtracted from the signal voltage, amplified, and input to the latch circuit, which doubles the signal. Normally, the latch rotation of the signal and the operation of the differential amplifier are performed in a complementary manner, and when the differential amplifier is in a standby state, the tK lunner 1 is operating, and the amplified signal is latched in the koji period. In conventional comparator circuits, the pulse period of the control signal that controls the switch used to charge the offset voltage to the capacitor is the same as the pulse period of the control signal that controls the latch circuit. I was using it. As a result, the tring period is determined by the speed of one pass of offset voltage reduction, and since it is a latch circuit, there is a drawback that suitability cannot be utilized. In other words, if the capacitor's offset voltage charging time is 4I:*, the accuracy will be higher, but the numbering period will be ll'JIIK() and the aptitude will be lost, and conversely, the numbering period will be 4 times. And the capacitor's offset voltage charging time had to be shortened, resulting in a disadvantage that the accuracy decreased, and a comparator path with an uninterrupted integral could not be obtained.

An object of the present invention is to prepare two sets of input offset voltage reduction circuits (t-4h) differential amplifier circuits and one latch circuit to reduce input offset voltage by utilizing the voltage storage capability of a capacitor. The 2@ differential increase circuits with one short voltage reduction circuit are operated alternately at a sufficiently long cycle, and two latches t*tp! 3-. By operating in series with a phase clock signal. By multiplexing the significant frequency outputs alternately output from the two latch circuits, K eliminates the apparent waiting time and allows continuous significant comparator operation. It is an object of the present invention to provide a block comparator circuit that outputs a rate output signal at high speed.

According to the present invention, the jIl difference-increasing path has an input offset voltage reduction path using a capacitively coupled DCC restore two operated by the first clock signal;
a first two-bit circuit which operates with a second clock signal with the output of the differential amplifier circuit of llll as an input; A DCII storer that operates with
The 20th differential amplifier-single path has a manual offset voltage reduction circuit using a circuit, and the #*2 differential amplifier 11! The second latch circuit operates with the second clock signal using the output of the circuit as an input, and the second first latch circuit and the second
It is possible to obtain a multi-channel circuit that manually switches and outputs the output of the latch path at any time, and an insulating comparator circuit that can be used as a 4I circuit.

Next, the present JIII will be explained with reference to FIG.

FIG. 1 is a schematic diagram of a conventional comparator circuit. A signal voltage is applied to input terminal 1, and a reference voltage is applied to input terminal 2. Switch IO! It is controlled by a pulse voltage φ shown as IzlWl&lK, and is turned on in the time domain I and turned off in the time domain layer. switch 11
, 12, and 13 are controlled by the pulse voltage φ shown in Fig. 1m) I. The state of the switch shown in FIG. 1 indicates the state of the region layer mt. region! In this case, the input terminals of the differential amplifier are short-circuited by the switch 11, and a reference voltage is applied. At this time, differential increase II
The offset voltage of the IA device appears as a voltage difference between output terminals 40 and 41. Since the switches 12 and 13 are on at this time, the voltages at the output terminals 40 and 41 are applied to the capacitors 21 and charged. Information regarding the OR voltage is also stored in the capacitor 21 as a voltage difference. The latch WAWI31 is connected to the terminal 50 in Fig. 2 fl.
) Since the control signal φ indicated by l is applied, the region layer is in a standby state 11, and the voltage subtracted by the offset voltage that is amplified in the region layer and appears at terminals 42 and 0 is latched in the region layer and output from the output terminal. do.

In this conventional one-way approach, it is the addition of the container that determines the moderation and accuracy.
If the charging time is long enough, information about the offset voltage can be stored sufficiently and the accuracy will increase, but the disadvantage is that the moderation will decrease, and in the opposite case the speed will increase. However, the disadvantage is that the accuracy is reduced.

mis is a schematic diagram of a speed comparator circuit according to IjjK. ! Dynamic amplifier circuit and capacitance addition, 21 circuit containing single circuit and differential amplifier proverb and capacitance n, 23 circuit containing switch lO
- Operate complementary to the operation of the switch 17. In the third cause, switches 10, 15, 16, and 17 are on, and switches 11, 12, 13, and 14 are off, so the signal input from terminal 1 and terminal 2
The comparison voltage input from the input terminal is amplified by M# by the differential amplifier 30 and transmitted to the input terminals 42 and 43 of the latch circuit 310 via the capacitors 20 and 21. The offset voltage of the differential amplifier @ts30, 32 is charged in the input terminal 42, 0, and is transmitted to the input terminal 42, 0 in a form in which the offset voltage of the differential amplifier -53O is removed. On the other hand, at this time, the input terminal of the differential amplifier 5S32 is short-circuited by the switch 15, and the input signal is cut off by the switch 14. Also, since switches 16 and 17 are on, the differential increases @! The proverbial offset voltage is capacitance 2
Stored on 2.23. Latch circuit that input 熾子柘, 4
7 is grounded at this time. More than 1! The operations described above are carried out by the switches lO-17, which are controlled by control signals output from the output terminals -, 61 of the control value 4# generating circuit. switch 10, 1
5, 16, and 17 are controlled by control signals from the output terminal -, and switches 11, 12, and 13-14 are controlled by a control signal from the output terminal 61. Latch circuits 31, 33
is controlled by the control output from the control circuit through the control terminals 50, 51k. Latch circuit 3
The output terminal 3 of one circuit and the output terminal 4 of two circuits are connected to an output terminal 5 by a multiplex connector 34.

Figure 4 101 is the voltage waveform of the terminal group, JI 4 diagram till is the voltage waveform of terminal 61, Figure 4 101 is the voltage #1 of the terminal catfish.
．． llj is shown. The one-way switch-like layer shown in FIG. 3 shows a state controlled by the region I of the waveform in the IiJ diagram, and in the region I, the state of each switch is reversed. A significant signal is obtained at terminal 3 in region (2) and at terminal 4 in region I. Therefore, the multiple terminal 34 is controlled so that the terminals 3 and 5 are connected in the region (2), and the terminals 4 and 5 are connected in the region I. If you adjust the length of area 1 and the area, the capacity will be increased from K, 2'in, 23 will be a differential increase of 41ii! 1
The offset voltages of F30 and F32 can be controlled to be charged to the required accuracy.

On the other hand, the latch circuits 31 and 33 are shown in FIG.
The sampling speed can be determined by the control signal indicated by K, and the intensity can be determined independently of region 1.1. In general, -) Tsuchi circuits are capable of high-speed operation. Therefore, it can be seen that the single path using the Ij1jK according to the present invention has sufficient accuracy and can perform high-interruption sampling that takes full advantage of the high suitability of the latch single path, which has not been utilized in the past.

[Brief explanation of the drawing]

Figure 1II is a schematic diagram of a conventional comparator (b) circuit; , Fig. 4 (Kiri, (bl, (01 is shown in Fig. 3113, and the numbers in the figure indicate the following, respectively.), 32... Difference amplifier, 20,
21,22.23... Capacitor, 31,3
3...Latch path, A...Multi-prefner, A, 36...Control signal generator, 10°11, 12, 13, 14, 15, 16, 1
7...Switch, input...signal input terminal,
2...Reference voltage input terminal, 3.4°5...
・・Output terminal, sum, 41 , 42 , 43 , 44
, 45, mallet. 47... Wiring, 50, 51... Control signal input terminal, mark. 61, 52... Control signal output terminal.

Claims (1)

[Claims] A capacitively coupled DC list 7ler i[l! operating on the lth clock signal! A 105th differential amplifier circuit having a manual offset voltage reduction circuit using 1N1, a 105th tunnel operated by a clock signal of iris 2 with the output of the first differential amplifier circuit as input, and a cocoon 1 a 20th offset voltage reduction circuit using a capacitively coupled DC restorer-1 circuit which operates with a clock signal having a logically complementary relation to the first clock signal; The output of the 20 differential add-on circuit is used as an input, and the 7M2 2-touch circuit operates with the clock signal of the iris 2, and the output of the #1 first latch circuit and the 2-touch circuit of the iris 2 are input and switched at any time. A multipunctor circuit that outputs
A comparator circuit whose special feature is to have .