JPS6051901A - High sensitivity comparator - Google Patents

Abstract

PURPOSE:To increase a minute input voltage, and to obtain a comparator having a high sensitivity by switching and controlling plural capacitors from parallel to series. CONSTITUTION:A sampled input voltage V is applied to a terminal 1, an output S1 and S2 of a controlling circuit 23 become ''1'' and ''0'', respectively, by a clock signal C applied to the terminal by synchronizing with said voltage, and switches SW9-17 are switched to the connection side. As a result, capacitors C4-8 are connected in parallel and charged to the voltage V. Subsequently, when a prescribed time passes, the output S1 of the circuit 23 becomes ''0'', and the C4-8 are detached from the parallel state and hold the voltage V, respectively. Next, the output S2 become ''1'', the SW18-21 are switched to the connection side, the C4-8 are connected in series, and Vc=5V is applied to the positive terminal of a comparator amplifier circuit 22. By repeating this step by a sample period, the sampled input voltage is brought to five times, respectively, applied to the input side of the circuit 22, amplified and outputted from a comparison output terminal 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-sensitivity comparator used in high-performance analog-to-digital converters and the like.

Generally, an analog-to-digital converter (A/D converter)
In this system, applied analog inputs are sampled at regular intervals and then converted into digital values. By the way, the analog values sampled as in the book "U" show very small values in the lowest state.

The value given to the input of the built-in converter/lator needed to be about 2 mV or more. but,
In high-performance A/D converters, which are in high demand these days, a most significant value of several tens of microvolts may be added to the input of the comparator. The problem was that it didn't fit.

The object of the present invention is to solve the problems of the prior art.

The object of the present invention is to provide a high-sensitivity converter that can be used in high-performance A/D converters and the like by significantly increasing sensitivity even when receiving a minute input voltage.

According to the present invention, n capacitors (an integer of n≧2) and a total of 2
In order to connect all (n-1) first switches and these n capacitors in series, they have the same direction so that the charging voltages of these capacitors are respectively applied. A meter inserted between positive and negative terminals (
n-1) second switch group and a third switch inserted between the series connection side terminal of the lowest stage capacitor and the input terminal when the n capacitors are connected in series. A comparator amplifier circuit to which a switch and the other terminal of the bottom capacitor are grounded, and a voltage appearing between the other terminal of the top capacitor and ground is applied in a state where the n capacitors are connected in series. and, in a first step, the first switch group and the third switch are switched to the connection side in order to connect the n capacitors in parallel and charge these capacitors according to the input voltage. , control means for disconnecting the first switch group and the third switch and switching the second switch group to the connection side in a second step after a predetermined time elapses; The input voltage n
A highly sensitive comparator can be obtained in which double the voltage is applied to the comparator amplifier circuit.

Next, nine embodiments of the high-sensitivity converter and converter according to the present invention will be described with reference to one drawing.

FIG. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention. In this figure, 1 is an input terminal to which sampled analog input is applied.

Reference numeral 2 designates a comparison output terminal and a clock signal input terminal which receives a pulse input equal to the sample period of the input signal applied to the 3-digit terminal 1. 4 to 8 are capacitors charged by input signals, and this example shows the case where n = 5 capacitors. 9 is a switch for applying an input signal, 10-
17 is a switch for connecting all capacitors 4 to B in parallel.

18-21 are switches for connecting the capacitors 4-8 in series. 22 is a condenser amplifier circuit to which an input voltage increased several times is applied.

23 receives the clock signal from terminal 3 and switches switch 9.
This is a control circuit that controls the switching of 21 to 21.

In addition, when the capacitors 4-8 are connected in series, the terminal of the lowest stage capacitor 4 on the side opposite to the side to which the input signal is applied is grounded, and the terminal on the side opposite to the side to which the input signal is applied is grounded. The terminal on the opposite side is connected to the positive input terminal of the comparator amplifier circuit 22, and the negative input terminal is grounded. For example, the control circuit 23 is 2.

It consists of a circuit similar to a flip-flop. and,
When a clock pulse is received from terminal 3, the period is divided into two step sections, first and second, and output terminal S
From 1 to 2 For example, high level "1" in the first step section
, output a low level °°0″ in the second step section,
From the output terminal S2, a low level “
IQ $1. High level ``'1'' in the second step section
is now available.

To explain the operation of such a circuit, first, when the sampled input voltage V is applied to the terminal 1, the output S1 of the multi-control circuit 23 is synchronously applied to the clock signal C applied to the terminal 3. ``1'' (S2 is ``0''), and all switches 9 to 17 are switched to the connection side.As a result, the input voltage V applied to the terminal causes all the capacitors connected in parallel to 4 to 8 are charged, and the terminal voltage of capacitors 4 to 8 becomes equal to V. This state is referred to as (6) the first step. This step lasts for a predetermined time (this time (determined in relation to time constants, etc.) elapses.

The output S1 of the control circuit 23 becomes °゛0'' and the switch 9
~17 disconnection occurs, and the terminal voltage V is maintained in each of the capacitors 4 to 8 which are disconnected from the parallel state. Following this, the output S2 of the control circuit 23 becomes "'1",
Switches 18-21 are switched to the connection side. to this":
Recapacitors 4 to 8 are connected in series to supply V to the positive terminal of connomitor amplifier circuit 22. -5V is applied. Capacitors 4 to 8 are disconnected from the parallel state and switched to series,
Voltage V. The state until the signal is applied to the converter amplifier circuit 22 is defined as the second step. Thus, by repeating the sampling period consisting of the first and second steps, the sampled input voltage applied to the switch 1 is:
Each of the signals is multiplied by 5 and sequentially applied to the input side of the comparator 22.

In addition, in the embodiment described above, the case where n = 5 charging capacitors are used is taken as an example, but the present invention is not limited to this, or the number of capacitors and the number of switches corresponding to the capacitors may be changed. By controlling switching, the apparent input sensitivity of the comparator can be changed arbitrarily.

Further, in the above embodiment, the control outputs of the control circuit 23 are S and S2, but the switches 9 to 1
It goes without saying that if the operating functions of switch 7 and switches 18 to 21 are reversed, first and second step control is possible with one output consisting of "1" and 110 I+. Furthermore, MOS as a switch used
If a switch is used, it can be made compact and high speed can be achieved.

As is clear from the above description, according to the present invention, the input sensitivity of the comparator can be arbitrarily increased in relation to the number of capacitors by switching and controlling a plurality of capacitors from parallel to series. Therefore, the present invention can be applied to high-performance A/D converters that operate even with minute input voltages to improve their performance and reliability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention. In this figure, 4 to 8 are capacitors. 9 to 21 are switches, 22 is a comparator amplifier circuit, 2
3 is a control circuit. 3

Claims (1)

[Claims] 1. n (an integer of n≧2) capacitors and a total of 2 ( n-1
) first switch group and their mutual positive and negative terminals having the same direction so that the charging voltages of these capacitors are respectively applied, in order to connect all of these n capacitors in series. A total of (n-1) second switch groups inserted between the series connection terminal and the input terminal of the lowest stage capacitor when the n capacitors are connected in series. a third switch,
the other terminal of the lowermost capacitor is grounded, and a voltage appearing between the other terminal of the uppermost capacitor and the ground is applied in a state where the n capacitors are connected in series; In order to connect the n capacitors in parallel in one step and charge these capacitors with the input voltage, the first switch group and the third switch are switched to the connection side, and a predetermined After some time has passed. and control means for turning off the first switch group and the third switch and switching the second switch group to the connection side in the second step, thereby controlling the voltage n times the input voltage. A high sensitivity converter/4' regulator applied to the converter amplifier circuit.