JPH01259628A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain a highly accurate high-speed A/D converter which is not influenced by the dispersion of an offset voltage without providing an auto-zero period by providing a correction input terminal for each comparator. CONSTITUTION:Correction input transistor pairs 101-10n to correct the offsets of the comparators are connected in parallel to comparators 11-1n respectively. Further, correction input control circuits 111-11n to hold voltages to be corrected are connected to the correction input terminals. A first correction voltage generating circuit 12 is connected to one of the two correction input terminals and a second correction voltage generating circuit 13 is connected to the other input. Thus, even when the offset voltage is not 0, the value of a current flowing in the correction input transistor pairs 101-10n is adjusted and thus, two output voltages are equalized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an A/C converting analog signal into a digital signal.
[) It relates to converters, particularly integrated high-speed, high-precision A/D converters.

[Conventional technology]

A parallel type A/I) converter uses a large number of comparators (voltage comparators) to simultaneously compare the analog input voltage and a large number of reference voltages, determine which reference voltage the input terminal is close to, and This is a converter that converts the determination result into a binary code and outputs it as a digital output.

This parallel type A/D converter simultaneously compares the input voltage with the reference voltage at a momentary time, so it has the fastest conversion speed compared to other methods.

A block diagram of a typical conventional parallel A/D converter is shown in Figure 7.
As shown in the figure. The analog input voltage input from the input terminal 2 is simultaneously compared with a large number of reference voltages divided by the voltage dividing resistors 31 to 3n by a large number of comparators 11 to 1.1 (according to the resolution), and then the latch 4 Then, the encoder 5 converts it into a binary code and outputs it. Here, in order to obtain highly accurate conversion results, it is necessary that the variations in the offset voltages of the plurality of comparators be sufficiently small.

The offset voltage V o i s of the comparator is a deviation voltage for magnitude determination. In other words, an ideal comparator with an off-set voltage of zero would have a boundary between ln and ■ when the input terminal V in and the reference voltage Vroj are equal.
``Judge the size of el.However, in reality, V
r n and Vrez are minute voltage ■. □When determining the magnitude using the time when there is a deviation of 5 as the boundary, the voltage of this deviation V o
i s is called an offset voltage.

A conventional parallel A/D converter uses a differential amplifier type comparator. However, in the case of an inactive OS transistor, since the threshold voltage 'VLh of the transistor pair does not have good pairability, there is a problem in that the difference ΔVth between the threshold voltages becomes an offset voltage.

For this reason, it has been difficult to realize highly accurate A/D conversion.

The voltage comparator disclosed in Japanese Unexamined Patent Publication No. 1.33725/1983 solved this problem by devising a control clock for the chopper type comparator. FIG. 8 shows an A/D converter using this voltage comparator.

In this comparator, the input terminal and the reference voltage are switched by switches 6 and 7, and the voltage change is amplified and compared. At this time, there is a so-called auto-zero period in which switches 8, 9, and 6 are turned on to perform resets 1--. During this auto-zero period, the offset voltage of the inverter is accumulated and stored in the crotch coupling capacitor C. Therefore, at the ratio 1 occlusion u■, the offset voltage becomes effectively zero, and the inputs are compared. Therefore, by using this comparator, a highly accurate A/1 converter can be realized.

[Problem to be solved by the invention]

However, according to the above-mentioned conventional technology, since it is essential to provide an auto-zero period, there is a problem that the conversion speed cannot be sufficiently increased. This is because comparison cannot be performed during the auto-zero period, so the comparison speed is reduced by half.

An object of the present invention is to provide a high-precision, high-speed A/D converter that does not provide an auto-zero period and is not affected by voltage variations in the off-celler 1.

[Means for solving N problems]

The above purpose is to provide a differential amplifier used as a comparator with
This can be achieved by providing a new pair of correction input transistors for canceling the offset and applying a voltage of the required magnitude to the input terminals of this transistor pair (hereinafter referred to as correction input terminals).

The voltage required for correction can be found by providing a correction period and applying a gradually changing input to the correction input terminal during this period. Furthermore, the voltage necessary for this correction can be held by providing a storage capacity at the correction input terminal.

[Effect]

The correction input transistor pair is connected in parallel to the differential amplifier. i.e. load resistor (or active load device)
A correction input transistor pair is connected in parallel with the differential input transistor pair to a differential amplifier composed of a differential input transistor pair and a differential input transistor pair.

In this case, the sum of the current flowing through the differential input transistor pair and the current flowing through the correction input transistor pair flows through the load resistor. Therefore, when the values of the differential input transistor pair or the load resistance are unbalanced and the two voltages applied to the differential inputs (input voltage V in and reference voltage Vrez) are equal, the two output voltages are equal. Even if the offset voltage is not zero, that is, the offset voltage is not zero, the two output voltages can be made equal by adjusting the value of the current flowing through the correction input transistor pair. In other words, the offset voltage can be made zero.

The current flowing through the correction input transistor pair can be adjusted by changing the voltage applied to the correction input terminal. To find the voltage required for correction, apply the same voltage to the two input terminals of the differential input transistor pair, and then apply a constant voltage that does not change over time to one of the two input terminals of the correction input terminal. On the other hand, it can be found by applying a voltage that increases (or decreases) in proportion to time within a range that includes a constant voltage, and stops increasing (or decreasing) when the two output voltages become equal.

The voltage necessary for this correction can be held by providing a storage capacity at the correction input terminal.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.

FIG. 1 is a diagram showing the overall circuit configuration of an A/D converter according to the present invention. In Fig. 1, comparator 1° input terminal 22
Voltage dividing resistor 3. Latch 4. The function and configuration of the encoder 5 are the same as a typical conventional parallel A/D converter. In the present invention, correction input transistor pairs 101-10n are connected in parallel to each comparator 11-1n for correcting the offset of the comparator. Furthermore, correction input control circuits 111 to 111 . for holding voltages to be corrected at correction input terminals. is connected. A first correction voltage generation circuit 12 is connected to one of the two correction input terminals, and a second correction voltage generation circuit 13 is connected to the other input.

Next, the connection between each comparator and the correction input transistor pair will be explained using FIG. 1a, l in Figure 2
b is the original differential input transistor pair of the comparator,
10a and 10b are a correction input transistor pair. The respective sources are connected, and further connected to constant current sources 11 and 10i. Capacitors 10c and 10d for voltage storage are connected to the input terminals (correction input terminals) of the correction input transistor pair. The switches lla, llb, llc, and lid belonging to the correction input control circuit are switches controlled as shown in the following operation description.

This comparator is provided with two periods (modes): a correction period (correction mode) and an operation period (operation mode). In the correction period, the offset of each comparator is corrected, while in the operation period, the comparators whose offsets have been corrected perform a comparison operation.

The operation during the correction period is as follows. During the correction period, the switch lla is turned off, the switch 11b is turned on, and the reference voltage input from the input terminal 1f is applied to the gates of the differential input transistor pair la, lb. If the characteristics of these two transistors and the resistance values of the load resistors 1c and ld are the same, the output voltages of the output terminals 1g and lh are equal.

However, if the characteristics are different, the output voltage will be different.

Becomes an offset voltage. Therefore, slightly different gate voltages are applied to the gates of the correction input transistor pair 10a, 10b. Since the current from the original differential input transistor and the current from the correction input transistor are added together and flow through the load resistance, the correction input transistor has a current difference sufficient to correct the current imbalance of the original input transistor. If the offset voltage is generated, the offset voltage effectively becomes zero.

The voltage difference required to correct the imbalance can be found by fixing the voltage on one of the correction inputs and sweeping the other. FIG. 3 is a diagram showing the signal waveform and operation timing when finding this voltage difference. Waveform a is a voltage waveform (ramp waveform) that is generated by the correction voltage generation circuit 13 and changes over time. The waveform is the system clock φ used in the correction circuit and latch circuit. Waveform C is latch 4 during the correction period (see Figure 1)
This signal is fed back to the correction input control circuit 11 as shown in FIG.

The correction input control circuit 11 receives the output signal of the latch 4 (waveform C
) and the system clock φ. This AND signal d is applied to the switch li in FIG.
e, lid, and controls the switch so that its high level turns the switch on and its low level turns it off. The waveform e is the terminal to which the ramp waveform a is applied, for example, if it is 10f, the correction human power transistor 1 on the 10f side
0b is the gate voltage waveform. The waveform f is the gate voltage waveform of the correction input transistor 10a on the terminal 10e side to which a constant voltage is applied.

During the correction period, as described above, the gate voltages of the differential input transistor pair la and lb are equal. A constant voltage is applied to the terminal 10e, and a terminal 1°Oe is applied to the terminal 10f.
A ramp waveform a is applied that starts at a voltage lower than the constant voltage of and ends at a higher voltage. At the beginning of the correction period,
Terminal 1. Since the voltage of Of is lower than the voltage of terminal 10e, the output voltage of terminal 1h is higher than the output voltage of terminal 1g. This voltage difference is amplified by the second and third stage amplifiers shown in FIG. Set to 4. When the voltage at the terminal 10f gradually increases, the output voltage at the terminal 1h gradually decreases, and at a certain point becomes lower than the output voltage at the terminal 1g.

Therefore, the output signal of latch 4 changes from high to low as shown in waveform C. Waveform d, which is an OR signal of this signal and clock φ, becomes low level at this point. Therefore, the switch 11 was repeatedly turned on and off.
c.

The lid remains off from this point on. Therefore, the gate voltage of the transistor 10b stops increasing from this point on and maintains a constant voltage, as shown by waveform e.

The gate voltage thus found is 2 when the two voltages applied to the differential inputs of the comparator are equal.
This is the voltage that makes the two output voltages equal. This voltage is the voltage necessary for correction to make the offset voltage zero. Although the voltage required for correction is different for each of the comparators 11 to 11+ in FIG. 1, by sweeping the ramp waveform once, the voltage necessary for correction can be obtained for each comparator at the same time.

The voltage necessary for this correction can be held in a storage capacitor added to the correction input terminal. However, due to leaks, it cannot be held for very long. Therefore, it is necessary to periodically provide a correction period and refresh the value. In the case of a video signal A/D converter, the timing can be between horizontal synchronization signals. 63.5 μs as shown in Figure 4
Since about 5 μsec of the period of ec is a horizontal synchronizing signal, this period is used as a correction period, and the voltage necessary for correction is determined and held in a storage capacitor. During the comparison period other than the correction period, the comparator operates as if the effective offset voltage is zero due to the held correction voltage. Note that the voltage held in this sample and hold circuit must be shielded by fixing the conductive film on the insulating film to a constant potential so that it is not affected by capacitive coupling with other clocks in the chip. is desirable.

FIG. 5 shows another embodiment of the invention. In this embodiment, the differential amplifier is a differential amplifier circuit using an active load based on a current mirror circuit. In the embodiment shown in Fig. 2, a differential amplifier circuit using a load resistor is used as an example, but in the embodiment shown in Fig. 2, a differential amplifier circuit using an active load is also used. offset can be reduced.

This embodiment is an example in which the polarity of the transistors of the correction input transistor pair is changed. That is, the correction transistor is pMO8. In this case, the constant current source is connected from the power supply voltage vDD instead of the ground, but the other circuit connections and operating principles are exactly the same as in the previous example.

FIG. 6 shows another embodiment of offset correction.

In this case, a single constant current source is used to simplify the circuit.

Note that unless the device is an A/D converter for video, there is no synchronization signal for providing a correction period, so the correction period may be provided at an appropriate time such as when the power is turned on.

〔Effect of the invention〕

According to the present invention, since the offset voltage of each comparator can be reduced to a required level or less, highly accurate A/D conversion can be realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the overall circuit structure of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the circuit in FIG. 1 in detail, and FIG. 3 is a circuit diagram showing the operation timing of FIG. 1. FIG. 1... Comparator, 2... Signal input terminal, 3...
・Series voltage dividing resistor, 4...Latch, 5...Encoder, 10...Correction manual power, 11...Correction input control circuit,
12.13゛...Correction voltage generation circuit, la, lb...
(Comparator) input transistor, 1. oa, 10b
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7+ 9 rear 1. Toss 4 Tuna 5 Eshiko 7

Claims (1)

[Claims] 1. A parallel type or series-parallel type A/D converter comprising a large number of comparators, a reference voltage generation circuit, and an encoder, characterized in that each of the comparators is provided with a correction input terminal. A/D converter. 2. The A/D converter according to claim 1, wherein a differential amplifier is used as the comparator, and a correction input transistor pair is connected in parallel to the differential input transistor pair of the differential amplifier. /D converter. 3. The A/D converter according to claim 1, further comprising a sample hold circuit provided at the correction input terminal. 4. In the A/D converter according to claim 3, of the two correction inputs of the comparator, the sample hold circuit of one correction input is connected to the first correction voltage generation time of each comparator, and An A/D converter characterized in that each of the sample and hold circuits for correction input is connected to a second correction voltage generation circuit. 5. The A/D converter according to claim 4, wherein one of the correction voltage generation circuits is a circuit that generates a set voltage,
The other A/D converter is a circuit that generates a ramp voltage or a sweep voltage. 6. The A/D converter according to claim 5, wherein the A/D converter includes a circuit for extracting a periodic signal of the video signal, and a ramp voltage generation circuit whose sweep is started by the extracted signal. An A/D converter characterized by: 7. The A/D converter according to claim 4, wherein said sample and hold circuit is controlled by an output signal of said comparator itself. 8. The A/D converter according to claim 7, wherein the input switch of the sample and hold circuit is opened and closed by an AND signal of the output signal of the comparator and the clock signal. converter. 9. The A/D converter according to claim 8, wherein the output signal of the comparator is a signal latched by a latch circuit, and the latch timing is determined by the comparator output signal after the input switch of the sample and hold circuit is turned off. An A/D converter characterized in that timing is set to latch the output. 10. An A/D converter, wherein the sample and hold circuit according to claim 3 comprises a capacitor and a MOS switch. 11. The sample hold circuit according to claim 3 is an A/D converter, characterized in that a conductive film covered from above via an insulating film is fixed at a constant potential and shielded. 12. The A/D converter according to claim 6, wherein the A/D converter performs self-calibration (automatic offset correction) during a synchronization signal period.