JPH0583095A - Comparator - Google Patents

Abstract

PURPOSE:To eliminate the need for an adder circuit and to suppress the increase in the circuit scale by adjusting a variable voltage so as to cancel an offset voltage. CONSTITUTION:When a 1st switch 34 is thrown to select a prescribed constant voltage and a 2nd switch 36 is closed, a charge in response to an offset voltage is stored in a capacitor 33 and an output logic of an operational amplifier 31 depends on the relation of quantity between the charge and a variable voltage alphaat that time. Then the variable voltage alpha is adjusted so as to cancel the offset voltage. Thus, the offset voltage generated when a MOS transistor(TR) is adopted for the 2nd switch and the offset voltage due to the dispersion in the diffusion mobility in source and drain regions are compensated and the comparison with high accuracy is implemented and the increase in the circuit scale is avoided by eliminating the need for an adder circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator, and more particularly to a comparator having an offset voltage compensation function. Generally, the operational amplifier used for the comparator is
It is composed of a differential amplifier circuit composed of transistor pairs with uniform characteristics. However, since it is extremely difficult to form a transistor pair having completely uniform characteristics, it is unavoidable that an offset voltage is generated due to variations in characteristics. The offset voltage is a voltage that appears at the output when the input of the operational amplifier is set to zero, and is usually expressed by a value (V _OS ) converted into the input. That is, the voltage corresponding to V _OS is equivalent to being input in series with the input terminal of the operational amplifier. Therefore, since the normal input voltage is increased or decreased by the amount of this V _OS and the comparator operation (comparison operation) becomes inaccurate, the offset voltage compensation is indispensable when a highly accurate comparator is to be constructed. ..

[0002]

2. Description of the Related Art [First Prior Art] In FIG. 7, 10 is a switch for switching between a first input voltage V _IN1 and a predetermined constant voltage (0 V), and 11 is a second input voltage V _IN2 and a predetermined voltage. These two switches 10 and 11 are logic 1 of the timing signal φ _{1 when} a switch position (a constant voltage selection position) shown in the figure is turned off.
It turns on during the period and turns off during the logic 0 period. Switches 10, 1
When 1 is turned on, the inverting input terminal (-) of the operational amplifier 12
V _IN1 is added to the non-inverting input terminal (+)
To the voltage V _IN2 + α through the adder circuit 13. The F / F is a flip-flop that is set / reset according to the output logic of the operational amplifier 12.

Here, “α” is a voltage generated by a known auto-zero circuit (abbreviation A / Z) 14, and the auto-zero circuit 14 is 2 as shown in FIGS. 8 (a) and 8 (b).
A variable analog voltage “α” (increased at logic 0, which increases or decreases according to the digital input of value logic (logic 1 or logic 0)
The output logic of the operational amplifier 12 is used as a digital input.

In such a configuration, when the auto-zero circuit 14 is operated in the logic 0 period of the timing signal φ ₁ , that is, when the switches 10 and 11 are in the positions (OFF) shown in the figure, the analog voltage “α” is generated by the operational amplifier 12. The size is set according to the offset voltage of. Therefore,
When φ ₁ is at logic 1 (comparison operation period), V _IN2 can be corrected by “α”, and the offset voltage can be canceled (V _OS −α = 0). [Second Conventional Example] In FIG. 9, reference numeral 21 denotes a switch for switching between a first input voltage V _IN1 and a second input voltage V _IN2 ,
A switch 22 short-circuits the input and output terminals of the operational amplifier 23, and a capacitor 24 is connected between the switch 21 and the inverting input (-) of the operational amplifier 23. In addition, F /
F is a flip-flop that is set / reset according to the output logic of the operational amplifier 23.

In such a configuration, (1) when the switch 21 is set to V _IN1 and the switch 22 is short-circuited, the capacitor 24 accumulates the total of the first input voltage V _IN1 and the offset voltage ΣV _OS. .. Accumulated charge (VA
₍₁₎ ) is given by the following equation. VA ₍₁₎ =-(V _IN1 + ΣV _OS ), where the negative sign represents the inverting operation of the operational amplifier, and ΣV
_OS is the offset voltage V _{OS (OP)} of the operational amplifier 23 and the offset voltage V _{OS (SW) due} to the clock leakage of the switch 22.
Voltage (ΣV _OS = V _{OS (OP)} + V added with (detailed later _{)
OS (SW)} ).

Next, (2) when the switch 21 is set to V _IN2 and the switch 22 is opened, the capacitance 24
The electric charge stored in V _IN2 and V _IN
It changes according to the relationship of _IN1 . _{VA (2) = V IN2 -V} IN1 + VA (1) = V IN2 -V IN1 - (V IN1 + ΣV OS) = V IN2 -2 × V IN1 -ΣV OS ...... Here, due to the clock leakage switch 22 Assuming that the offset voltage V _{OS (SW)} is 0 V, that is, ΣV _OS = V _{OS (OP)} , the above equation becomes the following equation '.

VA ₍₂₎ = V _IN2 −2 × V _IN1 −V _{OS (OP)} ... 'VA ₍₂₎ is larger than the voltage (0 V here) of the non-inverting input terminal (+) of the operational amplifier 23. For example, operational amplifier 2
A logic 0 is output from 3. That is, from the comparison result of V _IN1 doubled and V _IN2 , the offset voltage (V
_{OS (OP)} ) is removed and VA ₍₂₎ is required.

[0008]

However, in the first conventional example, there is a problem that the circuit becomes large in scale because the adder circuit 13 is required, and the second conventional example. In the example, there is a problem that the offset voltage V _{OS (SW) due} to the clock leakage of the switch 22 cannot be compensated.

The offset voltage V _{OS (SW)} is a problem that occurs when a MOS (metal oxide semiconductor) transistor is used for the switch 22. A MOS transistor that operates as a switch element conducts (ON) between the source and drain when a voltage is applied to the gate, and opens (OFF) between the source and drain when the voltage is removed, but immediately after transitioning from ON to OFF. May cause a slight potential difference between the source and the drain, and an offset voltage V _{OS (SW)} corresponding to this potential difference is generated. This is mainly due to variations in diffusion concentration between the source region and the drain region. Therefore, an object of the present invention is to suppress the influence of the offset voltage of the operational amplifier and the offset voltage due to clock leakage without increasing the circuit scale.

[0010]

In order to achieve the above object, the invention according to claim 1 has a signal input terminal 30 and an input terminal 3 of an operational amplifier 31 as shown in the principle diagram of FIG.
2 and the signal input terminal 30
To a first input voltage V _IN1 , a second input voltage V _IN2 or a predetermined constant voltage (for example, 0 V), and an input / output terminal 32 of the operational amplifier 31.
A second switch 36 for short-circuiting between 35 and a third input for connecting a reference input terminal 37 of the operational amplifier 31 to either a predetermined constant voltage (for example, 0V) or a predetermined variable voltage α.
Switch 38 and the first switch 34 select a predetermined constant voltage, and a variable voltage α having a magnitude corresponding to the output logic of the operational amplifier 31 while the second switch 36 is short-circuited. And an auto-zero circuit 39 for generating.

In order to achieve the above-mentioned object, the invention according to claim 2 interposes between a predetermined constant voltage (for example, 0 V) and the input terminal 41 of the operational amplifier 40 as shown in the principle diagram of FIG. An amplifier circuit 45 interposed between the capacitor 42 and the signal input terminal 43 and the reference input terminal 44 of the operational amplifier 40.
A first switch 46 for connecting the signal input terminal 43 to either the first input voltage V _IN1 or the second input voltage V _IN2 , and a short circuit between the input / output terminals 41 and 47 of the operational amplifier 40. And two switches 48.

[0012]

According to the first aspect of the invention, the first switch 34
When a predetermined constant voltage is selected and the second switch 36 is short-circuited, the electric charge according to the offset voltage ΣV _OS is accumulated in the capacitor 33, and depending on the magnitude relation between this electric charge and the variable voltage α at that time, the operational amplifier 31 The output logic is determined. Then, the variable voltage α is adjusted so that the output logic of the operational amplifier 31 transits from 1 to 0 or from 0 to 1, that is, cancels ΣV _OS . Therefore, not only V _{OS (OP)} but also V _{OS (SW)} can be compensated to perform a highly accurate comparison operation, and the addition circuit can be eliminated to avoid an increase in circuit scale.

[0013] In a second aspect of the present invention, first, V _IN1 is amplified by a predetermined amplification degree is accumulated in the capacitor, then, V _IN2 which are amplified with the same amplification factor as the V _IN1 is with the V _IN1 Comparison To be done. Here, the above amplification degree acts only on V _IN1 and V _IN2 , and does not act on the offset voltage (V _{OS (OP)} + V _{OS (SW)} ). Therefore, the ratio of the offset voltage to V _IN1 and V _IN2 decreases in inverse proportion to the amplification degree, and
The influence of _{OS (OP)} and V _{OS (SW)} is suppressed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 are diagrams showing an embodiment of the comparator according to the invention described in claim 1. First, the configuration will be described. In FIG. 3, 50 is a capacitance interposed between the signal input terminal 51 and the input terminal 53 of the operational amplifier 52, 54 is a first switch, 55 is a second switch, and 56 is a third switch. The first switch 54 connects the signal input terminal 51 to either the first input voltage V _IN1 , the second input voltage V _IN2 or a predetermined constant voltage (for example, 0 V), and the second switch 55 is Input / output terminal 5 of the operational amplifier 52
Short circuit between 3 and 57, and then the third switch 56
Is for connecting the reference input terminal 58 of the operational amplifier 52 to either a predetermined constant voltage (for example, 0 V) or a predetermined variable voltage “α”.

Here, the first to third switches 5
4, 55 and 56 are four kinds of timing signals φ ₀ , φ ₁ , φ ₂ as shown in the timing chart of FIG.
And on / off operation in synchronization with φ ₃ as follows,
Alternatively, the switching operation is performed. Logic ₀ period of φ ₀ : second switch 55 → short circuit (on) Third switch 56 → select a predetermined constant voltage Logic 0 period of φ ₀ : second switch 55 → open (off) third switch 56 → Select variable voltage α Logic 1 period of φ ₁ ： First switch 54 → Select V _IN1 Logic 1 period of φ ₂ ： First switch 54 → Select V _IN2 Logic 1 period of φ ₃ ： First Switch 54 → selects a predetermined constant voltage On the other hand, 59 is an auto-zero circuit, and the auto-zero circuit 5
Reference numeral 9 indicates that the output logic of the operational amplifier 52 is taken in at a timing of φ ₃ while the first switch 54 selects a predetermined constant voltage and the second switch 55 is short-circuited, and the output logic depends on the output logic. The variable voltage “α” having a large magnitude is generated (see FIG. 8). The F / F is a flip-flop that is set / reset according to the output logic of the operational amplifier 52.

Next, the operation will be described. Here, V _IN1 is +0.1 V and V _IN2 is +0.2 for simplification of description.
V, the predetermined constant voltage is 0 V, and the operational amplifier 52
The offset voltage V _{OS (OP) is set} to + 0.4V, and the offset voltage V _{OS (SW)} caused by the clock leakage of the second switch 55 is set to + 0.01V. (A) φ ₀ , φ ₁ , φ ₂ and φ ₃ are logic 1,
In the period (a) where 1, 0, 0 are arranged,
V _IN1 + V _{OS (OP)} + V _{OS (SW)} , that is, 0.1 V + 0.
A charge corresponding to 4V + 0.01V = 0.51V is accumulated. (B) φ ₀ , φ ₁ , φ ₂ and φ ₃ are logic 0,
In the period (b) where 0, 1, and 0 are lined up, the accumulated charge of the capacitor 50 changes at V _IN2 −V _IN1 , and the operational amplifier 5 at this time
The output logic of No. 2 is determined by the comparison result of the voltage applied to the input terminal 53 (corresponding to the accumulated charge of the capacitor 50) and the voltage applied to the reference input terminal 58 (variable voltage α). (C) φ ₀ , φ ₁ , φ ₂ and φ ₃ are logic 1 and
When the first switch 54 selects a predetermined constant voltage (0 V) and the second switch 55 is short-circuited during the period (c) where 0, 0, 1 are lined up, the total value of the offset voltage ( ΣV _OS = V _{OS (OP)} + V _{OS (SW)} = 0.41V)
A charge corresponding to is accumulated. (D) φ ₀ , φ ₁ , φ ₂ and φ ₃ are logic 0,
In the period (d) where 0, 0, 1 are lined up, the capacitor 50 maintains the value (ΣV _OS ) in the above period (c), and the operational amplifier 5
2 outputs a logic corresponding to the comparison result of ΣV _OS and α. Assuming that ΣV _OS is larger than α, the operational amplifier 52 outputs a logic 0 and the auto-zero circuit 59
Causes α to be increased. As a result, α and ΣV
The difference in _OS gradually narrows down, and α is ΣV
_When it exceeds _OS , the output logic from the operational amplifier 52 is inverted (0 → 1) this time, and α is corrected to the decreasing side. That is, the value of the variable voltage α changes by Σ with the transition of the output logic state.
_Adjusted to match V _OS . Therefore, the subsequent comparison operation is performed using the offset voltage V _{OS (OP) of} the operational amplifier 52 and the reference voltage (variable voltage α) that compensates the offset voltage V _{OS (SW) due} to the clock leakage of the second switch 55. Therefore, it is possible to realize a comparator with high comparison accuracy. Moreover, since no adder circuit is required, it is possible to avoid an increase in circuit scale.

FIG. 5 and FIG. 6 are views showing an embodiment of the comparator according to the present invention. First, the configuration will be described. In FIG. 5, 60 is a capacitance (for example, 10 PF) interposed between a predetermined constant voltage (for example, 0 V) and the input terminal 62 of the operational amplifier 61, and 63 is between the signal input terminal 64 and the reference input terminal 65 of the operational amplifier 61. Variable amplifier circuit (corresponding to the amplifier circuit described in the gist of the invention) interposed between
_Reference numeral 6 designates the signal input terminal 64 with a number of input voltages V _{IN1 to
INn} (V _IN1 is the first input voltage, and V _IN2 is the second input voltage) is connected to a first switch group (first switch) 67 is an input / output terminal 62 of the operational amplifier 61,
It is a second switch that short-circuits between 68.

Here, the first switch group 66 includes SW ₁
...... consists of a number of switches to SW _n, SW ₁ is turned on / off in synchronization with the timing signal phi _1, ...... SW _n will be turned on / off in synchronization with the timing signal phi _n. Only _{one of} these switches SW ₁ ... SW _n is turned on. The variable amplifier circuit 63 is an operational amplifier 63.
a, an input resistance Rs (for example, 1 KΩ), and a plurality of series feedback resistances Rfa ... Rfc (for example, 4 KΩ, 3
KΩ, 2KΩ), a plurality of switches SA ... SD, and a feedback capacitance C (for example, 5PF). By selectively turning on / off the switches SA ... SD to change the value of the feedback resistance, The amplification degree of the operational amplifier 63a is made variable. The maximum amplification degree is obtained when the switch SD is turned on, and the minimum amplification degree is obtained when the switch SA is turned on. In addition, F / F is an operational amplifier 6
It is a flip-flop that is set / reset according to the output logic of 1.

Next, the operation will be described. FIG. 6 shows this embodiment.
It is a timing chart, φ₁~ Φ_nIs for each switch
ON / OFF timing signal, φ_FIs the F / F capture timing
Signal. φ₀In the logic 1 period of the second switch
The switch 67 turns on and the input / output 62 and 68 of the operational amplifier 61 are connected.
Is shorted. Now φ₀With φ₁In one logical period
When the variable amplifier circuit 63 has the first input voltage V_IN1
Is given, and the switch SA ... SD is selectively turned on.
Is amplified with a predetermined amplification degree (eg, A times) set by
It A x V_IN1Is the reference input terminal 65 of the operational amplifier 61.
Output from the operational amplifier 61 to the non-inverting (
Here, it is extracted with an amplification of 1). The output 68 is the second
It is connected to the capacitor 60 by the switch 67,
Transfer output, that is, A × V_IN1Charge corresponding to the capacitance 60
Accumulated. At this time, the offset voltage of the operational amplifier 61 is
Pressure V_{OS (OP)}The charge corresponding to is also accumulated in the capacitor 60,
In addition to φ ₀Immediately after the transition to logic 0, the second switch
Offset voltage V due to clock leakage of switch 67_{OS (SW)}To
Corresponding charges are also accumulated in the capacitor 60. Therefore,
The quantity 60 is A x V_IN1And ΣV_OSIs equivalent to
It can be stored.

Φ ₀ goes to logic 0 and φ ₂ replaces φ ₁
Changes to logic 1, the second input voltage V is fed to the reference input terminal 65 of the operational amplifier 61 via the variable amplification circuit 63.
_IN2 is given. This V _IN2 is given the same amplification degree (A times) as the above V _IN1 , and the operational amplifier 61 is A ×
V _IN2 is compared with the electric charge accumulated in the capacitor 60, and the magnitude relation is determined to determine the logic of the output 68.

Here, the amplification degree of the variable amplification circuit 63 is set to 10
2 times, the input offset voltage (V _{OS (63)} ) of the operational amplifier 63a of the variable amplification circuit 63 is 0.1V, the offset voltage (V _{OS (OP)} ) of the operational amplifier 61 is 0.4V, and the clock leakage of the second switch 67. Offset voltage (V _{OS (SW)} )
The 0.01 V, the first input voltage V _IN1 0.1V, V _{I N2}
Is assumed to be 0.2V.

The output V _OUT1 of the variable amplifier circuit 63 when V _{IN1 is} selected (SW ₁ is on) is given by the following equation. V _OUT1 = amplification × V _IN1 + V _{OS (63)} = 10 × 0.1V + 0.1V = 1.1V V _OUT1 applied to the reference input terminal 65 of the operational amplifier 61
Is given to the capacitor 60 from the output 68 of the operational amplifier 61 via the second switch 67 in the ON state, and the accumulated charge V _CN1 of the capacitor 60 at this time is expressed by the following equation.

V _CN1 = V _OUT1 + V _{OS (OP)} = 1.1V + 0.4V = 1.5V ... When the second switch 67 turns off, the second switch 67
Offset voltage V _{OS (SW) due} to clock leakage of
The accumulated charge V _CN1 'of the capacitor 60 at this time is given by the following equation.

V_CN1’= V_CN1+ V_{OS (SW)} = 1.5V + 0.01V = 1.51V The first switch with the second switch 67 kept off.
66 SW₂When is turned on, the variable amplification circuit 63 increases the power by 10 times.
V amplified to_IN2And V_{OS (63)}Of the operational amplifier 61
It is given to the reference input terminal 65. Variable amplification times at this time
Output V of path 63 _OUT2Is given by the following equation.

V _OUT2 = amplification × V _IN2 + V _{OS (63)} = 10 × 0.2 V + 0.1 V = 2.1 V ... The operational amplifier 61 compares the voltages of the input terminal 62 and the reference input terminal 65. The former is the charge accumulated in the capacitor 60,
That is, V _CN1 '(1.51V), and the latter is V
It is a voltage V _{CN2 obtained} by adding V _{OS (OP)} to _OUT2 .

V _CN2 = V _OUT2 + V _{OS (OP)} = 2.1V + 0.4V = 2.5V ... The operational amplifier 61 compares V _CN2 and V _CN1 ′, and determines the output logic according to the comparison result. .. That is, V _CN2 =
2.5V, 'because it is = 1.51 V, the difference _{(V CN2 -V CN1' V CN1} ) is + 0.99 V, and the logic 1 is output.

As described above, in this embodiment, since the variable amplifier circuit 63 amplifies V _IN1 and V _IN2 , the influence of V _{OS (OP)} and V _{OS (SW)} can be suppressed. .. This can be easily understood by considering the case where the amplification degree is set to one, that is, the case where this embodiment is not applied.
In this case, V _OUT1 = amplification × V _IN1 + V _{OS (63)} = 1 × 0.1 V + 0.1 V = 0.2 V ... 'V _CN1 = V _OUT1 + V _{OS (OP)} = 0.2 V + 0.4 V = 0. 6V ...... 'V _CN1 ' = V _CN1 + V _{OS (SW)} = 0.6V + 0.01V = 0.61V ...... 'V _OUT2 = Amplification × V _IN2 + V _{OS (63)} = 1 × 0.2V + 0.1V = 0.3V become a _{...... 'V CN2 = V OUT2 +} V OS (OP) = 0.3V + 0.4V = 0.7V ......', becomes a very small value as V _CN2 -V _CN1 'is + 0.09V, The ratio of V _{OS (OP)} to V _CN2 and V _{C N1} 'is (V _{OS (OP)} + V _{OS (SW)} ) / V _CN2 = (0.4V + 0.01V) /0.7V=0.59, respectively. → 59% (V _{OS (OP)} + V _{OS (SW)} ) / V _CN1 ′ = (0.4 V + 0.01 V) /0.61 V = 0.67 → 67%, which is considerably large.

By the way, when 10 times amplification is applied, (V _{OS (OP)} + V _{OS (SW)} ) / V _CN2 = (0.4V + 0.01V) /2.5V=0.16→ 16% (V _{OS (OP)} + V _{OS (SW)} ) / V _CN1 '= (0.4V + 0.01V) /1.51V=0.27 → 27%, 59% to 16% and 67% It is reduced to 27%, and the influence of the offset voltage can be suppressed accordingly.

Since the influence of the offset voltage becomes large when a small input voltage is handled, the amplification degree of the variable amplification circuit 63 may be automatically set according to the level of the input voltage.

[0030]

According to the present invention, it is possible to avoid an increase in circuit scale by eliminating the need for an adder circuit, and to suppress the influence of the offset voltage of the operational amplifier and the offset voltage due to clock leakage.

[Brief description of drawings]

FIG. 1 is a principle diagram of the invention according to claim 1;

FIG. 2 is a principle diagram of the invention according to claim 2;

FIG. 3 is a configuration diagram of an embodiment according to the invention described in claim 1.

FIG. 4 is a timing chart of an embodiment according to the invention described in claim 1.

FIG. 5 is a configuration diagram of an embodiment according to the invention described in claim 2.

FIG. 6 is a timing chart of an embodiment according to the invention described in claim 2.

FIG. 7 is a configuration diagram and a timing chart of a first conventional example.

FIG. 8 is a symbol diagram and a timing chart of the auto-zero circuit.

9A and 9B are a configuration diagram and a timing chart of a second conventional example.

[Explanation of symbols]

V _IN1 : first input voltage V _IN2 : second input voltage α: variable voltage 30: signal input terminal 31: operational amplifier 32: input terminal 33: capacitance 34: first switch 35: output terminal 36: second Switch 37: Reference input terminal 38: Third switch 39: Auto zero circuit 40: Operational amplifier 41: Input terminal 42: Capacitance 43: Signal input terminal 44: Reference input terminal 45: Amplification circuit 46: First switch 47: Output terminal 48: Second switch

Claims (2)

[Claims] 1. A signal input terminal (30) and an operational amplifier (3
Capacitance (33) interposed between the input terminal (32) of 1)
When the signal input terminal (30) first input voltage (V _IN1), a first switch for connecting to one of the second input voltage (V _{I N2)} or a predetermined constant voltage (e.g., 0V) ( 34), a second switch (36) for short-circuiting the input / output terminals (32, 35) of the operational amplifier (31), and a reference input terminal (37) of the operational amplifier (31) to a predetermined constant voltage (for example, 0V) or a predetermined variable voltage (α) connected to a third switch (38) and the first switch (34) selects a predetermined constant voltage,
And an auto-zero circuit (39) for generating a variable voltage (α) having a magnitude corresponding to the output logic of the operational amplifier (31) while the second switch (36) is short-circuited,
Comparator characterized by having. 2. A capacitance (4) interposed between a predetermined constant voltage (for example, 0V) and an input terminal (41) of an operational amplifier (40).
2), an amplifier circuit (45) interposed between the signal input terminal (43) and the reference input terminal (44) of the operational amplifier (40), and the signal input terminal (43) at the first input voltage (V _IN1 )
_{Alternatively,} a first switch (46) connected to either of the second input voltage (V _IN2 ) and a second switch (48) for short-circuiting between the input / output terminals (41, 47) of the operational amplifier (40). Comparator characterized by including.