JPS5851612A - Comparison circuit - Google Patents
Comparison circuitInfo
- Publication number
- JPS5851612A JPS5851612A JP15039081A JP15039081A JPS5851612A JP S5851612 A JPS5851612 A JP S5851612A JP 15039081 A JP15039081 A JP 15039081A JP 15039081 A JP15039081 A JP 15039081A JP S5851612 A JPS5851612 A JP S5851612A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input terminal
- input
- differential amplifier
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0038—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は入力信号間のレベル差が小さい状態でも正確な
比較結果を出力することができるモノリシック比較回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic comparison circuit that can output accurate comparison results even when the level difference between input signals is small.
一般に％モノリシ、クリアナログーディジタル変換器（
以下Ａ／Ｄ変換器という）において、比較回路は重要な
回路要素であ、ｊ９、Ａ／Ｄ変換器の高精度化、高分解
能化にともなりて、入力信号間のレベル差の小さい場合
に％正確な出力が得られるよシ高精度表比較回路を必要
とするようになった。Generally % monolithic, clear analog to digital converter (
The comparison circuit is an important circuit element in the A/D converter (hereinafter referred to as an A/D converter). A highly accurate table comparison circuit is now required to obtain % accurate output.
従来、Ｍ０８構造のモノリシ、りＡ／Ｄ変換器の比較回
路として第１図の回路図に示すものが知られている。こ
の比較回路の特徴は、スイッチ１を閉じて第１のアナロ
グ入力電圧■ムｌ をサンプリングし、その比較動作期
間中そのアナログ入力電圧を保持するサンプル・ホール
ド機能を備えていることである。この比較回路の欠点は
、スイッチ３の０Ｎ−ＯＦＦ時に寄生容量６の充・放電
によ抄容量４の保持電荷の漏れがあることである。Conventionally, the circuit diagram shown in FIG. 1 is known as a comparison circuit for a monolithic A/D converter having an M08 structure. A feature of this comparison circuit is that it has a sample-and-hold function that closes switch 1 to sample the first analog input voltage, and holds that analog input voltage during the comparison operation. A drawback of this comparison circuit is that when the switch 3 is ON-OFF, the charge held in the capacitor 4 leaks due to charging and discharging of the parasitic capacitor 6.
この欠点を補うべく補償用素子を付加しても、高精度、
高分解のＡ／Ｄ変換器を構成できるまでになりていない
。さらに、この比較回路をＣ−ＭＯ８構造で構成した場
合、その電源電圧の変動に対して論理素子のインバータ
で構成された増幅器５の入カスレＶＷルド電圧の変動が
大きいため、比較動作中の電源電圧の変動に対して所要
精度を保持することが困難であった。Even if a compensation element is added to compensate for this drawback, high accuracy and
It is not yet possible to construct a high-resolution A/D converter. Furthermore, when this comparator circuit is configured with a C-MO8 structure, the input voltage level VW of the amplifier 5, which is composed of an inverter as a logic element, fluctuates greatly with respect to fluctuations in the power supply voltage. It was difficult to maintain the required accuracy against voltage fluctuations.
この電源電圧変動特性を改善した比較回路として、”
８ｏ１ ｉｄ −８ｆａｔｅ Ｃ１ｒｃ１．１ｉｔｓ
ＣｏｎｆｅｒｅｎｃｅＤ ｉｇ、 Ｔｅｃｈ、 Ｐａｐ
ｅｒｓ ” 、 Ｆｅｂ、 ｌ ９７３の１５２頁に発
表されたものは、第２図の回路図に示される。図におい
て、まずスイッチ１４．１５を閉じて、差動型増幅器１
１．１２の入力端を接地する。As a comparison circuit with improved power supply voltage fluctuation characteristics,
8o1 id -8fate C1rc1.1its
ConferenceDig, Tech, Pap
ers”, Feb. 1973, page 152, is shown in the circuit diagram of FIG.
1. Ground the input terminal of 12.
これＫよシ差動型増幅器１１の入力オフセット電圧ｅ、
を電圧利得０３倍した電圧に等しい電荷が容量１６に保
持される。次に、スイッチ１４ 、１５を開いて、スイ
ッチ１３を閉じて第１のアナログ入力信号Ｖ、□ と第
２のアナログ信号ＶＡ２ を比較する。これによって増
幅器１２の入力端においては、増幅器１１０入カオフセ
ツト電圧が補償される。またこの比較回路の入力オフセ
ット電圧ＶＯＦＦは次式で表わすことができる。If this is K, the input offset voltage e of the differential amplifier 11,
A charge equal to the voltage obtained by multiplying the voltage by a voltage gain of 03 is held in the capacitor 16. Next, the switches 14 and 15 are opened and the switch 13 is closed to compare the first analog input signal V, □ and the second analog signal VA2. At the input of the amplifier 12, the offset voltage at the input of the amplifier 110 is thereby compensated for. Further, the input offset voltage VOFF of this comparison circuit can be expressed by the following equation.
ＶＯＦＦ ＝ ６．／Ｇ ＊ ”’
・・・（１）ここでＣ２は増幅器１２の入力オフセット
電圧である。（１）式よシ明らかなように、この比較回
路の入力オフセット電圧は増幅器１１の電圧利得を大き
くする＃１ど低減される。しかし、増幅器１１の電圧利
得は入力オフセット電圧ｅ、によって、この増幅器１１
が飽和しない程度の値に抑える必要がある。また、この
比較回路は差動型増幅器によって構成されているため、
同相信号除去比（ＣＭＲＲ）が優れておシ、電源変動除
去比（８ＶＲＲ）も十分に大きいため、電源電圧の変動
に対しても安定であるが、その入力回路部にサンプル・
ホールド回路を備えていないため、逐次比較型のＡ／Ｄ
変換器を構成する場合、そのアナログ入力端にサンプル
・ホールド回路を独立に必要とする問題がある。VOFF=6. /G*”'
(1) Here, C2 is the input offset voltage of the amplifier 12. As is clear from equation (1), the input offset voltage of this comparator circuit is reduced by #1, which increases the voltage gain of the amplifier 11. However, the voltage gain of the amplifier 11 depends on the input offset voltage e,
It is necessary to suppress the value to a value that does not saturate. Also, since this comparison circuit is composed of a differential amplifier,
The common mode rejection ratio (CMRR) is excellent, and the power supply fluctuation rejection ratio (8VRR) is also sufficiently large, so it is stable against fluctuations in the power supply voltage.
Since it does not have a hold circuit, it is a successive approximation type A/D.
When constructing a converter, there is a problem in that an independent sample and hold circuit is required at the analog input end of the converter.
本発明の目的は、これらの欠点を除去し、電源電圧の変
動に対して、優れた安定性（電源電圧除去比）を備え、
入力オフセット電圧の補償が可能で、かつ被比較信号の
サンプル・ホールド力可能てＭＯ８モノリシ、りＡ／Ｄ
変換器及びデータ収集用Ｌ８Ｉを構成できるようにした
比較回路を提供するととＫある。The purpose of the present invention is to eliminate these drawbacks, provide excellent stability (power supply voltage rejection ratio) against fluctuations in power supply voltage, and
MO8 monolithic A/D that can compensate for input offset voltage and has sample and hold power for the compared signal.
It is proposed to provide a comparator circuit that can configure a converter and a data acquisition L8I.
本発明は、入力信号とこの入力と比較する比較信号とを
切替えて第１の容量素子に接続する第１のスイッチ手段
と、前記第１の容量素子からの信号を反転入力端子に接
続し、その第１の容量素子と実質的に同一の第２の容量
素子を非反転入力端子と共通線との縄に接続しかつこれ
ら反転入力端子と非反転入力端子との電位差を増幅して
反転出力および非反転出力をとシ出す第１の差動増幅器
と、この第１の差動増幅器の各入力端子と前記共通線と
の各接続を切替える第２のスイッチ手段と。The present invention provides a first switch means for switching between an input signal and a comparison signal to be compared with the input and connecting it to a first capacitive element, and a signal from the first capacitive element being connected to an inverting input terminal; A second capacitive element that is substantially the same as the first capacitive element is connected to a rope between the non-inverting input terminal and the common line, and the potential difference between the inverting input terminal and the non-inverting input terminal is amplified and output is inverted. and a first differential amplifier that outputs a non-inverted output, and a second switch means that switches connections between each input terminal of the first differential amplifier and the common line.
前記第１の差動増幅器の反転出方および非反転出力を実
質的に同一の容量をもつ第３および第４の容量素子を介
して反転入力端子および非反転入力端子にそれぞれ接続
しこれら各入力端子の間の電位差を増幅する第２の差動
増幅器と、この第２の差動増幅器の反転入力端子および
非反転入力端子と前記共通線との各接続を切替える第３
のスイッチ手段とを含み、前記第１．第２および第３の
スイッチ手段のオン動作の稜に各スイッチ手段のオフ動
作のタイミングをずらせた仁とを特徴とする比較回路に
ある。The inverting output and the non-inverting output of the first differential amplifier are respectively connected to the inverting input terminal and the non-inverting input terminal via third and fourth capacitors having substantially the same capacitance. a second differential amplifier that amplifies the potential difference between the terminals; and a third differential amplifier that switches connections between the inverting input terminal and the non-inverting input terminal of the second differential amplifier and the common line.
switch means of the first. The comparison circuit is characterized in that the timing of the off operation of each switch means is shifted from the edge of the on operation of the second and third switch means.
以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
第３図°は本発明の実施例の回路図、第４図はそのタイ
ミングチャートを示す。まず、時刻ｔ６にスイッチ１，
１４．２０を閉じ、スイッチ２を開く。いま、差動型増
幅回路１１の入力オフセット電圧をｅｍとすると、容量
２２には−２ｅ 鵞・Ｇ１・ｃ、ｏ電荷、容量２３には
−ｚ ｅ １ ” Ｇ Ｂ ” Ｃ＠の電荷がそれぞれ
保持され、第１のアナログ入力電圧をＶｌｌ とすると
、容量４にはＶｌｌ”ｃｔの電荷が保持される０次に、
時刻ｔ、に（第４図φ１）スイッチ２０を開き、時刻１
．（第４図φ、）スイッチ１４を開き、そして最後に（
第４図φ、）スイッチ１を開くと同時にスイッチ２を閉
じる。FIG. 3 shows a circuit diagram of an embodiment of the present invention, and FIG. 4 shows its timing chart. First, at time t6, switch 1,
14. Close 20 and open switch 2. Now, if the input offset voltage of the differential amplifier circuit 11 is em, the capacitor 22 has a charge of -2e G1c, and the capacitor 23 has a charge of -z e 1 "GB" C@. When the first analog input voltage is Vll, the capacitor 4 holds a charge of Vll"ct.
At time t, (FIG. 4 φ1) the switch 20 is opened, and the switch 20 is opened at time 1.
．． (Fig. 4 φ,) Open the switch 14, and finally (
Fig. 4 φ,) Switch 1 is opened and switch 2 is closed at the same time.
このように各スイッチのＯＦＦの時刻をずらすととＫよ
シ、それぞれの容量に保持された電荷の漏れを防ぐこと
ができ、その結果第２のアナログ入力電圧を■Ａ２ と
すれば１節点２４の電位は（■ム２−Ｖム菫）となる。By shifting the OFF time of each switch in this way, it is possible to prevent leakage of the charge held in each capacitor, and as a result, if the second analog input voltage is A2, one node 24 The potential of is (■mu2-Vmuviolet).
したがって、差動型増幅器１１０２つの出力端の電位差
は。Therefore, the potential difference between the two output terminals of the differential amplifier 110 is:
Ｇ、−（Ｖ、、 −Ｖ Ａ１ ＋ｅ、）となシ、前述
の通シ、容４１２２．２３にはあらかじめ
（” ｅｇｏｓ−（１ｅｔＧｔ） ）＝ｅｔＧ＊２
の差電圧に相当する電荷が保持されているので節点２５
，２６の電位差はＧｔ （Ｖ、ｕ−Ｖａｔ ） ）−ｆ
する。このように差動型増幅器１２０入力端においては
、差動型増幅器１１０入カオフセツト電圧ｅ１は補償さ
れていることになる。いま、差動型増幅器１２０入カオ
フセツト電圧なｅ、とし、この増幅器１２の電圧利得を
Ｇ、とすればその出力電圧７１社
Ｖａ＝Ｇｔ” （Ｇｌ（ＶＡ２−Ｖｌｌ ）＋ｅｔ）”
Ｇｔ ”Ｇｔ ・（（ＶＡ２ ＶＡＩ ）＋ｅｔ／Ｇ
ｔ １・・・・・・（２）
となって、その比較回路の入力オフセット電圧はｅ ＊
／Ｇｔ となることがわかる。したがって、差動型増
幅器の出力が飽和しない範囲内において、Ｇ。G, -(V,, -V A1 +e,), the above-mentioned circuit, capacitor 4122.23 holds a charge equivalent to the voltage difference of ("egos-(1etGt))=etG*2 in advance. Since it is, node 25
, 26 is Gt (V, u-Vat))-f
do. In this way, at the input end of the differential amplifier 120, the input offset voltage e1 of the differential amplifier 110 is compensated. Now, if the input offset voltage of the differential amplifier 120 is e, and the voltage gain of this amplifier 12 is G, then its output voltage Va=Gt"(Gl(VA2-Vll)+et)"
Gt ”Gt ・((VA2 VAI )+et/G
t1...(2), and the input offset voltage of the comparator circuit is e*
/Gt. Therefore, within the range in which the output of the differential amplifier does not saturate, G.
を大きくとる仁とによってその入力オフセット電圧を最
小に抑えることができ、入力オフセット電圧補償動作及
びアナログ入力電圧のサンプリング動作は達成されてい
る。このようにスイッチ１が閉じてい°る期間アナログ
入力電圧のサンプリングを行い、以後の比較動作期間中
そのアナログ入力電圧は保持されている。The input offset voltage can be suppressed to a minimum by increasing the value, and the input offset voltage compensation operation and analog input voltage sampling operation are achieved. In this way, the analog input voltage is sampled while the switch 1 is closed, and the analog input voltage is held during the subsequent comparison operation period.
この比較回路において、差動入力端が一定の同相電圧で
バイアスされているため、同相入力特性を劣化するとと
々く、第２図の回路と同等の優れた同相特性を備えてい
る。In this comparator circuit, since the differential input terminal is biased with a constant common-mode voltage, the circuit has excellent common-mode characteristics equivalent to that of the circuit shown in FIG. 2, without degrading the common-mode input characteristics.
さらに、第３図において、スイッチ１４の開閉時に寄生
容量を介して容量４の保持電荷に微少な変動を与えるが
、容量４と同等の容量２１を付加することによってこの
保持電荷の微少変動が差動入力に対して同相に起きるの
でステ、プエラーを差動入力間で各々補償でき、さらに
リーク電流による保持電荷の変動も差動入力間で補償さ
れる。Furthermore, in FIG. 3, when the switch 14 is opened and closed, a slight fluctuation is caused in the charge held in the capacitor 4 through the parasitic capacitance. Since this occurs in the same phase as the dynamic input, step and pull errors can be compensated for between the differential inputs, and fluctuations in held charge due to leakage current can also be compensated for between the differential inputs.
したがって、この比較回路のサンプル・ホールドのため
の容量４をモノリシック集積ができるほど小さな容量値
にできＬＢＩ化に好適であシ、また電源電圧変動特性の
優れた回路となる。Therefore, the capacitance 4 for sample and hold of this comparator circuit can be made small enough to be monolithically integrated, making it suitable for LBI and providing a circuit with excellent power supply voltage fluctuation characteristics.
第５図は第３図の実施例を０ＭＯ８構造に適用した場合
の回路図を示す。図において、差動型増幅器１１はＰチ
ャンネルトランジスタ３５．３６及びＮチャンネルトラ
ンジスタ３７．３８で構成され、差動型増幅回路１２は
Ｐチャンネルトランジスタ３９，４０及びＮチャンネル
トランジスタ４１．４２．４３で構成される。またこれ
らの増幅回路に定電流を供給するバイアス回路はＰチャ
ンネルトランジスタ３０．３１．３３，３４，４４およ
びＮチャンネルトランジスタ３２で構成され。FIG. 5 shows a circuit diagram when the embodiment of FIG. 3 is applied to an 0MO8 structure. In the figure, the differential amplifier 11 is composed of P channel transistors 35, 36 and N channel transistors 37, 38, and the differential amplifier circuit 12 is composed of P channel transistors 39, 40 and N channel transistors 41, 42, 43. be done. A bias circuit for supplying constant current to these amplifier circuits is composed of P-channel transistors 30, 31, 33, 34, and 44 and an N-channel transistor 32.
スイッチ１，２，１４．２０はそれぞれトランジスタに
よシ構成されている。The switches 1, 2, 14, and 20 are each constructed from a transistor.
第６図は本発明による比較回路を逐次比較型Ａ／Ｄ変換
器に適用した場合の構成図を示す。図中５０が本発明に
よる比較回路、５１が逐次比較レジスタ、５２がＤ／Ａ
変換器である。この逐次比較型Ａ／Ｄ変換器の動作説明
は良く知られているので省略する。本発明の比較回路を
使用する事によシ、高精度、高分解能で安定なサンプル
・ホールド機能を有する逐次比較型Ａ／Ｄ変換器をＭＯ
Ｓモノリック化することが可能となる。FIG. 6 shows a configuration diagram when the comparison circuit according to the present invention is applied to a successive approximation type A/D converter. In the figure, 50 is a comparison circuit according to the present invention, 51 is a successive approximation register, and 52 is a D/A
It is a converter. A description of the operation of this successive approximation type A/D converter will be omitted since it is well known. By using the comparator circuit of the present invention, a successive approximation type A/D converter with high precision, high resolution, and stable sample and hold functions can be realized.
It becomes possible to make it S monolithic.
以上本発明によれば、入力オフセット電圧の補償手段と
、サンプル・ホールド機能とを備え、電源電圧の変動特
性に優れ、さらに入力端部のスイ、チの開閉によるステ
、プエラーの補償により、小さなホールド容量でも高精
度な比較動作が可能なモノリシック化に好適な比較回路
を得ることができる。As described above, according to the present invention, it is equipped with an input offset voltage compensation means and a sample/hold function, and has excellent power supply voltage fluctuation characteristics. It is possible to obtain a comparison circuit suitable for monolithic implementation that can perform highly accurate comparison operations even with a hold capacitor.
第１図は従来の比較回路の回路図、第２図は従来の他の
比較回路の回路図、第３図は零発＾施例の回路図、第４
図は第３図のタイミングチャート、第５図は第３図の実
施例の詳細回路図、第６図は本発明を適用した逐次比較
型Ａ／Ｄ変換器の構成図である。
図において％１ ＊ ２ ＊ ３−１３ ＊ １４ ｅ
１５ ＊２０・・・・・・スイッチ、４．１６．２１
．２２．２３・・・・−・容量（コンデンサ）、６・・
・・・・寄生容量、５・・・・・・増幅器％１１．１２
−・・・・・差動増幅器、２４，２５゜２６・・・・・
・節点、３０，３１．３３〜３６．３９ 。
４０．４４−・・・・・Ｐチャンネルトランジスタ％３
２゜３７．３８．４１〜４３・・・・−Ｎチャンネルト
ランジスタ、５ｏ・・・・−比較回路、５１・・・・・
・逐次比較レジスタ、５２・−・・・・Ｄ／Ａ変換器、
である。Fig. 1 is a circuit diagram of a conventional comparison circuit, Fig. 2 is a circuit diagram of another conventional comparison circuit, Fig. 3 is a circuit diagram of a zero-starting example, and Fig. 4 is a circuit diagram of a conventional comparison circuit.
3 is a timing chart of FIG. 3, FIG. 5 is a detailed circuit diagram of the embodiment of FIG. 3, and FIG. 6 is a configuration diagram of a successive approximation type A/D converter to which the present invention is applied. In the figure %1 * 2 * 3-13 * 14 e
15 *20...Switch, 4.16.21
．． 22.23...- Capacity (capacitor), 6...
... Parasitic capacitance, 5 ... Amplifier %11.12
-... Differential amplifier, 24, 25° 26...
・Node, 30, 31.33-36.39. 40.44-...P-channel transistor%3
2゜37.38.41-43...-N channel transistor, 5o...-comparison circuit, 51...
・Successive approximation register, 52...D/A converter,
It is.
Claims (1)
１の容量素子に接続する第１ｑ）スイッチ手段と、前記
第１の容量素子からの信号を反転入力端子に！！続し、
その第１の容量素子と実質的に同一の第２の容量素子を
非反転入力端子と共通線との間に接続しかつこれら反転
入力端子と非反転入力端子との電位差を増幅して反転出
力および非反転出力をとシ出す第１の差動増幅器と、こ
の第１の差動増幅器の各入力端子と前記共通線との各接
続を切替える第２のスイッチ手段と、前記第１の差動増
幅器の反転出力および非反転出力を実質的に同一の容量
をもつ第３および第４の容量素子を介して反転入力端子
および非反転入力端子にそれぞれ接続しこれら各入力端
子の間の電位差を増幅する第２０差動増幅器と、この第
２の差動増幅器の反転入力端子および非反転入力端子と
前記共通線との各接続を切替える第３のスイッチ手段と
を含み、前記第１．第２および第３のスイッチ手段のオ
ン動作の後に各スイッチ手段のオフ動作のタイミングを
ずらせたことを特徴とする比較回路。A 1q) switch means for switching between an input signal and a comparison signal to be compared with this input and connecting it to a first capacitive element, and a signal from the first capacitive element to an inverting input terminal! ! Continuing,
A second capacitive element that is substantially the same as the first capacitive element is connected between the non-inverting input terminal and the common line, and the potential difference between the inverting input terminal and the non-inverting input terminal is amplified and output is inverted. and a first differential amplifier that outputs a non-inverted output; a second switch means that switches each connection between each input terminal of the first differential amplifier and the common line; The inverting output and the non-inverting output of the amplifier are respectively connected to the inverting input terminal and the non-inverting input terminal via third and fourth capacitive elements having substantially the same capacitance, and the potential difference between these input terminals is amplified. a 20th differential amplifier; a third switch means for switching each connection between an inverting input terminal and a non-inverting input terminal of the second differential amplifier and the common line; A comparison circuit characterized in that the timing of the off operation of each switch means is shifted after the on operation of the second and third switch means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15039081A JPS5851612A (en) | 1981-09-22 | 1981-09-22 | Comparison circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15039081A JPS5851612A (en) | 1981-09-22 | 1981-09-22 | Comparison circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5851612A true JPS5851612A (en) | 1983-03-26 |
| JPS6365172B2 JPS6365172B2 (en) | 1988-12-14 |
Family
ID=15495939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15039081A Granted JPS5851612A (en) | 1981-09-22 | 1981-09-22 | Comparison circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851612A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60135839A (en) * | 1983-12-26 | 1985-07-19 | Natl House Ind Co Ltd | Panel support apparatus for shear tester |
| JPS62126709A (en) * | 1985-11-27 | 1987-06-09 | Hitachi Ltd | Comparator |
| JPS6335018A (en) * | 1986-07-30 | 1988-02-15 | Nec Corp | Analog digital converter |
| JPS63240218A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Sequential comparison type a/d converter |
| JPS6413818A (en) * | 1987-07-08 | 1989-01-18 | Toshiba Corp | Consecutive comparison type ad converter |
| JPH0766728A (en) * | 1993-08-23 | 1995-03-10 | Nec Corp | Analog/digital converter |
| EP1018806A2 (en) * | 1999-01-08 | 2000-07-12 | Nec Corporation | A/D converter with a power saving circuit and its control method |
| GB2402008A (en) * | 2003-04-30 | 2004-11-24 | Synad Technologies Ltd | Method and apparatus for dc offset control |
| US8519874B2 (en) | 2010-09-29 | 2013-08-27 | Fujitsu Limited | Successive approximation A/D converter |
-
1981
- 1981-09-22 JP JP15039081A patent/JPS5851612A/en active Granted
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60135839A (en) * | 1983-12-26 | 1985-07-19 | Natl House Ind Co Ltd | Panel support apparatus for shear tester |
| JPS62126709A (en) * | 1985-11-27 | 1987-06-09 | Hitachi Ltd | Comparator |
| JPS6335018A (en) * | 1986-07-30 | 1988-02-15 | Nec Corp | Analog digital converter |
| JPS63240218A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Sequential comparison type a/d converter |
| JPS6413818A (en) * | 1987-07-08 | 1989-01-18 | Toshiba Corp | Consecutive comparison type ad converter |
| JPH0766728A (en) * | 1993-08-23 | 1995-03-10 | Nec Corp | Analog/digital converter |
| EP1018806A2 (en) * | 1999-01-08 | 2000-07-12 | Nec Corporation | A/D converter with a power saving circuit and its control method |
| EP1018806A3 (en) * | 1999-01-08 | 2003-03-05 | Nec Corporation | A/D converter with a power saving circuit and its control method |
| GB2402008A (en) * | 2003-04-30 | 2004-11-24 | Synad Technologies Ltd | Method and apparatus for dc offset control |
| GB2402008B (en) * | 2003-04-30 | 2006-09-06 | Synad Technologies Ltd | Method and apparatus for DC offset control |
| US7295820B2 (en) | 2003-04-30 | 2007-11-13 | Synad Technologies Limited | Method and apparatus for DC offset control |
| US8519874B2 (en) | 2010-09-29 | 2013-08-27 | Fujitsu Limited | Successive approximation A/D converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6365172B2 (en) | 1988-12-14 |
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