JPS63240218A - Sequential comparison type a/d converter - Google Patents

Abstract

PURPOSE:To attain accurate conversion corresponding to the range of change in an analog input voltage by allowing a comparator used in the comparison operation to generate plural bias voltages in a sequential comparison type A/D converter. CONSTITUTION:When the range of change in an analog input voltage being the object of comparison is within a 1st prescribed range, a bias voltage generating source generates the bias voltage corresponding to the 1st prescribed range and when the range of change in a 2nd prescribed range, the bias voltage generating source generates the bias voltage corresponding to the 2nd prescribed range and the comparator applies comparison based on the optimum bias voltage. That is, a voltage (1/2(V REF)) divided by resistors 8, 9 is fed respectively to gates of N-channel transistors (TRs) 1, 3 via switches 6, 7 in the bias voltage generating source 15 when the control signal 12 is at a high level, and in bringing the control signal 12 to a low level, the N-channel TR ID is turned off and a voltage (V REF) of the reference voltage source is applied to the TRs 1, 3 as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a successive approximation type A/D converter, and particularly to a comparator of a successive approximation type A/D converter.

[Prior Art] First, a successive approximation type A/D converter will be described with reference to FIG. In the figure, 41 is a D/A converter (hereinafter referred to as D
42 is a comparator, 43 is a successive approximation register, 44 is a reference clock generator, 45 is a reference power supply terminal,
46 indicates analog input signal terminals, respectively.

In the above successive approximation type A/D converter, the analog input voltage V
To convert AN into a digital signal, the most significant bit of the successive approximation register 43, which has a multi-bit structure, is input one bit at a time starting from the MSB so that the output voltage V DAC of the DAC 41 and the analog input voltage VAN match. L.S.
A digital signal is generated by comparing up to B. More specifically, in FIG. 5, FSR is the maximum value of the analog input signal that can be converted, and this is the maximum value of the analog input signal that can be converted.
It has the same value as the reference voltage V REF appearing at 5. Period T
s.

TNSTN, -1, . . . , To are switched by the clock of the clock generator 44 shown in FIG. In the first period TS, the input level of the analog input signal VAN appearing at the analog input signal terminal 46 is sampled, and in the period TN, the MSB of the successive approximation register 43 is set to "0" and the other bits are set to "1", The digital output of this successive approximation register 43, that is, the value of each bit, is sequentially converted to bN from the MSB side.
, bN-1, . 2
(VREF), set the MSB to “1” and VAN<1
/2 (VREF), set the MSB to "0".

In the example of FIG. 5, the MSB is set to "1".

Next, in the period T N-1, the successive approximation register 43 (N-
1) Set "1" to the bit, compare the corresponding digital output with VAN, and if VAN>VDAC, (
N-1) bit is set to “1”, and if VAN<VDAC, then (
Set the N-1)th bit to "0".

In the example of Figure 5, VDAC=Σ(1/2')bi·V REFl2l = (1/2+1/4) Comparing VREF and VAN, since VAN<3/4 (VREF) , (
The N-1)th bit is set to "0".

Hereafter, by repeating the same operation until the period TI,
All bits of the successive approximation register 43 are determined, and the analog human input signal VAN is digitized.

The conventional detailed configuration of the comparator 42 of the A/D converter will be explained. FIG. 6 is a circuit diagram showing the configuration of the comparator 42.

In the figure, an N-type MOS field effect transistor (hereinafter referred to as N
(hereinafter referred to as a channel transistor) 61 and a P-type MOS field effect transistor (hereinafter referred to as a P-channel transistor) 62 constitute a first inverter, and an N-channel transistor 63 and a P-channel transistor 6 constitute a first inverter.
4 constitute a second inverter. N-channel transistor 65 functions as a constant current source. N-channel transistor 61 and 63 have the same current characteristics, and P-channel transistor 62 and 64 have the same current characteristics. Furthermore, the gates of P-channel transistors 62 and 64 are commonly connected to node 79, so that
It constitutes a so-called current mirror type CMO9 differential amplifier.

Next, the operation will be explained. First, switch 66.67.68
．． 69 is turned off and the capacitor 70 is fully discharged, switches 66 and 67 are first turned on during the period Ts shown in FIG. After biasing the voltage to
N to a capacitor 70. Note that the reason for biasing the voltage to the gates of the N-channel transistors 61 and 63 is to make these transistors function in the saturation region and use the comparator at its normal operating point. In addition, as will be described later, the normal bias voltage is reduced to 1/2 (VRE
F). This bias voltage is generated by placing two resistors 72.73 having the same resistance value in series between the midpoint potential within the DAC or the reference potential VREF and the ground potential. Use divided voltage.

Next, during period TN in FIG. 2, switches 66, 67, and 69 are opened, and then switch 68 is closed to reduce the potential at node 78 to V.
DAC. Since the potential difference across the capacitor 700 at this time is 1/2 (VREF) - VAN, the potential at the node 77, that is, the gate potential of the N-channel transistor 61 is 1/2 (VREF)
) -VAN+VDAC.

As is clear from FIG. 5, l VDAC-VAN l! l; 1/2 (VR
EF), and the potential of node 77 is always within the range of ground potential and power supply potential VDD. This is the reason why a bias voltage of 1.2 (VREF) is supplied to the gates of N-channel transistors 61 and 63. In addition, since the other input terminal of the comparator, that is, the gate voltage of the N-channel transistor 63, is held at a value of 1/2 (VREF) by the capacitor 71, the magnitude of VAN and V DAC is ultimately compared. Therefore, when VDAC>VAN, the mutual conductance gm of the N-channel transistor 61 becomes larger than the mutual conductance of the N-channel transistor RO 3, and the output signal 74 of the comparator becomes high level. However, on the contrary, VDAC<VAN
When , the mutual conductance gm of the N-channel transistor 61 is smaller than the mutual conductance gm of the N-channel transistor 63, so the output signal 7
4 will be low level. The above operation is repeated N times and N
Get the digital value of the bit.

[Problems to be Solved by the Invention] Generally, in electronic circuits integrated on a semiconductor substrate, it is necessary to make effective use of terminals. In this case, from the viewpoint of effective use of the terminals, only one bias voltage source using the reference voltage source of the D/A converter can be provided.

However, in order to accurately convert a low-voltage analog input signal into a digital signal, it is necessary to lower the reference voltage, but lowering the reference voltage also lowers the bias voltage applied to the comparator. There is a problem in that the comparator cannot be operated at the best operating point, and the accuracy deteriorates on the contrary.

For example, if the analog input voltage VAN changes around 1 volt without much fluctuation, and V REF is used as 2 volts in order to convert this analog voltage with high accuracy, the N-channel transistor 61 in FIG.
The gate of 1/2 (VREF) -VAN+VDAC: 1
A voltage of (V) -VAN+VDAC is applied to the gate of the N-channel transistor 63, and a voltage of 1/2 (VREF) = 1 volt is applied to the gate of the N-channel transistor 63. However, if the gate voltage supplied to each N-channel transistor is too low, the comparator will not have the best operating point and accurate conversion cannot be expected.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an A/D converter that can perform accurate conversion in response to a range of changes in analog input voltage.

[Means for Solving the Problems] The present invention provides a successive approximation type A/D converter that converts a digital value supplied from a successive approximation register into an analog voltage, and compares the analog voltage with an input analog voltage using a comparator. The comparator is characterized in that the bias voltage generation source used in the comparison operation can generate a plurality of bias voltages.

[Operations and Effects] In the A/D converter according to the above configuration, when the variation range of the analog input voltage to be compared is within the first predetermined range, the bias voltage generation source Generates a bias voltage corresponding to On the other hand, if the variation range of the analog input terminal to be compared is within the second predetermined range, the bias voltage generation source generates a bias voltage corresponding to the second predetermined range. As a result, the comparator can perform a comparison operation based on the optimal bias voltage.

Therefore, the successive approximation type A/D converter of the present invention can increase or decrease the reference power supply voltage when A/D converting a low voltage analog input signal, and as a result, it is possible to perform comparison with sufficient accuracy. Can be done.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, in which an N-channel transistor 1 and a P-channel transistor 2 constitute a first inverter, and an N-channel transistor 3 and a P-channel transistor 4 constitute a first inverter. constitutes the second inverter. N-channel transistor 5 is a constant current source. N-channel transistors 1 and 3 have the same current characteristics, and P-channel transistors 2 and 4 have the same current characteristics.

The gates of the P-channel transistors 2.4 are commonly connected to the node 19, and together constitute a CMO8 differential amplifier. Resistors 8, 9, and N that generate the same resistance value are connected between the reference voltage source VREF and the ground voltage.
A channel transistor 10 is arranged in series, and when the control signal 12 is at a high level, the divided voltage (1/2 (VREF)) across the resistor 8.9 is connected to the N channel via the switch 6.7. applied to the gates of transistors 1.3, respectively. N-channel transistor 1
0 is turned off when the control signal 12 becomes low level, and the voltage of the reference voltage source (V
REF) is applied as is. Capacitor 13 functions to maintain the gate voltage of N-channel transistor 3 even when switch 7 is off.

Assume now that the power supply voltage VDD is 5 volts, the reference voltage VREF is 5 volts, and the analog input signal changes within a range of approximately 0 volts to 1 volt. In this case, the control signal 12 is set to a high level to turn on the N-channel transistor 10. As a result, during the period Ts in FIG.
．． When 7 is turned off, N-channel transistor 1.3
1/2 (VR
A voltage of EF) = 2.5 volts is applied. The operating point of the comparator at this time, that is, the output signal 14 is P in Figure 2-a.
It is located at the position indicated by the entry point on the characteristic curve 23 of the channel transistor. Next, after the period TN in FIG. 5, the switch 6.7 is opened and the conversion is started.

As mentioned above, the input signal 11 in FIG. 1 is 1/2 (V
REF) varies according to -VAN+'VDAC. As a result, when V DAC>V AN, the mutual conductance gm of the N-channel transistor 1 increases, and the operating point of the comparator shifts to point B on the characteristic curve 22 of the P-channel transistor. Therefore, the output signal 14 will be at a high level. On the other hand, when V DAC < VAN, N
Since the mutual conductance gm of the channel transistor 1 decreases, the operating point moves to the 0 point on the characteristic curve 24 of the P-channel transistor, and the output signal 14 becomes low level. Therefore, the output signal 14 changes like the characteristic curve 21 of an N-channel transistor.

Next, a case will be described in which an analog human input signal is used at V REF = 3 volts. If the control signals 1-1-2 are not switched in the same way as above, when the switch 6.7 is closed during the period Ts in FIG. 'EF)=1.5
A bias of volts will be applied. the result,
Since sufficient bias cannot be obtained for the N-channel transistor, the operating point is at point D on the characteristic curve 25.26 in FIG. 2-b. Since sufficient conversion accuracy cannot be obtained at such an operating point, the control signal 12 is shifted to a low level to turn off the N-channel transistor. Then, the bias voltage of the comparator becomes 3 volts, and a good operating point similar to that shown in FIG. 2-a is obtained. In the above embodiment, stable operation can be achieved even if VREF is set to 2 volts.

FIG. 3 is a circuit diagram of a bias voltage generation source used in a second embodiment of the present invention. In the second embodiment, a fuse 31 is used in place of the N-channel transistor 100 of the first embodiment, and by connecting or disconnecting this fuse 31, a bias voltage corresponding to the variation range of the analog input signal is generated. Such a fuse 31 can be connected or disconnected by mask option during one semiconductor manufacturing process.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, Figs. 2-a and 2-b are characteristic curve diagrams explaining the operation of the first embodiment, and Fig. 3 is the invention of the present invention. FIG. 4 is a block diagram of a successive approximation type A/D converter; FIG. 5 is a waveform diagram explaining the operation of the successive approximation type A/D converter; The figure is a circuit diagram of a conventional example. 1.3.5.10 N-channel transistor, 2.4...
...P-channel transistor, 6.7...
...Switch, 8.9...Resistor, 11...Input signal, 12...Control signal, 13...... Capacitor, 14...Output signal, 15...Bias voltage generation source, 31...φ
φ・Qψ・Fuse, 41...D/A converter, 42...Comparator, 43...Successive approximation register, 44...・
...Reference clock generator. Patent Applicant NEC Corporation Agent Patent Attorney Kiyoshi Kuwai - DD Figure 2-a Figure 2-b Figure 3

Claims (1)

[Claims] In a successive approximation type A/D converter that converts a digital value supplied from a successive approximation register into an analog voltage, and compares the analog voltage with an input analog voltage using a comparator, the comparator is a comparator. A successive approximation type A/D converter characterized in that a plurality of bias voltages can be generated by a bias voltage generation source used in operation.