CN113193842A - Capacitor-voltage conversion circuit - Google Patents

Capacitor-voltage conversion circuit Download PDF

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Publication number
CN113193842A
CN113193842A CN202110571054.3A CN202110571054A CN113193842A CN 113193842 A CN113193842 A CN 113193842A CN 202110571054 A CN202110571054 A CN 202110571054A CN 113193842 A CN113193842 A CN 113193842A
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China
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node
signal
transistor
switch
source
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Inventor
陈思婷
陈铖颖
余仕湖
李伯阳
王尘
冯平
杨可
宋长坤
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Xiamen University of Technology
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Xiamen University of Technology
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Priority to CN202110571054.3A priority Critical patent/CN113193842A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5776—Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a capacitor-voltage conversion circuit, which comprises a first operational amplifier, two compensation capacitors, two holding capacitors, a plurality of switches, a first clock signal and a second clock signal, wherein the first operational amplifier is connected with the first compensation capacitor; the first operational amplifier is a differential amplifier with double-end input and double-end output, two input ends of the capacitance-voltage conversion circuit are respectively connected to the differential input end of the first operational amplifier, namely a node b5 and a node b6, through compensation capacitors, one end of a first holding capacitor is connected to a node b5 or a reference potential through switch gating, and the other end of the first holding capacitor is connected to a negative signal end of the differential output end; one end of the second holding capacitor is connected to the node b6 or the reference potential through the switch gate, and the other end is connected to the positive signal end of the differential output end; the gating of the switch is controlled by the first clock signal and the second clock signal, and the conversion of the sampling phase and the amplifying phase of the conversion circuit is realized. The capacitance-voltage conversion circuit has the characteristics of large signal bandwidth, excellent dynamic range, low power consumption and the like, and can meet the precision requirement.

Description

Capacitor-voltage conversion circuit
Technical Field
The invention relates to the field of gyroscope application, in particular to a capacitance-voltage conversion circuit.
Background
In recent years, with the rapid development of micro-mechanical systems (MEMS), capacitive MEMS gyroscopes have been widely used in inertial navigation systems such as satellites, vehicles, and deep sea due to their advantages of low power consumption, low temperature drift, high precision, and compatibility with CMOS processes. The capacitive MEMS gyroscope is used as a sensing transduction unit and converts angular velocity into differential capacitance variable. In order to perform subsequent data processing, an analog front-end circuit (mainly comprising a capacitance-voltage conversion circuit and a Sigma delta analog-to-digital converter) is required to be added between the processor and the MEMS gyroscope to convert the capacitance physical quantity into a digital quantity. The noise floor, dynamic range, linearity, and setup time of the capacitance-voltage conversion circuit as the first stage of the analog front-end circuit are more critical to system success or failure.
Disclosure of Invention
The invention aims to provide a capacitance-voltage conversion circuit which has large signal bandwidth, excellent dynamic range, low power consumption and high precision.
In order to achieve the above purpose, the invention provides the following scheme:
a capacitance-voltage conversion circuit comprises a source differential input end, a source differential output end, a fully differential amplifier circuit unit, a first clock signal input end and a second clock signal input end; the first clock signal input end and the second clock signal input end are respectively used for inputting a first clock signal clk1 and a second clock signal clk 2; the fully differential amplifier circuit unit comprises a first operational amplifier, a switch S25, a switch S26, a switch S34, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1 and a holding capacitor CH 2; the first operational amplifier is a differential amplifier and comprises a differential input end and a differential output end; the negative signal end of the differential input end of the first operational amplifier is connected with a node b5, and the positive signal end of the differential input end of the first operational amplifier is connected with a node b 6; two ends of the compensation capacitor Cc1 are respectively connected to a node b5 and a node a1, and the node a1 is connected to the positive signal end of the source differential input end; two ends of the compensation capacitor Cc2 are respectively connected with a node b6 and a node a2, and the node a2 is connected with the negative signal end of the source differential input end; two ends of the holding capacitor CH1 are respectively connected with a node b4 and a node a 4; two ends of the switch S25 are respectively connected with a node a4 and a reference potential Vref; two ends of the switch S26 are respectively connected with a node a4 and a node b 5; two ends of the holding capacitor CH2 are respectively connected with a node b7 and a node a 7; two ends of the switch S34 are respectively connected with a node a7 and a reference potential Vref; two ends of the switch S35 are respectively connected with a node a7 and a node b 6; the switches S26, S35 are controlled by the first clock signal clk 1; the switches S25, S34 are controlled by the second clock signal clk 2; the first clock signal clk1 and the second clock signal clk2 are used for realizing conversion of a sampling phase and an amplification phase of the capacitance-voltage conversion circuit.
The technical effects are as follows: one end of each of the compensation capacitors Cc1 and Cc2 is connected to the reference potential Vref during sampling phase, one end of each of the holding capacitors CH1 and CH2 is also connected to the reference potential Vref during amplifying phase, so that a real 'virtual point' is formed at the input end of the first operational amplifier U1 during the next sampling phase period, one end of each of the holding capacitors CH1 and CH2 is connected to the reference potential Vref during amplifying phase, and the other end of each of the holding capacitors CH1 and CH2 is used for holding the output voltage value of the first operational amplifier U1 during the previous amplifying phase, so that the zero return operation in the conventional structure is eliminated, and the fast establishment of the output voltage in the period is facilitated.
Further, the fully differential amplifier circuit unit further includes a first gain capacitor array, a second gain capacitor array, a switch S18, a switch S27, a switch S23, a switch S24, a switch S32, and a switch S33;
the circuit configuration of the first gain capacitor array and the circuit configuration of the second gain capacitor array are the same; one end of the first gain capacitor array is connected with the node a1 and is connected with the reference potential Vref through a switch S18; the other end is connected with the node b4 through the switch S24 and is connected with the reference potential Vref through the switch S23; one end of the second gain capacitor array is connected with the node a2 and is connected with the reference potential Vref through the switch S27; the other end is connected with the node b7 through the switch S33 and is connected with the reference potential Vref through the switch S32; the switch S18, switch S23, switch S27, switch S32 are controlled by the first clock signal clk 1; the switches S24, S33 are controlled by the second clock signal clk 2.
Furthermore, the gain capacitor array comprises a basic gain capacitor and a plurality of extended gain capacitors, each extended gain capacitor is connected in parallel with the basic gain capacitor after being connected in series with a switch, and the capacitance value of the gain capacitor array is adjusted through gating the switches.
Further, the first operational amplifier comprises a transistor M0, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9 and a transistor M10; the first operational amplifier comprises a differential input end, a differential output end and a plurality of control input ends; the differential input end of the first operational amplifier is used for inputting a signal Vin and a signal Vip; the differential output end of the first operational amplifier is used for outputting a signal Voutp and a signal Voutn; the control input end of the first operational amplifier is used for inputting a control signal, and comprises: a signal Vbtail, a signal Vcnfbout, a signal Vb1, a signal Vb2, a signal Vb3, and a reference potential Vref; the circuit connection relationship of the internal circuit of the first operational amplifier is as follows: the gate of the transistor M0 is connected with a signal Vstatus, a source grounding potential and a drain is connected with a node t 6; the gate of the transistor M1 is connected to the signal Vin, the source is connected to the node t6, and the drain is connected to the node t 5; the gate of the transistor M2 is connected with a signal Vip, a source connection point t6 and a drain connection point t 7; the gate of the transistor M3 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M5; the gate of the transistor M4 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M6; the gate of the transistor M5 is connected with a signal Vb2, the source is connected with the drain and the drain of the transistor M3 and is connected with a node t8, and the signal Voutp is connected with a node t 8; the gate of the transistor M6 is connected with a signal Vb2, the source is connected with the drain and the drain of the transistor M4 and is connected with a node t9, and the signal Voutn is connected with a node t 9; the gate of the transistor M7 is connected with a signal Vb3, a source electrode connection point t5 and a drain electrode connection point t 8; the gate of the transistor M8 is connected with a signal Vb3, a source electrode connection point t7 and a drain electrode connection point t 9; the grid electrode of the transistor M9 is connected with a signal Vcmfout, the source electrode is connected with a power supply potential, and the drain electrode is connected with a node t 5; the transistor M10 has a gate connected to a signal Vcmfout, a source connected to a power supply potential, and a drain connected to a node t 7.
Further, the first operational amplifier further includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a switch S36, a switch S37, a switch S38, a switch S39, a switch S40, a switch S41, a third clock signal input terminal, and a fourth clock signal input terminal; the circuit connection relationship of the internal circuit of the first operational amplifier further comprises: the signal Voutn is connected to a node r 1; the signal Voutp is connected to a node r 3; two ends of the capacitor C1 are respectively connected with a node r1 and a node r 2; two ends of the capacitor C2 are respectively connected with a node r2 and a node r 3; two ends of the capacitor C3 are respectively connected with a node r4 and a node r 5; two ends of the capacitor C4 are respectively connected with a node r5 and a node r 6; two ends of the switch S36 are respectively connected with a node r1 and a node r 4; two ends of the switch S37 are respectively connected with a node r4 and a signal Vcm; two ends of the switch S38 are respectively connected with a node r2 and a node r 5; two ends of the switch S39 are respectively connected with a node r5 and a reference potential Vref; two ends of the switch S40 are respectively connected with a node r3 and a node r 6; two ends of the switch S41 are respectively connected with a node r6 and a signal Vcm; the third clock signal input end and the fourth clock signal input end are respectively used for inputting a third clock signal clk1a and a fourth clock signal clk2a, the third clock signal clk1a is an early turn-off signal of the first clock signal clk1, the fourth clock signal clk2a is an early turn-off signal of the second clock signal clk2, the switches S36, S38 and S40 are turned on by the third clock signal clk1a, and the switches S37, S39 and S41 are turned on by the fourth clock signal clk2 a.
The technical effects are as follows: the fully differential operational amplifier adopts a folded cascode structure with double-end input and double-end output, and can provide large output swing amplitude. Two clock signals clk1a and clk2a are arranged in the fully differential amplifier to turn off in advance, so that the charge sharing effect on the holding capacitors CH1 and CH2 during phase amplification is reduced, and the accuracy of output signals is improved.
Further, the input common-mode feedback amplifier circuit unit is further included, the input common-mode feedback amplifier circuit unit includes a second operational amplifier, a switch S4, a first feedback capacitor and a second feedback capacitor, and the second operational amplifier includes a differential input end and an output end; two ends of the differential input end of the second operational amplifier are respectively connected with two ends of the source differential input end; the output end of the second operational amplifier is connected with two ends of the source differential input end through the first feedback capacitor and the second feedback capacitor respectively, and is connected with a reference potential Vref through the switch S4; the switch S4 is controlled by the first clock signal clk 1.
The technical effects are as follows: the common-mode value of the two differential input ends of the second operational amplifier U2 is compared with the voltage value of the reference potential Vref, so that error charges generated by the common-mode value are eliminated, the input common-mode voltage of the second operational amplifier U2 is ensured to be stable, and thermal noise caused by common-mode voltage drift is effectively suppressed.
Further, the input common mode feedback amplifier circuit unit further comprises a switch S3 and a switch S5, two ends of the source differential input end are respectively connected with the reference potential Vref through a switch S3, a switch S5, and the switch S3 and a switch S5 are controlled by a first clock signal clk 1.
Further, the internal circuit of the second operational amplifier comprises a transistor M0, a transistor M1a, a transistor M1b, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10; the differential input end of the second operational amplifier comprises a differential input end, an output end and a plurality of control input ends; the differential input end of the second operational amplifier is used for inputting a signal Vin2 and a signal Vip 2; the output end of the second operational amplifier is used for outputting a signal Voutp 2; the control input end of the second operational amplifier is used for inputting a control signal, and comprises: a signal Vbp1, a signal Vbp2, a signal Vbn1, a signal Vbn2, and a reference potential Vref; the gate of the transistor M0 is connected with a signal Vbn2, the source is connected with the ground potential, and the drain is connected with a node t 2; the gate of the transistor M1a is connected to the signal Vin2, the source is connected to the node t2, and the drain is connected to the node t 1; the gate of the transistor M1b is connected with a signal Vip2, a source connection point t2 and a drain connection point t 1; the gate of the transistor M2 is connected to the reference potential Vref, the source is connected to the node t2, and the drain is connected to the node t 3; the gate of the transistor M3 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5; the gate of the transistor M4 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6; the gate of the transistor M5 is connected with a signal Vbn1, the source is connected with the drain and the drain of the transistor M3 are connected with a node t 5; the signal Voutp2 is connected to a node t 5; the gate of the transistor M6 is connected with a signal Vbn1, the source is connected with the drain and the drain of the transistor M4 are connected with a node t 4; the gate of the transistor M7 is connected with a signal Vbp2, a source connection point t1 and a drain connection point t 5; the signal Voutp2 is connected to a node t 5; the gate of the transistor M8 is connected with a signal Vbp2, a source connection point t3 and a drain connection point t 4; the grid electrode of the transistor M9 is connected with a signal Vbp1, the source electrode is connected with power supply potential, and the drain electrode is connected with a node t 1; the transistor M10 has a gate connected to the signal Vbp1, a source connected to the power supply potential, and a drain connected to the node t 3.
The circuit configuration of the first sub capacitor array and the circuit configuration of the second sub capacitor array are the same; one end of the first sub capacitor array and one end of the second sub capacitor array are connected to a node b2, the node b2 is connected to ground potential through a switch S16 and to the reference potential through a switch S17; the other end of the first sub capacitor array and the other end of the second sub capacitor array are respectively connected to two ends of the source differential input end; the switch S16 is controlled by a second clock signal clk2, and the switch S17 is controlled by a first clock signal clk 1.
Furthermore, the sub-capacitor array comprises a basic compensation capacitor and a plurality of extended compensation capacitors, each extended compensation capacitor is connected in parallel with the basic compensation capacitor after being connected in series with a switch, and the capacitance value of the sub-capacitor array is adjusted through gating the switches.
The technical effects are as follows: the compensation capacitor array can select the compensation capacitor through the control switch to form different capacitance values to compensate the parasitic capacitor and eliminate gain error and direct current offset.
The invention realizes the following technical effects:
the capacitor-voltage conversion circuit provided by the invention adopts a two-step approach circuit strategy combining a compensation capacitor and a holding capacitor for differential amplification, can effectively reduce the influence caused by 1/A errors, and realizes the capacitor-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and accuracy.
Drawings
FIG. 1 is a functional block diagram of a capacitance-to-voltage conversion circuit of the present invention;
FIG. 2 is a circuit diagram of one embodiment of a capacitance-to-voltage conversion circuit of the present invention;
FIG. 3 is an internal circuit diagram of a first operational amplifier;
fig. 4 is an internal circuit diagram of the second operational amplifier.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
As shown in fig. 1, the present invention discloses a capacitor-voltage converting circuit, which includes a source differential input terminal, a source differential output terminal, a compensation capacitor array Ccin, an input common mode feedback amplifier circuit unit, a fully differential amplifier circuit unit, a first clock signal input terminal and a second clock signal input terminal; wherein the differential input signals of the source differential input terminals are identified as inp, inn, and the differential output signals of the source differential output terminals are identified as: vop, von. Two ends of the compensation capacitor array are bridged to the source differential input end; the input common mode feedback amplifier circuit unit comprises a differential input end, two feedback signal input ends, an output end and a plurality of switches, wherein the differential input end is respectively connected with two ends of the source differential input end, the two feedback signal input ends are respectively connected with two ends of the source differential input end, and the output end of the input common mode feedback amplifier circuit unit is connected with a reference potential Vref; the fully differential amplifier circuit unit comprises a differential input end, a differential output end and a plurality of switches, the differential input end of the fully differential amplifier circuit unit is connected with the source differential input end, and two ends of the differential output end of the fully differential amplifier circuit unit are respectively connected with two ends of the source differential output end; the first and second clock signal input ends are used for inputting a first clock signal clk1 and a second clock signal clk2, and the first and second clock signals clk1 and clk2 are used for controlling switches in the input common mode feedback amplifier circuit unit and the fully differential amplifier circuit unit so as to realize conversion between a sampling phase and an amplification phase of the capacitor-voltage conversion circuit.
In the embodiment shown in fig. 2, the fully differential amplifier circuit unit includes: the circuit comprises a first operational amplifier U1, a switch S26, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1 and a holding capacitor CH 2; the first operational amplifier U1 is a differential amplifier with differential output;
the circuit connection relationship of the partial circuit units is as follows:
the negative signal end of the differential input end of the first operational amplifier U1 is connected with the node b5, and the positive signal end of the differential input end is connected with the node b 6;
the differential output end of the first operational amplifier U1 is the differential output end of the fully differential amplifier circuit unit, the negative signal end of the differential output end of the first operational amplifier U1 is connected with the negative signal end von of the source differential output end, and the positive signal end of the differential output end is connected with the positive signal end vop of the source differential output end;
two ends of the feedback capacitor Cc1 are respectively connected with a node b5 and a node a1, and the node a1 is connected with a positive signal terminal inp of the source differential input terminal;
two ends of the feedback capacitor Cc2 are respectively connected with a node b6 and a node a2, and the node a2 is connected with a negative signal terminal inn of the source differential input terminal;
the two ends of the holding capacitor CH1 are connected to the node b4 and the node a4, respectively; the two ends of the switch S25 are respectively connected with the node a4 and the reference potential Vref; two ends of the switch S26 are respectively connected with the node a4 and the node b 5; the node b4 is connected with the negative signal end of the differential output end of the first operational amplifier U1;
the two ends of the holding capacitor CH2 are connected to the node b7 and the node a7, respectively; the two ends of the switch S34 are respectively connected with the node a7 and the reference potential Vref; two ends of the switch S35 are respectively connected with the node a7 and the node b 6; the node b7 is connected with a positive signal end of the differential output end of the first operational amplifier U1;
the opening of the switch S26, the switch S35 is controlled by the first clock signal clk 1;
the opening of the switches S25, S34 is controlled by the second clock signal clk 2.
In the embodiment shown in fig. 2, the input common mode feedback amplifier circuit unit includes: the circuit comprises a second operational amplifier U2, a switch S4, a feedback capacitor Cic1 and a feedback capacitor Cic2, wherein the second operational amplifier U2 is a differential amplifier.
The circuit connection relationship of the partial circuit units is as follows:
two ends of a differential input end of the second operational amplifier U2 are respectively connected to a node a1 and a node a 2;
the output terminal of the second op-amp U2 is connected to node b1, node b1 is connected to node a1 through a feedback capacitor Cic1, and is connected to node a2 through a feedback capacitor Cic 2; is connected to a reference potential Vref through a switch S4; wherein the opening of the switch S4 is controlled by the first clock signal clk 1.
The input common mode feedback amplifier circuit unit further comprises a switch S3 and a switch S5, two ends of the source differential input end are respectively connected with a reference potential Vref through a switch S3 and a switch S5, and the switch S3 and the switch S5 are turned on under the control of a first clock signal clk 1.
Carrier _ input is a carrier modulation signal and is output to the off-chip gyroscope. The carrier _ input is connected with a reference potential Vref through a switch S2 by a ground point of a switch S1, wherein the switch S1 is controlled by clk1, and the switch S2 is controlled by clk 2.
The working principle is as follows:
switches S1-S5, S16-S18, S23-S27, and S32-S35 control the conversion between the sampling phase and the amplification phase of the present capacitor-voltage conversion circuit, and when clk1 is equal to 1 and clk2 is equal to 0, the switch controlled by the first clock signal clk1 is turned on (closed), and the present capacitor-voltage conversion circuit enters the sampling phase; when clk1 is equal to 0 and clk2 is equal to 1, the switch controlled by the first clock signal clk1 is turned off, the switch controlled by the second clock signal clk2 is turned on (closed), and the capacitor-voltage converter circuit enters an amplification phase.
A feedback loop formed by the feedback capacitors Cic1, Cic2 and the second operational amplifier U2 forms a three-input single-end output folded cascode structure, the common-mode value of two differential input ends of the second operational amplifier U2 can be compared with the voltage value of the reference potential Vref, and the error charge generated by the part can be eliminated, so that the stability of the input common-mode voltage of the second operational amplifier U2 is ensured, and meanwhile, the thermal noise caused by common-mode voltage drift is effectively inhibited; the two-step approach circuit strategy combining the compensation capacitors Cc1 and Cc2 and the holding capacitors CH1 and CH2 avoids the return-to-zero state of the output voltage in a two-phase clock, and realizes high-speed and high-precision signal output.
The left plates of the compensation capacitors Cc1 and Cc2 are connected to a reference potential Vref during sampling phase, the left plates of the holding capacitors CH1 and CH2 are also connected to the reference potential Vref during amplifying phase, so that a real 'virtual point' is formed at the input end of the first operational amplifier U1 during the next sampling phase period, the left plates of the holding capacitors CH1 and CH2 are connected to the reference potential Vref during amplifying phase, and the right plates hold the output voltage value of the first operational amplifier U1 during the previous amplifying phase, so that the zero resetting operation in the traditional structure is eliminated, and the fast establishment of the output voltage in the period is facilitated.
The compensation capacitor array Ccin can select compensation capacitors by controlling the switches S6-S10 and S11-S15, so that different capacitance values are formed to compensate parasitic capacitors generated by the gyroscope and bonding and eliminate gain errors and direct current offset.
When sampling phase, two polar plates of the gain capacitor array Ci are both connected to a reference potential Vref, the residual charge of the amplification phase in the previous period is eliminated, and the switches S19-S22 and S28-S31 are used for controlling and selecting different gain capacitors, so that the continuous gain adjustment of the circuit is realized.
In the present invention, an example of the internal circuit of a first op-amp U1 is given, as shown in fig. 3. The first operational amplifier U1 is a fully differential operational amplifier, and in this example comprises capacitors C1-C4, switches S36-S41, and transistors M0-M10, and the inputs of the first operational amplifier U1 comprise a signal Vin, a signal Vip, a signal Vbtail, a signal Vcnfbout, a signal Vb1, a signal Vb2, a signal Vb3, and a reference potential Vref; the differential output of the first operational amplifier U1 includes a signal Voutp and a signal Voutn, where the signal Vbtail is the gate bias voltage of the transistor M0 (tail current source), so that M0 operates in the saturation region, and the value of the tail current source is determined; the signal Vcmfbout is a common-mode feedback output voltage of the first operational amplifier U1; the signal Vb1 is the gate bias voltage of the transistors M3 and M4, so that the transistors M3 and M4 work in a saturation region; the signal Vb2 is the gate bias voltage of the transistors M5 and M6, so that the transistors M5 and M6 work in a saturation region; the signal Vb3 is the gate bias voltage of the transistors M7 and M8, so that the transistors M7 and M8 operate in the saturation region.
The specific circuit connection is as follows:
signal Voutn is connected to node r 1;
signal Voutp connects node r 3;
two ends of the capacitor C1 are respectively connected with a node r1 and a node r 2;
two ends of the capacitor C2 are respectively connected with a node r2 and a node r 3;
two ends of the capacitor C3 are respectively connected with a node r4 and a node r 5;
two ends of the capacitor C4 are respectively connected with a node r5 and a node r 6;
two ends of the switch S36 are respectively connected with a node r1 and a node r 4;
two ends of the switch S37 are respectively connected with the node r4 and the signal Vcm;
two ends of the switch S38 are respectively connected with a node r2 and a node r 5;
two ends of the switch S39 are respectively connected with a node r5 and a reference potential Vref;
two ends of the switch S40 are respectively connected with a node r3 and a node r 6;
two ends of the switch S41 are respectively connected with the node r6 and the signal Vcm;
the gate of the transistor M0 is connected to the signal Vbit, the source ground potential and the drain to the node t 6;
the gate of the transistor M1 is connected to the signal Vin, the source is connected to the node t6, and the drain is connected to the node t 5;
the gate of the transistor M2 is connected to the signal Vip, the source is connected to the node t6, and the drain is connected to the node t 7;
the gate of the transistor M3 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M5;
the gate of the transistor M4 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M6;
the grid of the transistor M5 is connected with a signal Vb2, the source is connected with the drain and the drain of the transistor M3 and is connected with a node t8, and the signal outp is connected with a node t 8;
the gate of the transistor M6 is connected with the signal Vb2, the source is connected with the drain and the drain of the transistor M4 and is connected with a node t9, and the signal outn is connected with a node t 9;
the gate of the transistor M7 is connected with the signal Vb3, the source is connected with the node t5, and the drain is connected with the node t 8;
the gate of the transistor M8 is connected with the signal Vb3, the source is connected with the node t7, and the drain is connected with the node t 9;
the gate of the transistor M9 is connected with a signal Vcmfout, the source is connected with a power supply potential, and the drain is connected with a node t 5;
the transistor M10 has a gate connected to the signal Vcmfout, a source connected to the power supply potential, and a drain connected to the node t 7.
The fully differential operational amplifier adopts a folded cascode structure with double-end input and double-end output, and can provide large output swing amplitude. And the fully differential amplifier is provided with two clock signals clk1a and clk2a which are turned off in advance, so that the charge sharing effect on the holding capacitors CH1 and CH2 when the amplifying phase (clk1 is 0 and clk2 is 1) is reduced, and the accuracy of the output signal is improved.
The working principle of the two-step approximation is as follows:
in the sampling phase (clk1 is 1, clk2 is 0), the voltage value of the reference potential Vref is sampled by the left plates of the compensation capacitors Cc1 and Cc2, and the right plates are connected to the input end of the first operational amplifier U1 and the left plates of the holding capacitors CH1 and CH 2. Since the right plates of the holding capacitors CH1 and CH2 are respectively connected to the output terminals von and vop of the first operational amplifier U1, and the left plate is connected to the reference potential Vref in the last amplification phase (clk1 is 0 and clk2 is 1), the reference voltages held by the left plates of CH1 and CH2 are transmitted to the right plates of Cc1 and Cc2 and the input terminal of the first operational amplifier U1 in the sampling phase (clk1 is 1 and clk2 is 0) in this period. This mechanism makes the input of the first op-amp U1 a real "virtual ground" (the offset at the input of the first op-amp U1 is eliminated due to the clamping action of the reference potential Vref). Meanwhile, two polar plates of the gain capacitor array Ci are connected to a reference potential Vref, and residual charges of an amplification phase in the previous period are eliminated.
When amplifying the phase (clk1 is 0, clk2 is 1), the left plate of the gain capacitor array Ci is connected to the input terminal of the first operational amplifier U1, and the right plate is connected to the output terminal of the first operational amplifier U1, forming a circuitΔC/Ci, and performing amplification operation. Meanwhile, the left pole plates of the CH1 and the CH2 are connected to a reference potential Vref, and the right pole plate keeps an output voltage value of the last amplification phase (clk1 is 0 and clk2 is 1), so that the zero resetting operation in the traditional structure is eliminated, a two-step approach circuit strategy is realized, and the fast establishment of the output voltage in the period is facilitated.
In the present invention, an example of the internal circuit of the second op-amp U2 is given, as shown in fig. 4. The second operational amplifier U2 is an input common mode feedback operational amplifier, and includes transistors M0, M1a, M1b, M2, M3, M4, M5, M6, M7, M8, M9, and M10. The input common-mode feedback operational amplifier comprises a differential input end, an output end and a plurality of control input ends, wherein signals Vin2 and signals Vip2 are input into the differential input end; the output terminal outputs a signal outp 2; the control input inputs a signal Vbp1, a signal Vbp2, a signal Vbn1, a signal Vbn2, and a reference potential Vref; the signal Vbp1 is the gate bias voltage of the transistors M9 and M10, so that the transistors M9 and M10 work in a saturation region; the signal Vbp2 is the gate bias voltage of the transistors M7 and M8, so that the transistors M7 and M8 operate in the saturation region; the signal Vbn1 is the gate bias voltage of the transistors M5 and M6, so that the transistors M5 and M6 work in the saturation region; the signal Vbn2 is the gate bias voltage of the transistor M0, which makes the transistor work in the saturation region
The specific circuit connection is as follows:
the gate of the transistor M0 is connected to the signal Vbn2, the source ground potential, and the drain to the node t 2;
the gate of the transistor M1a is connected to the signal Vin2, the source is connected to the node t2, and the drain is connected to the node t 1;
the gate of the transistor M1b is connected with a signal Vip2, a source connection point t2 and a drain connection point t 1;
the gate of the transistor M2 is connected to the signal Vref, the source is connected to the node t2, and the drain is connected to the node t 3;
the gate of the transistor M3 is connected to the node t4, the source ground potential, and the drain is connected to the source of the transistor M5;
the gate of the transistor M4 is connected to the node t4, the source ground potential, and the drain is connected to the source of the transistor M6;
the gate of the transistor M5 is connected to the signal Vbn1, the source is connected to the drain of the transistor M3, and the drain is connected to the node t 5; signal outp2 connects node t 5;
the gate of the transistor M6 is connected to the signal Vbn1, the source is connected to the drain of the transistor M4, and the drain is connected to the node t 4;
the gate of the transistor M7 is connected to the signal Vbp2, the source is connected to the node t1, and the drain is connected to the node t 5; signal outp2 connects node t 5;
the gate of the transistor M8 is connected to the signal Vbp2, the source is connected to the node t3, and the drain is connected to the node t 4;
the gate of the transistor M9 is connected with a signal Vbp1, the source is connected with the power supply potential, and the drain is connected with a node t1 of the drain of the transistor M1 a;
the transistor M10 has a gate connected to the signal Vbp1, a source connected to the power supply potential, and a drain connected to the node t 3.
The input common-mode feedback operational amplifier circuit provided by the invention adopts a three-input single-end output folded cascode structure, can compare the common-mode value of two differential input ends of the main operational amplifier with a reference voltage, and eliminates error charges generated by the common-mode value, thereby ensuring the stability of the input common-mode voltage of the main operational amplifier and effectively inhibiting thermal noise caused by common-mode voltage drift.
The capacitor-voltage conversion circuit provided by the invention adopts a two-step approach circuit strategy combining a compensation capacitor and a holding capacitor for differential amplification, can effectively reduce the influence caused by 1/A errors, and realizes the capacitor-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and accuracy.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A capacitance-to-voltage conversion circuit, characterized by: the full differential amplifier circuit comprises a source differential input end, a source differential output end, a full differential amplifier circuit unit, a first clock signal input end and a second clock signal input end;
the first clock signal input end and the second clock signal input end are respectively used for inputting a first clock signal clk1 and a second clock signal clk 2;
the fully differential amplifier circuit unit comprises a first operational amplifier, a switch S25, a switch S26, a switch S34, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1 and a holding capacitor CH 2;
the first operational amplifier is a differential amplifier and comprises a differential input end and a differential output end;
the negative signal end of the differential input end of the first operational amplifier is connected with a node b5, and the positive signal end of the differential input end of the first operational amplifier is connected with a node b 6;
two ends of the compensation capacitor Cc1 are respectively connected to a node b5 and a node a1, and the node a1 is connected to the positive signal end of the source differential input end;
two ends of the compensation capacitor Cc2 are respectively connected with a node b6 and a node a2, and the node a2 is connected with the negative signal end of the source differential input end;
two ends of the holding capacitor CH1 are respectively connected with a node b4 and a node a 4; two ends of the switch S25 are respectively connected with a node a4 and a reference potential Vref; two ends of the switch S26 are respectively connected with a node a4 and a node b 5;
two ends of the holding capacitor CH2 are respectively connected with a node b7 and a node a 7; two ends of the switch S34 are respectively connected with a node a7 and a reference potential Vref; two ends of the switch S35 are respectively connected with a node a7 and a node b 6;
the switches S26, S35 are controlled by the first clock signal clk 1;
the switches S25, S34 are controlled by the second clock signal clk 2;
the first clock signal clk1 and the second clock signal clk2 are used for realizing conversion of a sampling phase and an amplification phase of the capacitance-voltage conversion circuit.
2. The capacitance-to-voltage conversion circuit of claim 1, wherein: the fully differential amplifier circuit unit further comprises a first gain capacitor array, a second gain capacitor array, a switch S18, a switch S27, a switch S23, a switch S24, a switch S32 and a switch S33;
the circuit configuration of the first gain capacitor array and the circuit configuration of the second gain capacitor array are the same;
one end of the first gain capacitor array is connected with the node a1 and is connected with the reference potential Vref through a switch S18; the other end is connected with the node b4 through the switch S24 and is connected with the reference potential Vref through the switch S23;
one end of the second gain capacitor array is connected with the node a2 and is connected with the reference potential Vref through the switch S27; the other end is connected with the node b7 through the switch S33 and is connected with the reference potential Vref through the switch S32;
the switch S18, switch S23, switch S27, switch S32 are controlled by the first clock signal clk 1; the switches S24, S33 are controlled by the second clock signal clk 2.
3. The capacitance-to-voltage conversion circuit of claim 2, wherein: the gain capacitor array comprises a basic gain capacitor and a plurality of extended gain capacitors, each extended gain capacitor is connected with a switch in series and then connected with the basic gain capacitor in parallel, and the capacitance value of the gain capacitor array is adjusted through a gating switch.
4. The capacitance-to-voltage conversion circuit of claim 1, wherein: the first operational amplifier comprises a transistor M0, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9 and a transistor M10;
the first operational amplifier comprises a differential input end, a differential output end and a plurality of control input ends;
the differential input end of the first operational amplifier is used for inputting a signal Vin and a signal Vip;
the differential output end of the first operational amplifier is used for outputting a signal Voutp and a signal Voutn;
the control input end of the first operational amplifier is used for inputting a control signal, and comprises: a signal Vbtail, a signal Vcnfbout, a signal Vb1, a signal Vb2, a signal Vb3, and a reference potential Vref;
the circuit connection relationship of the internal circuit of the first operational amplifier is as follows:
the gate of the transistor M0 is connected with a signal Vstatus, a source grounding potential and a drain is connected with a node t 6;
the gate of the transistor M1 is connected to the signal Vin, the source is connected to the node t6, and the drain is connected to the node t 5;
the gate of the transistor M2 is connected with a signal Vip, a source connection point t6 and a drain connection point t 7;
the gate of the transistor M3 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M5;
the gate of the transistor M4 is connected with the signal Vb1, the source electrode is connected with the ground potential, and the drain electrode is connected with the source electrode of the transistor M6;
the gate of the transistor M5 is connected with a signal Vb2, the source is connected with the drain and the drain of the transistor M3 and is connected with a node t8, and the signal Voutp is connected with a node t 8;
the gate of the transistor M6 is connected with a signal Vb2, the source is connected with the drain and the drain of the transistor M4 and is connected with a node t9, and the signal Voutn is connected with a node t 9;
the gate of the transistor M7 is connected with a signal Vb3, a source electrode connection point t5 and a drain electrode connection point t 8;
the gate of the transistor M8 is connected with a signal Vb3, a source electrode connection point t7 and a drain electrode connection point t 9;
the grid electrode of the transistor M9 is connected with a signal Vcmfout, the source electrode is connected with a power supply potential, and the drain electrode is connected with a node t 5;
the transistor M10 has a gate connected to a signal Vcmfout, a source connected to a power supply potential, and a drain connected to a node t 7.
5. The capacitance-to-voltage conversion circuit of claim 4, wherein: the first operational amplifier further comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a switch S36, a switch S37, a switch S38, a switch S39, a switch S40, a switch S41, a third clock signal input end and a fourth clock signal input end;
the circuit connection relationship of the internal circuit of the first operational amplifier further comprises:
the signal Voutn is connected to a node r 1;
the signal Voutp is connected to a node r 3;
two ends of the capacitor C1 are respectively connected with a node r1 and a node r 2;
two ends of the capacitor C2 are respectively connected with a node r2 and a node r 3;
two ends of the capacitor C3 are respectively connected with a node r4 and a node r 5;
two ends of the capacitor C4 are respectively connected with a node r5 and a node r 6;
two ends of the switch S36 are respectively connected with a node r1 and a node r 4;
two ends of the switch S37 are respectively connected with a node r4 and a signal Vcm;
two ends of the switch S38 are respectively connected with a node r2 and a node r 5;
two ends of the switch S39 are respectively connected with a node r5 and a reference potential Vref;
two ends of the switch S40 are respectively connected with a node r3 and a node r 6;
two ends of the switch S41 are respectively connected with a node r6 and a signal Vcm;
the third clock signal input end and the fourth clock signal input end are respectively used for inputting a third clock signal clk1a and a fourth clock signal clk2a, the third clock signal clk1a is an early turn-off signal of the first clock signal clk1, the fourth clock signal clk2a is an early turn-off signal of the second clock signal clk2, the switches S36, S38 and S40 are turned on by the third clock signal clk1a, and the switches S37, S39 and S41 are turned on by the fourth clock signal clk2 a.
6. The capacitance-to-voltage conversion circuit of claim 1, wherein: further comprising an input common mode feedback amplifier circuit unit comprising a second operational amplifier, a switch S4, a first feedback capacitance and a second feedback capacitance,
the second operational amplifier comprises a differential input end and an output end;
two ends of the differential input end of the second operational amplifier are respectively connected with two ends of the source differential input end;
the output end of the second operational amplifier is connected with two ends of the source differential input end through the first feedback capacitor and the second feedback capacitor respectively, and is connected with a reference potential Vref through the switch S4;
the switch S4 is controlled by the first clock signal clk 1.
7. The capacitance-to-voltage conversion circuit of claim 6, wherein: the input common mode feedback amplifier circuit unit further comprises a switch S3 and a switch S5, two ends of the source differential input end are respectively connected through a switch S3, a switch S5 and a reference potential Vref, and the switch S3 and the switch S5 are controlled by a first clock signal clk 1.
8. The capacitance-to-voltage conversion circuit of claim 6, wherein: the internal circuit of the second operational amplifier comprises a transistor M0, a transistor M1a, a transistor M1b, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9 and a transistor M10;
the differential input end of the second operational amplifier comprises a differential input end, an output end and a plurality of control input ends;
the differential input end of the second operational amplifier is used for inputting a signal Vin2 and a signal Vip 2;
the output end of the second operational amplifier is used for outputting a signal Voutp 2;
the control input end of the second operational amplifier is used for inputting a control signal, and comprises: a signal Vbp1, a signal Vbp2, a signal Vbn1, a signal Vbn2, and a reference potential Vref;
the gate of the transistor M0 is connected with a signal Vbn2, the source is connected with the ground potential, and the drain is connected with a node t 2;
the gate of the transistor M1a is connected to the signal Vin2, the source is connected to the node t2, and the drain is connected to the node t 1;
the gate of the transistor M1b is connected with a signal Vip2, a source connection point t2 and a drain connection point t 1;
the gate of the transistor M2 is connected to the reference potential Vref, the source is connected to the node t2, and the drain is connected to the node t 3;
the gate of the transistor M3 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5;
the gate of the transistor M4 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6;
the gate of the transistor M5 is connected with a signal Vbn1, the source is connected with the drain and the drain of the transistor M3 are connected with a node t 5; the signal Voutp2 is connected to a node t 5;
the gate of the transistor M6 is connected with a signal Vbn1, the source is connected with the drain and the drain of the transistor M4 are connected with a node t 4;
the gate of the transistor M7 is connected with a signal Vbp2, a source connection point t1 and a drain connection point t 5; the signal Voutp2 is connected to a node t 5;
the gate of the transistor M8 is connected with a signal Vbp2, a source connection point t3 and a drain connection point t 4;
the grid electrode of the transistor M9 is connected with a signal Vbp1, the source electrode is connected with power supply potential, and the drain electrode is connected with a node t 1;
the transistor M10 has a gate connected to the signal Vbp1, a source connected to the power supply potential, and a drain connected to the node t 3.
9. The capacitance-to-voltage conversion circuit of claim 1, wherein: the circuit configuration of the first sub capacitor array is the same as that of the second sub capacitor array;
one end of the first sub capacitor array and one end of the second sub capacitor array are connected to a node b2, the node b2 is connected to ground potential through a switch S16 and to the reference potential through a switch S17;
the other end of the first sub capacitor array and the other end of the second sub capacitor array are respectively connected to two ends of the source differential input end;
the switch S16 is controlled by a second clock signal clk2, and the switch S17 is controlled by a first clock signal clk 1.
10. The capacitance-to-voltage conversion circuit of claim 9, wherein: the sub-capacitor array comprises a basic compensation capacitor and a plurality of expansion compensation capacitors, each expansion compensation capacitor is connected with a switch in series and then connected with the basic compensation capacitor in parallel, and the capacitance value of the sub-capacitor array is adjusted through gating the switch.
CN202110571054.3A 2021-05-25 2021-05-25 Capacitor-voltage conversion circuit Pending CN113193842A (en)

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Application Number Priority Date Filing Date Title
CN202110571054.3A CN113193842A (en) 2021-05-25 2021-05-25 Capacitor-voltage conversion circuit

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