JPS61126823A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To form an A/D converter which converts even an analog input signal coming from a large signal source resistance with high accuracy by decreasing a rush current generated in sampling the analog input signal. CONSTITUTION:When it is supposed that an A/D converter is actuated by a unipolar power supply and a reference voltage VREF of a D/A converter 8 is equal to a power supply voltage, accurate comparison cannot be attained up to the LSB (least significant bit), because a common mode input voltage range of a differential amplifier is narrower in general than the range from zero to the power supply voltage when the analog input signal is zero or equal to the VREF. Then in the conversion within the common mode input voltage range of the differential amplifier 13, the analog input signal and the output signal of the D/A converter 8 are compared directly by the differential amplifier 13 and in the conversion of the analog input signal at the outside of the common mode input voltage range of the differential amplifier 13, a chopper stabilizing system as in a conventional example is adopted. Then the rush current is suppressed to 1/4 of the conventional example.

Description

[Detailed Description of the Invention] (*Field of Industrial Application) The present invention relates to an analog-to-digital converter, and particularly to an MO8
Analog-digital converters (hereinafter referred to as A) made using technology
/D converter).

(Prior art) An example of a successive approximation input/D converter using conventional MO8 technology is published in the magazine "IEEg Journal of 5ol".
id-8tate C1rcuit' VOL, 5C
-13, No, 6゜December 1978.7
It is shown on pages 85-791.

The configuration diagram of this L/DR 91 is shown in Fig. 5. This A/D converter uses a so-called chip-stabilized comparator in which feedback is applied between the input and output of the inverter using a switch. One of its features is that it is designed to reduce

In this circuit, an analog input signal is sampled by a capacitor 5 through all input terminals 1 with switches 2 and 4 turned on and switch 3 turned OFF. Next, switch 2, 4
is turned off and switch 3 is turned on, whereby the analog input signal is held in capacitor t5. Here, the sequence of successive approximation is started, and first, the switch 3
A voltage V (company) r/2 is supplied to the capacitor t5 via t-.

Here, V is the reference voltage supplied to the D/N converter 8. The voltage at node 10 (Yxo) during successive approximation is
It becomes as follows.

vto −(VDAC−VIN) +Vru where,
VDAC is the output voltage of the D/4/converter 8.

VIN indicates the analog input voltage, and VTM indicates the input/output voltage when feedback is applied to the inverter. As is clear from this formula, the analog input voltage is Vttxr /
If it is larger than 2, the output of Innoku Ichiyo 6 indicates "1", and as a result, M2S (@upper bit) of successive approximation register 7 is set to "1", and the output t of D/A converter 8
Set to 3/4 Vtty.

On the other hand, when the analog input voltage is smaller than Yar+r/2, the output of the inverter 6 shows "0", and as a result, the MOB of the successive approximation register is cleared to rOJ, and the D/
Set the output of the A converter 8 to 1/4V/P. These successive approximation operations are continued until the minimum resolution of the D/A converter 8 is achieved, and the conversion results are held in the successive approximation register 7.

In addition, as an example of a pond, there is also
9-132231 Karuru. In this example, like the above-mentioned N/D converter, a chip stabilization method is used for the comparator, and a differential amplifier is used for the amplifier in order to further improve accuracy. A configuration diagram of this A/D converter is shown in FIG. In the figure.

Elements having the same functions as those in FIG. 5 are designated by the same numbers.

In the figure, an analog input signal supplied to an input terminal 1 is connected to a capacitor 5 via a switch 2t. At this time, the other electrode of the capacitor t5 is biased to the output potential vgzr/2 of the D/A converter 8 via the switch 11. Next, by turning off the switch 2°11 and turning on the switch 3ft, the analog input signal is held in the capacitor t5.

The conversion method of this A/D converter is also a successive approximation method like the A/D converter in the #&10 example, and the subsequent explanation of the successive approximation operation will be omitted.

! ! In FIG. 86, the common line 14 is the V of the D/A converter 8.
Connected to azr/2. This is this common line 14
When the potential of V ur/2 is smaller than V ur/2, the node 10 becomes a negative potential when the analog input signal is equal to Vazr/2, and the N-channel MO8 forming the switch 11
A forward current flows between the P-well layer and the N-type diffusion layer forming the FET, which causes the charge held in the capacitor t5 to fluctuate, resulting in a decrease in conversion accuracy. Furthermore, if the potential of this common line 14 is greater than v1/2, when the analog input signal is zero, the node 10 has Vttzr IJ,
A voltage is generated on the top, that is, on the power supply μ, and a forward current flows between the P-type diffusion layer and the N-type substrate of the P-channel MO8FET (7) that constitutes the switch 11, which is maintained at the capacitance [5]. Charge leaks. Therefore, this common line 14t
By biasing to -V, y/2, fluctuations in the charge held in the capacitor 5 are prevented, and analog input signals can be digitally converted over a wide range from zero to the power supply.

However, in these conventional methods, in an A/D converter with a built-in chip stabilization comparator that samples and holds the analog input signal with the capacitor t5, the voltage of the previous analog input signal to be converted and the voltage of the next analog input signal are When a potential difference is created between the conversion target analog input signal voltage and the conversion target analog input signal voltage, the capacitor t5 is charged and discharged at the next sampling of the conversion target analog input signal, so that a so-called rush current flows instantaneously.

For this reason, especially when the resistance of the analog input signal source is large, an error voltage is generated at its input terminal, resulting in a conversion error.

(Object of the Invention) The object of the present invention is to provide an A/
To provide an A/D converter capable of converting even an analog input signal with high precision even with a thick signal source resistance by reducing run: Lt current generated when numbering an analog input signal in a D converter. It is in.

(Configuration of the Invention) The configuration of the analog-to-digital converter of the present invention includes a differential amplifier that differentially amplifies input voltages from first and second input terminals, and a digital signal corresponding to the output voltage of the differential amplifier. A successive approximation register that outputs a digital output signal from the successive approximation register, a D/4 converter that outputs an analog signal corresponding to the digital output signal from the successive approximation register and a comparison reference voltage, and an output signal of the D/A converter. an input circuit that switches an analog input signal to be converted into a digital signal and supplies the output signal to the first and second input terminals through one element each; a first switch means for switching between the analog input signal and connecting the analog input signal tl- to one electrode of the six-dimensional element;
a second switch means that switches the connection to the other electrode of the eyelid element and supplies it to the first input terminal, and switches and connects one electrode of the six-electrode element to the midpoint potential of the reference voltage; and a fourth switch means that connects the output voltage of the D/A converter to the midpoint potential and connects it to the second input terminal.1&: Features.

In the input circuit according to the present invention, the first switch means converts the output signal of the D/A converter into the analog input signal and @
2 timing ξ is connected to one magnetic pole of the gt element by switching the timing Vc rotation/pulling period, and the second switching means switches the connection with the analog input signal connected at the timing # & 1 to the first magnetic pole. At the second timing, the capacity of the capacitive element is switched to the magnetic pole and connected to the first input terminal, and the third switch means connects one pole of the gt element to the first input terminal at the first timing. A fourth switch means connects and disconnects the midpoint potential of the reference voltage at a third timing, and connects the output voltage of the D/A converter connected at the first timing to the second timing. Then, the connection is switched to the midpoint potential and connected to the second input terminal.

(Example) The present invention will be described in detail with reference to the drawings below.

FIG. 1 shows a configuration diagram of an embodiment of an A/D converter according to the present invention, and FIG. 2 shows a timing chart of each switch. In the figure, elements having the same functions as those in FIG. 6 are indicated by the same numbers, and in this embodiment, switches 15 to 18
The connection is different from the conventional example. In this embodiment, switch 2
．． 3 is the lth switch means, and switch 15.16 is the second switch means.
switch means, switch 17 is a third switch means,
The switch 18 corresponds to fourth switch means. This embodiment also employs the successive approximation method, but in this embodiment, the analog input signal is not numbered and held before the successive approximation operation as described in the conventional example.

First, the switches 3, 15, and 17 are turned on, the switch 2.16 is turned off, and the switch 18 is connected to the output 9 side of the D/A converter 8 (conversion period T1 of the upper two bits in FIG. 2). In this switch state, the analog input signal is directly supplied to the normal input terminal of the differential amplifier 13 via the switch 1st-. On the other hand, the inverting input terminal of the differential amplifier 130 is connected to the output 9 of the D/A converter 8 via the switch 18.
connected to. Further, one electrode of the capacitor 5 is connected to the output 9 of the D/A converter 8 via the switch 3, and the other electrode of the capacitor 5 is connected to the Vagr/2 of the D/A converter via the switch 17. connected to electrical potential. Therefore, at the same time as the successive approximation sequence starts, the analog input signal is compared with Vat/2, which is the output signal of the D/A converter 8, by the differential amplifier 13. At the same time, the content 5 is charged with the output signal of the D/&'& converter 8.

In this MSB comparison, the analog input signal is
If it is larger than F/2, the output of the differential amplifier 13 is saturated in the old direction, and the successive approximation register 7 is set to MS8t-rlJ. Then, the output signal of the D/A converter 8 is 3/4
VREF is set and the second bit is compared. At this time, capacitor 5 is 3/4v times the output signal of D/shunter 8? will be charged.

Also, in the MSB comparison, the analog input signal is “Jut”.
If it is smaller than /2, the output of the differential amplifier 13 is saturated in the negative direction, and the successive approximation register 7 is set to MOBfr:rOJ. Then, the output signal of the D/A converter 8 is 1/
4 vRIF' and while the second bit is compared, the capacitor 5 is charged with 1/4 V'apt,r, which is the output signal of the D/switcher 8. By continuing the successive approximation operation on this L5, the capacitor 5 is charged to a voltage close to the analog input signal.

However, here, the A/D converter according to the present invention operates with a single power supply, and furthermore, the reference voltage V of the D/A converter is
is equal to the power supply voltage, then the common mode input voltage range of the differential amplifier 13 is generally when the analog input signal is equal to zero or '/RIIF.

Because it is narrower than the range from zero to the power supply voltage, it is not possible to accurately compare down to L8B (the least significant bit).Therefore, in the present invention, variations and smells within the common mode input voltage range of the differential amplifier 13 are as explained above. The analog input signal and the output signal of the D/switching switch 8 are directly compared by the differential amplifier 13, and the conversion of the analog input signal outside the common mode input voltage range of the differential amplifier 13 is made uniformly stable as in the conventional example. The method is adopted.

The present invention will now be explained in more detail by way of specific examples.

Now, according to the present invention: the power supply voltage and D/D converter of the A/D converter
The reference voltage of the A converter is 5V, and the analog input signal to be converted is 5V.

First, for the upper bits, each switch is set as shown in FIG. 1 within a range that does not exceed the common mode input voltage range of the differential amplifier 13, and successive approximation is performed. In addition, when the amplifier shown in FIG. 4 is used as an example of the differential amplifier 13, its common mode input voltage range is in the range of about 1v to 4v.

Therefore, when performing successive approximation from MOB,
The output voltage of the D/A converter 8 is Z5v-3, 75v-4
, 375V-... However, since the upper limit of the common mode input voltage range of the above-mentioned differential amplifier 13 is approximately 4V, the analog input signal and the D/switching switch 8 Only the second bit can be compared directly with the output signal using a differential amplifier. At this time, the capacitor 5 is charged with a potential difference of 3.75Y and 2.5V.

Next, before starting the conversion of the third bit onwards.

Switches 2 and 16 are ON, switches 3 and 15 are OFF
F'L, the switch 18 is set to the vR meter/2 side of the D/input converter 8 (sampling period T2 in FIG. 2).

Therefore, the analog input signal is sampled by capacitor 5, but at this time capacitor 5 is already 3.75V and 2.5V.
Since it is charged with a potential difference of V, even if an analog input signal of 5 V is input, only a charge corresponding to 1°25 V moves and the Lanier current can be suppressed to a relatively small amount.

On the other hand, according to the conventional example, the analog input signal of Ov is first pulled and held, then converted, and the
57 samples of 5V analog input signal
There was a charge movement corresponding to , and therefore a large Lasche current was flowing.

As described above, according to the present invention, it is possible to suppress the Lanier current to at least 174 compared to the conventional one, and furthermore,
Depending on the bit comparison result, the output of the D/A converter is 4.
It is set to 375 V, and if it is charged to this voltage, the run current can be suppressed to 1/8 of the conventional one.

In the A/D converter according to the present invention, successive approximation of the 3rd bit μ step-down is started by turning the switch 3iON and the switch 2°17 OFF (3-bit TA step-down conversion period T4 in FIG. 2). At this time, when the switch 17 is turned off (T3 in Figure 2), the analog input signal is
The analog input signal and D/A signal are held at node 10.
A differential voltage of the output signal of the converter 8 is generated. This differential voltage is amplified by the differential amplifier 13. The successive approximation operation of the third bit μ drop according to this embodiment is the same as that of the conventional example, and a detailed explanation thereof will be omitted.

FIG. 3 is a block diagram of an embodiment of the pond according to the present invention;
Capacity 19. Buffer amplifiers 20 and 21 consisting of differential amplifiers are added. When converting the upper bit, the capacitor 5 is charged and discharged by the output signal of the D/LR/converter 8, so a run-y current flows, but if the output resistance value of the D/A converter 8 is sufficiently small, the conversion will be performed 4 times. It is possible to directly connect the switch 3 and the output 9 of the D/shunter 8 without affecting. However, if the output resistance value is large, the influence of rack and current becomes a problem. therefore,
As in this embodiment, it is preferable to connect the switch 3 and the output 9 of the D/A converter 8 via the buffer amplifier 20't- connected in a voltage holocouple manner. Further, a buffer amplifier 21 similarly connected as a voltage follower is added in order to avoid mutual interference between the D/switching device 8 and the comparator.

Further, the capacitor 19 is added to the sampling capacitor 5 to compensate for errors caused by leakage current or the like.

Figure 17114 is a circuit diagram of an example of a differential amplifier used in the comparator of the A/D converter of this embodiment. In the figure, 24~
32 is a PCh transistor, 33 to 38 are Nch transistors, 39.40 is an interstage capacitor, and 41 is a switch. The cut-out differential amplifier is Pch) transistor 27,2
The primary stage differential amplifier consists of Pch) U/rasters 31, 32 and Nch
A constant current is supplied to these amplifiers comprised of transistors 36, 37, and 38 from a bias circuit comprised of Pch transistors 24 to 30 and an Nch transistor/transistor 33. This differential amplifier compensates for the input offset voltage of the UJ stage by maintaining the crotch capacitance of 39.40, making it suitable as a high-precision comparator.

(Effects of the Invention) As explained above, according to the present invention, by reducing the Lasche current that occurs when sampling an analog input signal, the conversion speed can be maintained even when the signal source resistance value is large. It is possible to obtain a D/D converter that is capable of highly accurate digital conversion, and is also capable of converting a wide range of analog signals from zero to power supply voltage with a single power supply, and is suitable for monolithic implementation.

[Brief explanation of drawings]

1 and 3 are block diagrams of the first and second embodiments of the present invention, and FIG. 2 is a block diagram of the first and second embodiments of the present invention. Figures I1 and 3 show the operation of the timing diagram, and Figure 44 shows the comparator t- of this embodiment.
FIG. 5 is a circuit diagram of the constituent differential amplifier. Figure 6 shows the N/D/
FIG. 2 is a configuration diagram showing two sides of the exchanger. In the figure, 1.51.52... Input terminal, 2.3.4.1
1.15-18.41...Switch, 5,12
．． 19... Capacity, 6... Inverter,
7...Successive approximation register, 8...D/
A converter, 9... Output, 10... Node, 13.20.21... Differential amplifier, 14...
...Common line. 24~32...Pch) transistor, 33~
38...Nch transistor, 39, 40.
...Interstage gfk, 53... River output terminal. Vvρ 4th function zFF

Claims (1)

[Claims] A differential amplifier that differentially amplifies the input voltage from the first and second input terminals, a successive approximation register that outputs a digital signal according to the output voltage of the differential amplifier, and a digital output from the successive approximation register. A D/A converter that outputs an analog signal according to the signal and a comparison reference voltage, and a D/A converter that switches between the output signal of this D/A converter and the analog input signal to be digitally converted via a capacitive element. and a first input circuit that switches the output signal of the D/A converter with the analog input signal and connects it to one electrode of the capacitive element. switch means for connecting the analog input signal to the other electrode of the capacitive element and supplying the analog input signal to the first input terminal; a third switch means for switching the connection to the midpoint potential and a fourth switch means for switching the connection between the output voltage of the D/A converter to the midpoint potential and connecting it to the second input terminal; An analog-to-digital converter comprising a switch means.