JPS63251820A - Constant current source circuit - Google Patents

Abstract

PURPOSE:To prevent the characteristic variance of a transistor TR as well as the current variance of a constant current source due to the temperature change, by detecting the drain current flowing to the TR and controlling the gate voltage of the TR so that said drain current is kept at a fixed level. CONSTITUTION:The drain current ID of a transistor TRM1 is detected as the voltage value obtained between both terminals of a capacitor in a switched capacitor circuit. This voltage value is sampled and held by a sampling/holding circuit 2 and then compared with the reference voltage value set previously and received from a reference voltage generating circuit 3 via a comparator 4 for decision of the level of the current ID. Then the gate voltage of a 2nd TR, i.e., the gate voltage of the TRM1 is controlled according to the level of the current ID. Thus the current ID is kept at a fixed level. In such a way, a current of a fixed level is obtained regardless of the characteristic variance or the temperature dependence of the TRM1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to MOS (Metal Oxide Sem
The present invention relates to a constant current source circuit having a circuit configuration suitable for fabrication into a 100nductor type semiconductor integrated circuit.

[Conventional technology]

FIG. 6 is a circuit diagram showing a constant current source circuit using a conventional fixed bias method. In the same figure, M is a P-channel MO8FET (hereinafter abbreviated as transistor), R4
, R2 is a resistor, RL is a resistor (load circuit), ■,
is the power supply, and ■ is the transistor M.

VOll indicates the gate-source voltage of the transistor M.

FIG. 7 shows the gate-source voltage v08 versus drain current of the transistor M shown in FIG. It is a graph showing the static characteristics of.

The operation will be explained below with reference to FIGS. 6 and 7.

As can be seen from FIG. 7, the gate of transistor M1
Source-to-source voltage V. If S is constant, the drain current ID is also constant, and a constant current ID flows regardless of the size of the resistor R5.

Here, the gate voltage of the transistor M is the resistor R11
It is determined by the resistance ratio of R2 and the voltage of the power supply V.

Therefore, if the voltage of the power supply V is constant, the gate-source voltage vcls of the transistor M is kept constant, and the transistor M operates as a constant current source.

However, the gate-source voltage V(
11 pairs of drain current! The characteristics include characteristic variations that occur during manufacturing and temperature dependence. In other words, in conventional constant current source circuits, the drain current l, which should be a constant current, is always insufficient to maintain a constant current because no consideration was given to variations in characteristics and temperature fluctuations during manufacturing. It was impossible to say that it was something that could be done.

[Problem that the invention seeks to solve]

Generally, in the semiconductor manufacturing process, there are large variations in characteristics of transistors. Also, transistors have poorer temperature characteristics than resistors, capacitors, etc. However, in the above conventional technology,
As already mentioned, such variations in transistor characteristics and temperature fluctuations are not taken into consideration, and there is a problem in that the current value of the constant current source fluctuates greatly (usually about twice to half the rated current in the MO8IC process). Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a constant current source circuit capable of solving the problems of the prior art described above and suppressing current variations and fluctuations of a constant current source due to variations in transistor characteristics, temperature fluctuations, etc. .

[Means for solving problems]

The above purpose is to achieve the drain current I flowing through the transistor M.
This is achieved by detecting D and controlling the gate voltage of the transistor M so that the drain current ID is constant.

Therefore, in the present invention, first, the drain current of the transistor M is determined. In order to detect this, a second transistor paired with the transistor M is provided to form a current mirror circuit. and a switch capacitor circuit connected to the drain side of the second transistor;
Capacitor (capacitance) in the switched capacitor circuit
A current detection circuit is provided, which includes a first switch circuit for discharging the charge of the second transistor, and a time period during which the drain current of the second transistor flows into the capacitor in the switched capacitor circuit (sampling time); The drain current of the transistor M is detected as the voltage value across the capacitor in the switched capacitor circuit based on the relationship with the amount of charge stored in the capacitor in the switched capacitor circuit. After sample-holding the voltage value in a sample-hold circuit, the comparison circuit compares the voltage value with a basic voltage value from a preset reference voltage generation circuit to determine the magnitude of the drain current ID. By controlling the gate voltage of the second transistor, that is, the gate voltage of the transistor M, accordingly, the drain current is kept constant.

[Effect]

In the current detection circuit described above, the switched capacitor circuit is connected to the drain side of the second transistor, samples and holds the drain current of the second transistor for a certain period of time at a certain period. The first switch circuit operates so as to discharge the charge of a capacitor in the switched capacitor circuit that samples this drain current in synchronization with the operation of each switch in the switched capacitor circuit.

Through these operations, the drain current flowing through the second transistor can be converted into a voltage and detected from both ends of the capacitor in the switched capacitor circuit.

Further, the sample and hold circuit includes the switched sample and hold circuit.
The sampled and held voltage is further sampled and held by the capacitor circuit in synchronization with the switching operation of each switch in the switched capacitor circuit.

Further, the reference voltage generation circuit generates a voltage of a constant value.

Further, the comparison circuit compares the output voltage of the sample hold circuit and the reference voltage of the reference voltage generation circuit,
An error voltage (or current) corresponding to the voltage difference between them is output. Similarly, the output voltage (error voltage) from the comparison circuit is smoothed by a smoothing circuit.

Thus, by applying the smoothed voltage to the gate of the second transistor and to the gate of the transistor M,
The drain voltage fiIp of the transistor M can be controlled. Thereby, this drain current ID is equal to the drain current t! of the second transistor in the switched capacitor circuit. ? Since it is maintained at a certain value determined by the sampling time, the value of the drain current sampling capacitor in the switched capacitor circuit, and the reference voltage, it is independent of the characteristic variations and temperature dependence of the transistor M. A constant current can be obtained.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, 1 is a current detection circuit, 2 is a sample hold circuit, 3 is a reference voltage generation circuit, 4 is a comparison circuit, and 5 is a smoothing circuit. In addition, Ml and M2 are P-channel MO8FETs (hereinafter abbreviated as transistors), V,
, V2. V, respectively, are a power supply, R4 is a resistor, R1 is a resistor (load circuit), S, , S2 . S5゜s4. S5 is a switch circuit, C4, C2, and C5 are capacitors, A1 + A2 tri-amplifiers, and B is an output terminal.

In addition, in FIG. 2, (a) shows the switch circuits S, S2 in FIG. 1, and (b) shows the switch circuits 551S4 and (
Q) is the switch circuit S5, (d) is the switch circuit S6
FIG. 3 is a timing diagram showing the timing of switch operation, respectively. In the same figure, the high level is conductive (ON
) state, and the low level is a non-conducting (OFF) state.

First, with reference to FIGS. 1 and 2, the individual operations of each circuit in FIG. 1 will be explained. The transistor M operates as a constant current source transistor using the resistor RL as a load circuit.

Next, the current detection circuit 11C will be explained. In the switched capacitor circuit, the switch circuit s1. s2.
s, , s4 perform input/output control of the capacitor C1 at regular intervals. The switch circuits S, , S2 include transistors M
2 and the capacitor C1, and the capacitor C
1 is connected to a power supply (ground) K, and the drain current ID2 of the transistor M2 is accumulated in the capacitor C1. Further, the switch circuits S, , S4 operate in synchronization with the switch circuits S, , S2.

These switch circuits s, , s2. s, , s4
Therefore, the capacitor C1 performs sample-and-hold operation. On the other hand, the switch circuit S5 includes the switch circuit S,
t S2, s,.

In synchronization with the operation of S4, the accumulated charge in the capacitor C1 is discharged.

Here, the transistor M2 has the same polarity as the transistor M, and constitutes a current mirror circuit. Therefore, the drain current of transistor M2.

In □, a current proportional to the drain current IDK of the transistor M flows. Also, the voltage vc across the capacitor C1
is the switch circuit S1. S2 is conductive (switch circuit S,
, S4. S5 is in a non-conducting state) time tl
, the capacitance of the capacitor C1 can be expressed as C1. Therefore, the drain current ID2 of the transistor M2 can be detected as the voltage v0 across the capacitor C1.

Moreover, the voltage V of the output terminal B is the switch circuit S5゜S
4 is in the ON state, switch circuits S, , S2 . S5 is OFF
If the voltage of power supply v3 is v5 in the state, then V! l”
” -V, +vs ・・・・・・・・・
Since it can be expressed as (2), the drain current of the transistor M2 can be converted into a voltage and taken out from the output terminal B.

Next, the sample and hold circuit 2 will be explained. The sample and hold circuit 2 detects the voltage V across the capacitor C1.
. , the switch circuits S, , S2°S5. S4,85
The sampled signal is sampled by a switch circuit S6 that operates in synchronization with the sample, and is held in a capacitor C2. Here, the amplifier is acting as an impedance converter.

Next, the % reference voltage generation circuit 5 performs the above (1) and (2).
From the relationship in the equation, the drain current I,2 of transistor M2
A constant voltage (reference voltage V2) corresponding to 1c is generated.

The comparison circuit 4 compares the reference voltage v2 output from the reference voltage generation circuit 3 with the voltage across the capacitor C2 of the sample hold circuit 2, and outputs the result as an error voltage. Here, amplifier A2 operates as a comparator. The output of the amplifier A2 is in a bipedance state when the signal levels of the non-inverting input and the inverting input are equal.

The smoothing circuit 5 smoothes the error voltages output multiple times from the comparison circuit 4.

Next, the overall circuit operation will be explained.

2 from the drain current of the transistor M2 in the current detection circuit 1 is converted into voltage information by the capacitor C1, the nuclear voltage is sampled by the switch circuit S6 of the sample and hold circuit 2, and held by the capacitor C2. This sampled and held voltage is compared in a comparator circuit 4 with a reference voltage v2 output from the reference voltage generating circuit 3.

Here, considering the case where the output voltage of the sample and hold circuit 2 is higher than the reference voltage v2, the output of the comparison circuit 4 becomes a voltage close to the ground voltage. As a result, the charge in the capacitor C3 of the smoothing circuit 5 decreases, and the output voltage of the smoothing circuit 5 decreases. That is, these operations increase the gate-source voltage of the transistors M11M2 and increase the drain current of each transistor.

Next, the output voltage of the sample hold circuit 2 and the reference voltage v
Consider the case where 2 and 2 are equal. At this time, the output of the comparison circuit 4 is not in a high impedance state, and the smoothing circuit 5
The output voltage of is held. therefore,
Transistor M1. The gate-source voltage of M2 is kept constant, and transistor M operates as a constant current source.

Next, the output voltage of the sample and hold circuit 2 is set to the reference voltage v
Consider the case where it is lower than 2. At this time, the comparator circuit 4 outputs a voltage close to the power supply voltage. the result,
The voltage across the capacitor C3 of the smoothing circuit 5 increases, and the voltage between the gates and sources of the transistors M, M2 decreases. That is, an operation is performed to reduce the drain currents of transistors M, , M2.

According to this embodiment, it is possible to configure a constant current source circuit that is not affected by variations in transistor characteristics and temperature fluctuations.

Note that since the amplifier A in the sample and hold circuit 2 is used as an impedance converter, it is clear that a source follower or the like may be used instead of the voltage follower. Furthermore, since the resistor RL is used as a load for the constant current source transistor M, it is clear that an active element such as a transistor may be used in place of the resistor R5.

In addition, in FIG. 1, the transistor M2 of the current detection circuit 1
and the transistor M constituting the current mirror circuit is 1
However, it is clear that by connecting a plurality of transistors to the transistor M2 in a current mirror manner in the same way as the transistor M1, each transistor also functions as a constant current source.

Next, FIG. 3 is a circuit diagram showing another embodiment of the present invention.

In FIG. 3, parts having the same functions as those in FIG. 1 are given the same reference numerals. The difference between this embodiment and the embodiment shown in FIG. 1 is that the P-channel MO3F'E! T M
,, N-channel MOS FET as a substitute for M2
The point is that M, , M4 is used. The operation of the present embodiment can be easily understood analogically from the explanation of the operation of the embodiment of FIG. 1 described above.

According to this embodiment, it is possible to configure a constant current source circuit that is not affected by variations in characteristics of N-channel MOS PETs and temperature fluctuations.

FIG. 4 is a circuit diagram showing still another embodiment of the present invention.

In FIG. 4, parts having the same functions as those in FIG. 1 are given the same reference numerals. The difference between this embodiment and the embodiment shown in FIG. 1 is that the P-channel MO9FIT M,
PNP type bipolar transistor T1 as M20s
．． The point is that T2 is used. Similarly, R2 and R are respective resistances. The operation of this embodiment can also be easily understood analogically from the explanation of the operation of the embodiment of FIG. 1 described above.

According to this embodiment, it is possible to configure a constant current source circuit that is not affected by variations in transistor characteristics and temperature fluctuations even by using PNP type bipolar transistors.

FIG. 5 is a circuit diagram showing yet another embodiment of the present invention.

In FIG. 5, parts K having the same functions as those in FIGS. 1 and 4 are given the same reference numerals.

The difference between this embodiment and the embodiment shown in Fig. 1 is that the P-channel MO
8Fli! The point is that NPN type bipolar transistors T, , 'I'4 are used as substitutes for T Ml and M2.

The operation of this embodiment can also be easily understood analogically from the explanation of the operation of the embodiment of FIG. 1 described above.

According to this embodiment, it is possible to configure a constant current source circuit that is not affected by variations in transistor characteristics and temperature fluctuations even by using NPN bipolar transistors.

〔Effect of the invention〕

According to the present invention, transistors (MOS FE'I', J FET, MlitS
It is possible to realize a constant current source circuit that is free from current variations and fluctuations in current source transistors, with respect to variations in characteristics of transistors (1'ET, bipolar transistors, etc.) and changes in characteristics due to temperature fluctuations.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 to 5 are circuit diagrams showing other embodiments of the present invention, and FIG. 6 is a circuit diagram showing a conventional example of a constant current circuit. , Figure 7 shows a general MOS FET
It is a graph which shows the example of a characteristic. DESCRIPTION OF SYMBOLS 1... Current detection circuit, 2... Sample hold circuit, 3... Reference voltage generation circuit, 4... Comparison circuit, 5...
...Smoothing circuit, Ml, M2...P channel MO8FE
T, M5. M4...N channel MO8FET, C
,, C2, C, . . . capacitor, sl, s2. s,
, s4. s5. s6...Switch circuit, A,, A2...
...Amplifier, RL...Resistance (load circuit), 'I',...
T2...PNP! Transistor, '[',,'I'4
...NPN' type transistor. Agent Patent Attorney Katsuma Ogawa r:・ 1st Ward, Figure 2, Figure 3 “Figure 4 Whole Life!” Road, Figure 5, Figure 7-1VG51

Claims (1)

[Claims] 1. A first transistor element and a bias circuit;
A constant current source circuit that supplies a predetermined current to a load circuit, wherein the first transistor element has first, second, and third transistor elements.
A constant current source circuit has electrodes, the first electrode is connected to a first power supply, the second electrode is connected to a load circuit, and the third electrode is connected to the bias circuit. The circuit includes a second transistor element having three electrodes, a first, a second, and a third electrode, and a switched capacitor circuit;
A first electrode of the transistor element is connected to the first electrode of the first transistor element, and a third electrode of the second transistor element is connected to the third electrode of the first transistor element. to configure a current mirror circuit,
A second electrode of the second transistor element is connected to a second power source via the switched capacitor circuit, and the switched capacitor circuit connects the second electrode of the second transistor element to the second electrode of the second transistor element. A current detection circuit that detects the current flowing to the second power supply and obtains a voltage corresponding to the current value; a sample-and-hold circuit that samples and holds the voltage obtained by the current detection circuit; and a sample-and-hold circuit that generates a reference voltage. a reference voltage generation circuit; a comparison circuit that compares the reference voltage generated by the reference voltage generation circuit with the voltage sampled and held in the sample and hold circuit; and a comparison circuit that smoothes and smooths the error voltage obtained as a result of the comparison. a smoothing circuit that applies the converted error voltage to a third electrode of the second transistor element. 2. In the constant current source circuit according to claim 1, the switched capacitor circuit in the current detection circuit has a first capacitor, one end of the first capacitor, and the second capacitor circuit.
a first switch connected between the second electrode of the transistor element; a second switch connected between the other end of the first capacitor and the second power supply; a third switch connected between one end of the connected side of the first switch in the first capacity and a third power supply; and a connected side of the second switch in the first capacity. a fourth switch, one end of which is connected to one end, and the other end of which is an output terminal of the current detection circuit; and a fifth switch, which is connected in parallel to the first capacitor. - The voltage across the first capacitor is extracted by synchronized opening and closing operations of each of the fifth switches, and corresponds to the current value of the current flowing from the second electrode of the second transistor element to the second power source. The sample-and-hold circuit includes a sixth switch that opens and closes in synchronization with the first and second switches, and a second capacitor, and the sample-and-hold circuit includes a sixth switch that opens and closes in synchronization with the first and second switches, and a second capacitor. A constant current source circuit characterized in that the voltage is sampled and held as a voltage across the second capacitor. 3. The first and second transistor elements are field effect transistors, the first electrode of the first and second transistor elements is a source electrode, the second electrode is a drain electrode, and the third electrode is a 3. A constant current source circuit according to claim 1 or 2, each comprising a gate electrode. 4. The first and second transistor elements are bipolar transistor elements, and the first electrode of the first and second transistor elements is an emitter electrode, the second electrode is a collector electrode, and the third electrode is a collector electrode. A constant current source circuit according to claim 1 or 2, characterized in that the constant current source circuit comprises a base electrode.