JP2012083851A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same.SOLUTION: A semiconductor device includes a first semiconductor element having PN junction, a second semiconductor element having PN junction, and a circuit including the first semiconductor element and the second semiconductor element as constituent elements, and an addition signal in which a first forward voltage generated in the PN junction of the first semiconductor element and a second forward voltage generated in the PN junction of the second semiconductor element are added is output from the circuit. In the semiconductor device, the first semiconductor element and the second semiconductor element are in serial connection, and at actual use temperature regions respectively of the first semiconductor element and the second semiconductor element, a temperature characteristic of a first signal output from the circuit when the circuit does not include the second semiconductor element as the constituent element and a temperature characteristic of a second signal output from the circuit when the circuit does not include the first semiconductor device are inverted.

Description

  The present invention includes a circuit including a first semiconductor element having a PN junction and a second semiconductor element having a PN junction as components, and a first forward voltage generated from the circuit at the PN junction of the first semiconductor element. And a semiconductor device that outputs an addition signal obtained by adding the second forward voltage generated at the PN junction of the second semiconductor element, and a method for manufacturing the same.

  Conventionally, as disclosed in Patent Document 1, for example, a reference voltage circuit including a band gap unit that outputs a reference voltage and a temperature compensation unit that compensates a temperature characteristic of an output signal of the band gap unit has been proposed.

  The band gap unit outputs a reference voltage according to the control voltage, supplies a current according to the reference voltage to the first and second junction type semiconductor elements, and a current flowing through the first junction type semiconductor element. And a differential amplifier that outputs a control voltage to respond.

  When the temperature characteristic of the output signal (reference voltage) of the band gap portion has a peak value, the temperature compensation unit generates a compensation current proportional to the square of the absolute temperature generated according to the control voltage. 2 has the function of being superimposed on the current flowing through the junction type semiconductor element. On the other hand, when the temperature characteristic of the output signal (reference voltage) of the band gap portion has a bottom value, the temperature compensation portion uses the above-described compensation current to flow through the first and second junction type semiconductor elements. The function to subtract from.

  As described above, the reference voltage circuit described in Patent Document 1 includes a temperature compensation unit that compensates for the temperature characteristics of the reference voltage in addition to the band gap unit that outputs the reference voltage. It is controlled so that the temperature characteristic of is constant. Note that the peak value and the bottom value generated in the temperature characteristic of the reference voltage are caused by the temperature characteristic of the forward voltage of the junction type semiconductor element described above.

JP 2009-59149 A

  Incidentally, the reference voltage circuit disclosed in Patent Document 1 includes a temperature compensation unit in addition to the band gap unit in order to make the temperature characteristic of the reference voltage constant. This increases the number of parts of the reference voltage circuit and complicates the configuration. As a result, there arises a problem that the cost increases and the physique increases.

  Therefore, in view of the above problems, the present invention provides a semiconductor device in which the peak value and bottom value of an output signal based on the temperature characteristics of a forward voltage are cancelled, and a method for manufacturing the same, although having a simple structure. With the goal.

  In order to achieve the above-described object, the invention described in claim 1 includes a circuit including a first semiconductor element having a PN junction and a second semiconductor element having a PN junction as constituent elements. A semiconductor device that outputs an addition signal in which a first forward voltage generated at a PN junction of a first semiconductor element and a second forward voltage generated at a PN junction of a second semiconductor element are added, the first semiconductor When the element and the second semiconductor element are connected in series and the circuit does not include the second semiconductor element as a component in the actual use temperature range of each of the first semiconductor element and the second semiconductor element, the output is output from the circuit. The temperature characteristic of the first signal and the temperature characteristic of the second signal output from the circuit when the circuit does not include the first semiconductor element are inverted.

  Thus, according to the present invention, the temperature characteristic of the first signal and the temperature characteristic of the second signal are inverted. That is, when the first signal has a peak value, the second signal has a bottom value, and when the first signal has a bottom value, the second signal has a peak value. In the present invention, the first semiconductor element and the second semiconductor element are connected in series. According to these, the first signal and the second signal whose temperature characteristics are inverted are added, and a signal (addition signal) in which the temperature characteristics of the first signal and the temperature characteristics of the second signal are canceled is output. The As described above, in the present invention, an addition signal in which the temperature characteristic of the forward voltage is canceled is output with a simple configuration. As a result, the number of parts of the semiconductor device is reduced and the configuration thereof is simplified as compared with a semiconductor device having a circuit that compensates the temperature characteristic of the addition signal in addition to the circuit that outputs the addition signal. As a result, the cost is reduced and the physique is reduced.

  As a circuit, as described in claim 2, the circuit includes at least one first semiconductor element and two semiconductor element groups formed by serially connecting the same number of second semiconductor elements as the first semiconductor elements. One end of one semiconductor element group is connected to the inverting input terminal, and one end of the other semiconductor element group is connected to the non-inverting input terminal, and between the output terminal and the inverting input terminal of the first amplifier. A first resistor connected to the first resistor, a second resistor connected between the output terminal and the non-inverting input terminal of the first amplifier, and connected in parallel with the first resistor, and one end of the non-inverting input of the first amplifier. A reference voltage circuit having a third resistor connected to the terminal and having the other end connected to one end of the other semiconductor element group can be employed.

When the semiconductor element group is formed by connecting one first semiconductor element and one second semiconductor element in series, each of the voltage V ₁ of the first signal and the voltage V ₂ of the second signal is one of the semiconductor element groups. The first forward voltage of the first semiconductor element constituting the first semiconductor element is V _PN1 , the second forward voltage of the second semiconductor element is V _PN2 , the resistance values of the _first to third resistors are R _{1 to} R ₃ , and the Boltzmann constant. Where k is the electronic charge, q is the electronic charge, and T is the absolute temperature.

Each of the first terms on the right side of Equations 1 and 2 indicates a negative temperature characteristic, and each of the second terms on the right side indicates a positive temperature characteristic. According to these, the temperature characteristics of the first signal and the second signal can be adjusted by adjusting the value of the second term on the right side (resistance values R _{1 to} R ₃ ). Thereby, the temperature characteristic of the addition signal represented by V ₁ + V ₂ can be adjusted.

  In the case of the configuration according to claim 2, as described in claim 3, the semiconductor element group includes a plurality of first semiconductor elements and the same number of second semiconductor elements as the first semiconductor elements connected in series. The structure which consists of is preferable. According to this, the temperature characteristic of the addition signal can be adjusted by adjusting the numbers of the first semiconductor element and the second semiconductor element.

According to a fourth aspect of the present invention, it is preferable that at least one of the first to third resistors is a variable resistor. Each of the voltages V ₁ and V ₂ depends on the resistance values of the first to third resistors, as shown in Equations 1 and 2. Therefore, the temperature characteristic of the added signal can be adjusted by adjusting at least one resistance value of the first to third resistors.

  Since the invention described in claim 5 has the same effects as the invention described in claim 1, the description thereof is omitted.

  7. The voltage value adjustment according to claim 6, wherein the voltage value of each of the first signal and the second signal is adjusted, and an added signal obtained by adding the first signal and the second signal adjusted in voltage value is output. And an output circuit that outputs the addition signal output from the voltage value adjustment unit to the outside.

  According to this, even if the voltage levels of the first signal and the second signal are different, these values can be adjusted to the same level. Therefore, the temperature characteristic included in the addition signal can be made more effective and constant.

  As a more specific configuration of the voltage value adjusting unit according to the sixth aspect, the configuration according to the seventh to ninth aspects can be employed. That is, as described in claim 7, the voltage value adjustment unit includes a first resistor provided between the output terminal of the first circuit and the output circuit, and an output terminal of the second circuit between the output circuit and the output circuit. And an end of the first resistor on the output circuit side and an end of the second resistor on the output circuit side are connected, and a midpoint of the first resistor and the second resistor is output. A configuration connected to a circuit can be employed. In this case, as described in claim 8, at least one of the first resistor and the second resistor is preferably a variable resistor. According to a ninth aspect of the present invention, the voltage value adjustment unit includes a first switched capacitor circuit formed between the output terminal of the first circuit and the output circuit, an output terminal of the second circuit, and the output circuit. A second switched capacitor circuit formed between the first switched capacitor circuit, an end of the first switched capacitor circuit on the output circuit side and an end of the second switched capacitor circuit on the output circuit side connected to each other. A configuration in which the midpoint of the circuit and the second switched capacitor circuit is connected to the output circuit can be employed.

  According to the structure of Claim 8, each voltage level of a 1st signal and a 2nd signal can be adjusted by changing each resistance value of a 1st resistance and a 2nd resistance. According to the configuration described in claim 9, unlike the configurations described in claims 7 and 8, power consumption can be suppressed.

  As a more specific configuration of the output circuit according to the sixth aspect, the configurations according to the tenth and eleventh aspects can be employed. That is, as described in claim 10, an amplifier circuit can be adopted as the output circuit. In addition, as described in claim 11, a voltage follower circuit can be adopted as the output circuit.

  According to a twelfth aspect of the present invention, it is preferable that the first circuit and the second circuit are plural. According to this, the temperature characteristic of the addition signal can be adjusted by adjusting the numbers of the first circuit and the second circuit.

  In addition, as a more specific configuration of each of the first circuit and the second circuit, the configurations described in claims 13 and 14 can be employed. That is, as described in claim 13, the first circuit includes two first semiconductor elements, one end of one first semiconductor element connected to the inverting input terminal, and one end of the other first semiconductor element not connected. A first amplifier connected to the inverting input terminal, a third resistor connected between the output terminal and the inverting input terminal of the first amplifier, and a connection between the output terminal and the non-inverting input terminal of the first amplifier. And a fourth resistor connected in parallel with the third resistor, a fifth resistor connected at one end to the non-inverting input terminal of the first amplifier, and connected at the other end to one end of the other first semiconductor element. The second circuit includes two second semiconductor elements, one end of one second semiconductor element being connected to the inverting input terminal, and one end of the other second semiconductor element being a non-inverting input. A second amplifier connected to the terminal, and an output terminal and an inverting input terminal of the second amplifier , A seventh resistor connected between the output terminal and the non-inverting input terminal of the second amplifier, connected in parallel with the sixth resistor, and one end of the second resistor connected to the second amplifier. It is possible to adopt a configuration that is a reference voltage circuit that is connected to the non-inverting input terminal and has the other end connected to one end of the other second semiconductor element.

In this configuration, the first signal voltage V ₁ and the second signal voltage V ₂ are the first forward voltage V _PN1 , the second forward voltage V _PN2 , and the resistances of the third to eighth resistors, respectively. When the values are R _{3 to} R ₈ , they are represented by the following formula.

Each of the first terms on the right side of Equations 3 and 4 has a negative temperature characteristic, and each of the second terms on the right side has a positive temperature characteristic. According to these, the temperature characteristic of the first signal and the temperature characteristic of the second signal can be adjusted by adjusting the value of the second term on the right side (resistance values R _{3 to} R ₈ ). Thereby, the temperature specification of the addition signal can be adjusted.

According to a fourteenth aspect, at least one of the third to eighth resistors may be a variable resistor. Each of the voltages V ₁ and V ₂ depends on the resistance values of the third to eighth resistors, as shown in equations 3 and 4. Therefore, the temperature characteristic of the added signal can be adjusted by adjusting at least one resistance value of the third to eighth resistors.

  The first circuit includes, in addition to the first semiconductor element, a first constant current generation circuit that generates a constant current, and a constant current generated by the first constant current generation circuit. A reference voltage circuit having a first current mirror circuit flowing through one semiconductor element and a tenth resistor connected between the first current mirror circuit and the first semiconductor element. In addition to the semiconductor element, a second constant current generating circuit for generating a constant current, a second current mirror circuit for passing a constant current generated by the second constant current generating circuit to the second semiconductor element, and the second current A configuration that is a reference voltage circuit having an eleventh resistor connected between the mirror circuit and the second semiconductor element can be employed.

Also in this configuration, each of the voltage V ₁ of the first signal and the voltage V ₂ of the second signal includes a term having a negative temperature characteristic and a term having a positive temperature characteristic, as shown in Equations 3 and 4. It is represented by the sum of Therefore, the temperature characteristic of the first signal and the temperature characteristic of the second signal can be adjusted by adjusting the value of the term having the positive temperature characteristic. The term having the positive temperature characteristic is determined by the components of the constant current generating circuit according to claim 15 and the resistance values of the tenth and eleventh resistors. This effect will be described in detail in the embodiment.

  As the semiconductor element, a bipolar transistor, a MOS transistor, or a diode can be employed as described in claims 16, 18, and 19. In this case, the collector and base of the bipolar transistor are connected, and the collector and base of the parasitic bipolar transistor formed in the MOS transistor are connected.

  Further, as described in claim 17, when the semiconductor element is a bipolar transistor, it is preferable that the emitter areas of the first semiconductor element and the second semiconductor element are different. According to this, since the addition signal depends on the emitter area, the temperature characteristic of the addition signal can be adjusted.

  The method of manufacturing a semiconductor device according to any one of claims 1 to 19, wherein the circuit, or each of the first circuit and the second circuit, includes a plurality of resistors as constituent elements. It is preferable to adjust the resistance value of the resistor while observing the value of the addition signal by laser trimming. According to this, since the addition signal depends on the resistance value, the temperature characteristic of the addition signal can be adjusted.

1 is a circuit diagram showing a schematic configuration of a semiconductor device according to a first embodiment. It is a graph which shows notionally the temperature dependence of the voltage of each of a 1st signal, a 2nd signal, and an addition signal. It is a graph which shows the temperature dependence and resistance dependence of each voltage of a 1st signal and a 2nd signal, (a) shows the voltage of a 1st signal, (b) shows the voltage of a 2nd signal. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the modification of the semiconductor device which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram illustrating a schematic configuration of the semiconductor device according to the first embodiment. FIG. 2 is a graph conceptually showing the temperature dependence of the voltages of the first signal, the second signal, and the addition signal. FIG. 3 is a graph showing the temperature dependence and resistance dependence of the voltages of the first signal and the second signal, where (a) shows the voltage of the first signal and (b) shows the voltage of the second signal. Indicates.

  The semiconductor device 100 according to this embodiment includes a reference voltage circuit 10. The reference voltage circuit 10 includes two semiconductor element groups 13a and 13b in which a first semiconductor element 11 having a PN junction and a second semiconductor element 12 having a PN junction are connected in series, an amplifier 14, and resistors 15 to 17 And having.

  As shown in FIG. 1, the first resistor 15 and the first semiconductor element group 13a are connected in series between the output terminal 14a of the amplifier 14 and the ground, and the first resistor 15 and the first semiconductor element group 13a are connected. The midpoint is connected to the inverting input terminal 14 b of the amplifier 14. A second resistor 16, a third resistor 17, and a second semiconductor element group 13 b are connected in series between the output terminal 14 a of the amplifier 14 and the ground, and the second resistor 16 and the third resistor 17 are connected to each other. The midpoint is connected to the non-inverting input terminal 14 c of the amplifier 14.

  The first semiconductor element 11 is a PNP transistor in which a collector and a base are connected, and the second semiconductor element 12 is an NPN transistor in which a collector and a base are connected. The collector-base voltage (forward voltage) of each of the PNP transistor and the NPN transistor has a negative temperature characteristic, and the behavior of the temperature characteristic of each forward voltage is different. This difference in the behavior of the temperature characteristic of the forward voltage is due to the difference in impurity concentration between the NPN transistor and the PNP transistor.

When each of the semiconductor element groups 13a and 13b includes only the first semiconductor element 11, as conceptually shown in FIG. 2, the temperature characteristics of the voltage V _BG1 of the first signal output from the reference voltage circuit 10 (FIG. 2). The line indicated by a solid line in FIG. On the contrary, when each of the semiconductor element groups 13a and 13b has only the second semiconductor element 12, the temperature characteristic of the voltage V _BG2 of the second signal output from the reference voltage circuit 10 (shown by a broken line in FIG. 2). The line is convex upward. The difference in behavior of the temperature characteristics of the voltages V _BG1 and V _BG2 is due to the difference in temperature characteristics of the forward voltage between the NPN transistor and the PNP transistor.

The first signal voltage V _BG1 and the second signal voltage V _BG2 are respectively the forward voltage of the first semiconductor element 11 (first forward voltage) V _PN1 and the forward voltage of the second semiconductor element 12 (second Forward voltage) is V _PN2 , resistances R _{1 to} R ₃ are resistance values R _{1 to} R ₃ , Boltzmann constant is k, electron charge is q, and absolute temperature is T, and the emitter areas of the semiconductor elements 11 and 12 are In the case of being identical, it is shown by the following formula.

  Each first term on the right side of Equations 5 and 6 shows negative temperature characteristics, and each second term on the right side shows positive temperature characteristics.

FIG. 3 shows respective temperature characteristics of the voltages V _BG1 and V _BG2 when the resistance values R ₁ and R ₃ are kept constant and the resistance value R ₂ is changed. Figure 3 (a), (b), respectively, three lines (solid, dashed, dashed line) are shown, each three lines, the voltage _V BG1 resistance value _{R 2} are _{different, V BG2} The temperature characteristics are shown. Resistance R ₂ is higher solid, dashed, in the order of one-dot chain line.

As shown in FIG. 3 (a), part to be convex downward in the temperature characteristic of the voltage V _BG1 (bottom) is moved to the low temperature side as the resistance value R ₂ increases. On the contrary, as shown in FIG. 3B, the upwardly convex portion (peak) in the temperature characteristic of the voltage V _BG2 moves to the high temperature side as the resistance value R ₂ increases. Thus, the bottom and the top, shows the opposite behavior with respect to change of the resistance value R _2. According to this, the resistance value R ₂ by varying appropriately, the bottom and top, it can be seen that it is possible to position the same temperature range. The resistance values R _{1 to} R ₃ of the present embodiment are determined so that the bottom and the top are located in the same temperature range in the actual use temperature range (−50 to 170 ° C.) of the semiconductor elements 11 and 12. are, the temperature characteristic of the voltage V _BG1 of the first signal, and the temperature characteristic of the voltage V _BG2 of the second signal is inverted.

By the way, the value obtained by adding the voltage V _BG1 and the voltage V _BG2 corresponds to the voltage V _BG of the output signal (addition signal) of the reference voltage circuit 10, which is expressed by the following equation.

As described above, it shows the temperature characteristic of the voltage V _BG1 of the first signal, and the temperature characteristics of the voltage V _BG2 of the second signal is inverted, the behavior shown by a solid line and a broken line in FIG. According to this, the temperature characteristic of the voltage V _{BG obtained} by adding the voltage V _BG1 and the voltage V _BG2 is constant as shown by a one-dot chain line in FIG.

As described above, the semiconductor device 100 (reference voltage circuit 10) according to the present embodiment has a simple configuration, but the temperature characteristics of the voltage _VBG of the addition signal are constant. As a result, the number of parts of the semiconductor device 100 is reduced and the configuration is simplified as compared with the semiconductor device having a circuit for compensating the temperature characteristic of the voltage _VBG of the addition signal in addition to the reference voltage circuit 10. The As a result, the cost is reduced and the physique of the semiconductor device 100 is reduced.

By the way, in the present invention, in order to position the bottom and the top in the same temperature range, the temperature characteristics of the voltage V _BG of the addition signal are observed with the components of the reference voltage circuit 10 formed on the chip. However, the semiconductor device 100 is manufactured by adjusting the resistance values R _{1 to} R _{3 of} the resistors 15 to 17 by laser trimming. With this manufacturing method, the temperature characteristics of the voltage _VBG are made constant. Note that before forming the components of the reference voltage circuit 10 on the chip, the resistance values R _{1 to} R _{3 in} which the bottom and the top are located in the same temperature range may be obtained in advance.

In the present embodiment, an example is shown in which each of the semiconductor element groups 13a and 13b is formed by connecting one first semiconductor element 11 and one second semiconductor element 12 in series. However, the number of semiconductor elements 11 and 12 is not limited to the above example. As shown in FIG. 4, each of the semiconductor element groups 13 a and 13 b includes a plurality of first semiconductor elements 11 and the same number as the first semiconductor elements 11. The second semiconductor element 12 may be connected in series. According to this, the temperature characteristics of the voltage _VBG of the addition signal can be adjusted by adjusting the numbers of the first semiconductor elements 11 and the second semiconductor elements 12. In this case, the collector and base impurity concentrations of the plurality of semiconductor elements 11 constituting the semiconductor element groups 13a and 13b are different, and the collector and base impurity concentrations of the plurality of semiconductor elements 12 are different. FIG. 4 is a circuit diagram showing a modification of the semiconductor device according to the first embodiment.

In the present embodiment, an example in which the semiconductor device 100 includes the reference voltage circuit 10 has been described. However, as illustrated in FIG. 5, when the resistors 15 to 17 are variable resistors, the semiconductor device 100 adjusts the resistance values R _{1 to} R ₃ of the resistors 15 to 17 in addition to the reference voltage circuit 10. You may have. In this case, each of the resistors 15 to 17 is configured by providing a switch and a resistor for each of a plurality of wirings connected in parallel. Each switch connected in parallel is controlled to open and close based on the information stored in the EEPROM built in the adjustment unit 20, thereby changing the resistance values R _{1 to} R ₃ . As shown in Equation 7, the voltage V _{BG of the} addition signal depends on the resistance values R _{1 to} R ₃ . Therefore, the temperature characteristics of the voltage V _BG of the addition signal can be adjusted by adjusting the resistance values R _{1 to} R ₃ by the adjustment unit 20. Unlike the above-described modification, not all of the resistors 15 to 17 are variable resistors, and one or two of the resistors 15 to 17 may be variable resistors. FIG. 5 is a circuit diagram showing a modification of the semiconductor device according to the first embodiment.

The semiconductor elements 11 and 12 of the present embodiment are bipolar transistors, respectively, and the equations shown in Equations 5 to 7 indicate cases where the emitter areas of the semiconductor elements 11 and 12 are the same. However, for example, the ratio of the emitter area of the first semiconductor element 11 of the first semiconductor element group 13a to the emitter area of the first semiconductor element 11 of the second semiconductor element group 13b is K: L, and the first semiconductor element group Assuming that the ratio of the emitter area of the second semiconductor element 12 of 13a and the emitter area of the second semiconductor element 12 of the second semiconductor element group 13b is M: N, Expression 7 is rewritten as the following expression.

Thus, the voltage V _BG depends not only on the resistance values R _{1 to} R ₃ but also on the emitter area ratios K, L, M, and N. Therefore, the temperature characteristics of the voltage _VBG can be adjusted by adjusting the ratio of the emitter areas.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 6 is a circuit diagram showing a schematic configuration of the semiconductor device according to the second embodiment, and corresponds to FIG. 1 shown in the first embodiment.

  Since the semiconductor device 100 according to the second embodiment is often in common with that according to the first embodiment, a detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In 1st Embodiment, the example which has the reference voltage circuit 10 which contains the semiconductor element groups 13a and 13b as a component was shown. On the other hand, in the present embodiment, the first reference voltage circuit 30 including the first semiconductor element 11 shown in the first embodiment as a component and the second reference voltage circuit 40 including the second semiconductor element 12 as a component. And an added signal obtained by adding the output signals of the first reference voltage circuit 30 and the second reference voltage circuit 40 is output.

The circuit configurations of the first reference voltage circuit 30 and the second reference voltage circuit 40 are similar to those of the reference voltage circuit 10 shown in the first embodiment, and the difference in configuration is that of the provided semiconductor element. Only numbers and types. The first reference voltage circuit 30 is provided with two first semiconductor elements 11, and the second reference voltage circuit 40 is provided with two second semiconductor elements 12. Accordingly, the first reference voltage circuit 30 outputs the first signal voltage V _BG1 , and the second reference voltage circuit 40 outputs the second signal voltage V _BG2 . These voltages V _BG1 and V _BG2 are respectively expressed by _Equations 5 and 6. In order to adjust each voltage level voltage _{V BG1, V BG2,} and the resistance value _R 1 to R ₃ of the resistor 15 to 17 of the first reference voltage circuit 30, the second reference voltage circuit 40 resistance 15-17 The resistance values R _{1 to} R ₃ may be different.

The semiconductor device 100 according to the present embodiment adjusts the voltage values of the first signal voltage V _BG1 and the second signal voltage V _BG2 in addition to the reference voltage circuits 30 and 40, and the adjusted voltage V _BG1. And a voltage value adjustment unit 50 that outputs an addition signal obtained by adding the voltage _VBG2 and an output circuit 60 that outputs the addition signal output from the voltage value adjustment unit 50 to the outside.

The voltage value adjustment unit 50 according to the present embodiment includes a fourth resistor 51 provided between the output terminal of the first reference voltage circuit 30 and the output circuit 60, and the output terminal and output circuit of the second reference voltage circuit 40. And a fifth resistor 52 provided between the first and second resistors. The end of the fourth resistor 51 on the output circuit 60 side and the end of the fifth resistor 52 on the output circuit 60 side are connected, and the midpoint of the fourth resistor 51 and the fifth resistor 52 is connected to the output circuit 60. Yes. With this configuration, by appropriately setting the resistance values R ₄ and R ₅ of the fourth resistor 51 and the fifth resistor 52, the voltage levels of the voltages V _BG1 and V _BG2 are adjusted, and the voltage levels are adjusted. the voltage _{V BG} of the addition signal and the voltage _{V BG1} and the voltage _{V BG2} is added is output. The resistance values R _{1 to} R ₅ described above are determined so that the bottom and the top are located in the same temperature range in the actual use temperature range (−50 to 170 ° C.) of the semiconductor elements 11 and 12. are, the temperature characteristic of the voltage V _BG1 of the first signal, and the temperature characteristic of the voltage V _BG2 of the second signal is inverted. Thus, the temperature characteristic of the voltage _{V BG} that is the voltage _{V BG1} and the voltage _{V BG2} is added, it is constant.

  The output circuit 60 according to the present embodiment is an amplifier circuit, and includes an operational amplifier 61 and a feedback resistor 62. The addition signal output from the voltage value adjustment unit 50 is amplified by the output circuit 60, and the amplified addition signal is output to the outside.

As described above, the semiconductor device 100 according to the present embodiment has a simple configuration, but the temperature characteristics of the voltage _VBG of the addition signal are constant. Thereby, the number of parts of the semiconductor device 100 is reduced and the configuration is simplified. As a result, the cost is reduced and the physique of the semiconductor device 100 is reduced.

By the way, in order to position the bottom and the top in the same temperature range, the inventor performs the voltage operation in a state where the components 30 to 60 of the semiconductor device 100 are formed on the chip as in the first embodiment. The semiconductor device 100 is manufactured by adjusting the resistance values R _{1 to} R _{5 of} the resistors 15 to 17, 51, and 52 by laser trimming while observing the temperature characteristics of V _BG . Note that before forming the components 30 to 60 of the semiconductor device 100 on the chip, the resistance values R _{1 to} R _{5 in} which the bottom and the top are located in the same temperature range may be obtained in advance.

In the present embodiment, an example in which the semiconductor device 100 includes one first reference voltage circuit 30 and one second reference voltage circuit 40 has been described. However, the number of reference voltage circuits 30 and 40 is not limited to the above example, and the semiconductor device 100 may include a plurality of reference voltage circuits 30 and 40. In this case, the output terminals of the plurality of first reference voltage circuits 30 are connected to the voltage value adjustment unit 50 via a first addition circuit (not shown) including a resistor or the like as a component, and the first reference voltage circuit 30 The same number of output terminals of the second reference voltage circuits 40 are connected to the voltage value adjustment unit 50 via second addition circuits (not shown) including resistors and the like as components. According to this, the temperature characteristics of the voltage _VBG of the addition signal can be adjusted by adjusting the number of each of the first reference voltage circuit 30 and the second reference voltage circuit 40. In this case, the impurity concentrations of the collectors and bases of the first semiconductor elements 11 of the plurality of first reference voltage circuits 30 are different, and the collectors and bases of the second semiconductor elements 12 of the plurality of second reference voltage circuits 40 are different. Impurity concentration is different.

Hereinafter, a modification of the semiconductor device 100 according to the second embodiment will be described with reference to FIGS. In this embodiment, the semiconductor device 100 has shown the example which has the reference voltage circuits 30 and 40, the voltage value adjustment part 50, and the output circuit 60. FIG. However, as illustrated in FIG. 7, when the resistors 51 and 52 are variable resistors, the semiconductor device 100 may include an adjusting unit 20 that adjusts the resistance values R ₄ and R ₅ of the resistors 51 and 52, respectively. In this case, each of the resistors 51 and 52 is formed by providing a switch and a resistor for each of a plurality of wirings connected in parallel. Each switch connected in parallel is controlled to open and close based on the information stored in the EEPROM built in the adjustment unit 20, whereby the resistance values R ₄ and R ₅ are changed. The voltage level of the voltage V _BG1 output from the fourth resistor 51 depends on the resistance value R _4, and the voltage level of the voltage V _BG2 output from the fifth resistor 52 depends on the resistance value R ₅ . Therefore, the temperature characteristics of the voltage V _BG of the addition signal can be adjusted by adjusting the resistance values R ₄ and R ₅ by the adjustment unit 20. Similarly to the first embodiment, the resistors 15 to 17 may be variable resistors, and the resistance values R _{1 to} R ₃ may be varied.

  In the present embodiment, an example in which the output circuit 60 is an amplifier circuit is shown. However, the output circuit 60 is not limited to the above example. For example, as shown in FIG. 8, the inverting input terminal and the output terminal of the voltage value adjustment unit 50 are connected, and the non-inverting input terminal and the output terminal are connected. A connected voltage follower circuit can also be employed. In this case, since the voltage level of the addition signal is not inverted, the addition signal output from the output circuit 60 can be easily handled.

In the present embodiment, an example in which the voltage value adjustment unit 50 is configured by the resistors 51 and 52 is shown. However, the constituent elements of the voltage value adjustment unit 50 are not limited to the above example, and may be configured by two switched capacitor circuits, for example, as shown in FIG. In this case, the power consumption can be suppressed as compared with the case where the voltage value adjustment unit 50 is configured by the resistors 51 and 52. As shown in FIG. 9, the switched capacitor circuit includes two switches 53 and 54 connected in series, and a capacitor 55 arranged between the midpoint of the switches 53 and 54 and the ground. According to this configuration, the capacitances of the capacitor 55 of the first switched capacitor circuit connected to the first reference voltage circuit 30 and the capacitors 55 of the second switched capacitor circuit connected to the second reference voltage circuit 40 are respectively determined. By adjusting, the voltage levels of the first signal voltage V _BG1 output from the first reference voltage circuit 30 and the second signal voltage V _BG2 output from the second reference voltage circuit 40 can be adjusted. it can.

  In the present embodiment, the first reference voltage circuit 30 includes the first semiconductor element 11, the amplifier 14, and resistors 15 to 17, and the second reference voltage circuit 40 includes the second semiconductor element 12 and the amplifier 14. And the example comprised by resistance 15-17 was shown. However, the configuration of the reference voltage circuits 30 and 40 is not limited to the above example, and for example, the configuration shown in FIG. 10 can be adopted.

In this modification, the first reference voltage circuit 30 includes, in addition to the first semiconductor element 11, a first constant current generation circuit 71 that generates a constant current, and a constant current generated by the first constant current generation circuit 71. A first current mirror circuit 72 that flows through the first semiconductor element 11 and a sixth resistor 73 connected between the first current mirror circuit 72 and the first semiconductor element 11 are included. The first constant current generating circuit 71 is composed of two PNP transistors and one resistor, and the first current mirror circuit 72 is composed of three NPN transistors and two PNP transistors. In this case, the voltage V _BG1 of the first signal is such that the ratio of the emitter areas of the two PNP transistors constituting the first constant current generation circuit 71 is 1: G, and the resistance value of the resistor constituting the first constant current generation circuit 71 Is R ₆ , and the resistance value of the sixth resistor is R ₇ .

In addition to the second semiconductor element 12, the second reference voltage circuit 40 includes a second constant current generation circuit 74 that generates a constant current, and a constant current generated by the second constant current generation circuit 74. And a seventh resistor 76 connected between the second current mirror circuit 75 and the second semiconductor element 12. The second constant current generation circuit 74 is composed of two NPN transistors and one resistor, and the second current mirror circuit 75 is composed of three NPN transistors. In this case, the voltage V _BG2 of the second signal is such that the ratio of the emitter areas of the two NPN transistors constituting the second constant current generation circuit 74 is 1: H, and the resistance value of the resistor constituting the second constant current generation circuit 74 Is R ₈ , and the resistance value of the seventh resistor is R ₉ .

Also in this configuration, as shown in Equations 9 and 10, each of the first signal voltage V _BG1 and the second signal voltage V _BG2 includes a term having a negative temperature characteristic and a term having a positive temperature characteristic. Represented by the sum. According to this, by adjusting the resistance values R _{6 to} R ₉ and the emitter area ratios G and H, the value of the term having the positive temperature characteristic (the second term on the right side), the voltages V _BG1 and V _BG2 are adjusted. adjust the temperature characteristic, the temperature characteristic of the voltage _{V BG} that is the voltage _{V BG1} and the voltage _{V BG2} is added may be constant.

In the case of the configuration shown in FIG. 10, the voltage value adjustment unit 50 includes buffers 56 and 57 in addition to the resistors 51 and 52. The voltage V _BG1 is output to the output circuit 60 via the first buffer 56 and the fourth resistor 51, and the voltage V _BG2 is output to the output circuit 60 via the second buffer 57 and the fifth resistor 52. .

  In the present embodiment, an example in which the first semiconductor element 11 is a PNP transistor and the second semiconductor element 12 is an NPN transistor is shown. However, the semiconductor elements 11 and 12 are not limited to bipolar transistors, and for example, MOS transistors or diodes can be employed as shown in FIG. When MOS transistors are employed as the semiconductor elements 11 and 12, the collector and base of a parasitic bipolar transistor formed in the MOS transistor are connected. As a matter of course, as the semiconductor elements 11 and 12 constituting the semiconductor device 100 of the first embodiment, a MOS transistor or a diode can be employed instead of a bipolar transistor.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Reference voltage circuit 11 ... 1st semiconductor element 12 ... 2nd semiconductor element 13a, 13b ... 1st semiconductor element group, 2nd semiconductor element group 14 ... Amplifier 15-17 ... First to third resistors 20 ... adjusting unit 30 ... first reference voltage circuit 40 ... second reference voltage circuit 50 ... voltage value adjusting unit 60 ... output circuit 100 ... semiconductor apparatus

Claims (20)

A circuit including a first semiconductor element having a PN junction and a second semiconductor element having a PN junction as constituent elements;
A semiconductor device that outputs an addition signal in which a first forward voltage generated at a PN junction of the first semiconductor element and a second forward voltage generated at a PN junction of the second semiconductor element are added from the circuit. There,
The first semiconductor element and the second semiconductor element are connected in series;
In the actual use temperature range of each of the first semiconductor element and the second semiconductor element, when the circuit does not include the second semiconductor element as a component, temperature characteristics of the first signal output from the circuit; When the circuit does not include the first semiconductor element, the temperature characteristic of the second signal output from the circuit is inverted. The circuit is
Two semiconductor element groups formed by serially connecting at least one first semiconductor element and the same number of second semiconductor elements as the first semiconductor elements;
A first amplifier in which one end of one semiconductor element group is connected to an inverting input terminal and one end of the other semiconductor element group is connected to a non-inverting input terminal;
A first resistor connected between an output terminal and an inverting input terminal of the first amplifier;
A second resistor connected between the output terminal and the non-inverting input terminal of the first amplifier and connected in parallel with the first resistor;
A reference voltage circuit having one end connected to a non-inverting input terminal of the first amplifier and the other end connected to one end of the other semiconductor element group. Item 14. The semiconductor device according to Item 1.   The semiconductor device according to claim 2, wherein the semiconductor element group includes a plurality of first semiconductor elements and the same number of second semiconductor elements as the first semiconductor elements connected in series.   The semiconductor device according to claim 2, wherein at least one of the first to third resistors is a variable resistor. A first circuit including a first semiconductor element having a PN junction as a component;
A second circuit including a second semiconductor element having a PN junction as a component,
A first signal that is output from the first circuit and includes a first forward voltage generated at a PN junction of the first semiconductor element, and a PN junction of the second semiconductor element that is output from the second circuit. A semiconductor device that outputs an addition signal obtained by adding a second signal including a second forward voltage,
A semiconductor device, wherein a temperature characteristic of the first signal and a temperature characteristic of the second signal are inverted in an actual use temperature range of each of the first semiconductor element and the second semiconductor element. A voltage value adjusting unit that adjusts voltage values of the first signal and the second signal, and outputs an addition signal obtained by adding the first signal and the second signal whose voltage values are adjusted;
6. The semiconductor device according to claim 5, further comprising: an output circuit that outputs an addition signal output from the voltage value adjustment unit to the outside. The voltage value adjustment unit is
A first resistor provided between an output terminal of the first circuit and the output circuit;
A second resistor provided between the output terminal of the second circuit and the output circuit,
An end of the first resistor on the output circuit side is connected to an end of the second resistor on the output circuit side, and a midpoint of the first resistor and the second resistor is connected to the output circuit. The semiconductor device according to claim 6.   8. The semiconductor device according to claim 7, wherein at least one of the first resistor and the second resistor is a variable resistor. The voltage value adjustment unit is
A first switched capacitor circuit formed between an output terminal of the first circuit and the output circuit;
A second switched capacitor circuit formed between the output terminal of the second circuit and the output circuit;
An end on the output circuit side in the first switched capacitor circuit and an end on the output circuit side in the second switched capacitor circuit are connected, and a midpoint between the first switched capacitor circuit and the second switched capacitor circuit The semiconductor device according to claim 6, wherein the semiconductor device is connected to the output circuit.   The semiconductor device according to claim 6, wherein the output circuit is an amplifier circuit.   The semiconductor device according to claim 6, wherein the output circuit is a voltage follower circuit.   The semiconductor device according to claim 5, wherein the first circuit and the second circuit are plural. The first circuit includes:
Two first semiconductor elements;
A first amplifier in which one end of one of the first semiconductor elements is connected to an inverting input terminal and one end of the other first semiconductor element is connected to a non-inverting input terminal;
A third resistor connected between an output terminal and an inverting input terminal of the first amplifier;
A fourth resistor connected between the output terminal and the non-inverting input terminal of the first amplifier and connected in parallel with the third resistor;
A reference voltage circuit having one end connected to the non-inverting input terminal of the first amplifier and the other end connected to one end of the other first semiconductor element;
The second circuit includes:
Two second semiconductor elements;
A second amplifier having one end of the second semiconductor element connected to an inverting input terminal and one end of the other second semiconductor element connected to a non-inverting input terminal;
A sixth resistor connected between the output terminal and the inverting input terminal of the second amplifier;
A seventh resistor connected between the output terminal and the non-inverting input terminal of the second amplifier and connected in parallel with the sixth resistor;
A reference voltage circuit having one end connected to the non-inverting input terminal of the second amplifier and the other end connected to one end of the other second semiconductor element. The semiconductor device according to claim 5.   The semiconductor device according to claim 13, wherein at least one of the third to eighth resistors is a variable resistor. The first circuit includes:
In addition to the first semiconductor element,
A first constant current generating circuit for generating a constant current;
A first current mirror circuit for passing a constant current generated by the first constant current generation circuit to the first semiconductor element;
A reference voltage circuit having a tenth resistor connected between the first current mirror circuit and the first semiconductor element;
The second circuit includes:
In addition to the second semiconductor element,
A second constant current generating circuit for generating a constant current;
A second current mirror circuit for passing a constant current generated by the second constant current generation circuit to the second semiconductor element;
13. The semiconductor device according to claim 5, wherein the semiconductor device is a reference voltage circuit having an eleventh resistor connected between the second current mirror circuit and the second semiconductor element. .   16. The semiconductor device according to claim 1, wherein each of the first semiconductor element and the second semiconductor element is a bipolar transistor having a collector and a base connected to each other.   The semiconductor device according to claim 16, wherein the first semiconductor element and the second semiconductor element have different emitter areas.   16. The first semiconductor element and the second semiconductor element are MOS transistors, and a collector and a base of a parasitic bipolar transistor formed in the MOS transistor are connected to each other. 2. A semiconductor device according to item 1.   The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are diodes. A method of manufacturing a semiconductor device according to any one of claims 1 to 19,
Each of the circuit or the first circuit and the second circuit includes a plurality of resistors as components,
A method of manufacturing a semiconductor device, comprising: adjusting a resistance value of the resistor while observing a value of the addition signal by laser trimming.

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