KR101551705B1 - Reference voltage generating circuit - Google Patents

Abstract

A reference voltage generating circuit is provided. The reference voltage generating circuit comprises a first circuit comprising a mirroring element for mirroring a first current proportional to an absolute temperature, a second circuit for generating a second current inversely proportional to the absolute temperature, And a third circuit for generating a reference current using the reference current, the second circuit comprising: a pnp-type BJT for receiving the first current to the emitter; And a resistor connecting the emitter and the base in parallel.

Description

[0001] The present invention relates to a reference voltage generating circuit,

The present invention relates to a reference voltage generating circuit.

The reference voltage is a voltage that is a reference voltage when a different internal voltage is generated in a circuit.

 Especially in recent IT technology, converting analog signal to digital is the most basic and essential technology. This conversion is performed by an analog-to-digital converter (ADC). To operate with accurate resolution without linear errors or other errors, a reference voltage, which is insensitive to variations in temperature or power supply voltage, This is essential.

Although many reference voltage generating circuits have been studied to generate the reference voltage, it is considered that the power consumed by the area and the current path due to the use of circuit elements such as resistors is considered to be an important factor.

In addition, it is necessary to implement a circuit that has a function that, when the temperature of the circuit becomes high, the operation becomes inaccurate or the circuit element is damaged and the operation is automatically turned off when the temperature becomes high. In the case of the conventional reference voltage generating circuit having such a function, the npn-type bipolar junction transistor (BJT) can not be used in a general CMOS integration process, and the fabrication is possible at a level higher than that of the BiCMOS integration process, .

Korea Patent Publication No. 2013-0108174

A problem to be solved by the present invention is to provide a reference voltage generating circuit with improved integration efficiency and added temperature protection function.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a reference voltage generating circuit including a first circuit including a mirroring element for mirroring a first current proportional to an absolute temperature, a second circuit for generating a second current inversely proportional to an absolute temperature And a third circuit for generating a reference current by adding the first current and the second current to generate a reference current and using the reference current to generate a reference voltage, A pnp type BJT to be supplied to the pnp type BJT, and a resistor connecting the emitter of the pnp type BJT and the base in parallel.

The third circuit may include a reference current generating circuit for mirroring the reference current and a converting resistor section for converting the reference current mirrored by the reference current generating circuit into a plurality of reference voltages having different sizes.

The fourth circuit may further include a fourth circuit receiving the reference voltage and the reference current and generating an operation-off signal when the temperature of the reference voltage generation circuit becomes equal to or higher than a first threshold temperature, And an NMOS transistor having a threshold voltage that is equal to or lower than the reference voltage when the temperature of the circuit is equal to or higher than the first threshold temperature.

And a fifth circuit for receiving the reference current by the reference current generation circuit and controlling the amount of current flowing into the drain of the NMOS transistor of the fourth circuit to turn off the NMOS transistor at a second threshold temperature lower than the first threshold temperature, Circuit. ≪ / RTI >

The fifth circuit may include a PMOS transistor that receives a reference current at a source, is turned off when the NMOS transistor is turned on, and is turned on when the NMOS transistor is turned off.

Here, the fourth circuit may further include a noise filter for reducing noise of the operation-off signal.

According to another aspect of the present invention, there is provided a reference voltage generating circuit including a first circuit for providing a reference voltage, a first circuit for providing a reference voltage, A PMOS transistor which is turned on when the NMOS transistor is turned off and is turned on when the NMOS transistor is turned off and which shares the drain with the NMOS transistor; and a PMOS transistor having a drain connected to the drain of the NMOS transistor and a source of the PMOS transistor And a second circuit for providing the same reference current, wherein the NMOS transistor is turned on and the amount of current of the NMOS transistor is reduced so that the threshold voltage of the NMOS transistor is lower than a second threshold temperature lower than the first threshold temperature, .

Other specific details of the invention are included in the detailed description and drawings.

1 is a circuit diagram for explaining a reference voltage generating circuit according to an embodiment of the present invention.
2 is a graph for explaining generation of a reference current according to the present invention.
FIG. 3 is a graph exemplarily showing a change in threshold voltage according to the temperature of the NMOS transistor.
4 is a graph illustrating a hysteresis function of a reference voltage generating circuit according to an embodiment of the present invention.
5 is a flowchart for explaining driving of the reference voltage generating circuit of FIG.
6 is a circuit diagram for explaining driving of the reference voltage generating circuit according to the flowchart of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, a reference voltage generating circuit according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

FIG. 1 is a circuit diagram for explaining a reference voltage generating circuit according to an embodiment of the present invention, and FIG. 2 is a graph for explaining generation of a reference current according to the present invention. FIG. 3 is a graph illustrating an example of a change in a threshold voltage according to a temperature of an NMOS transistor, and FIG. 4 is a graph illustrating a hysteresis function of a reference voltage generating circuit according to an embodiment of the present invention.

Referring to FIG. 1, the reference voltage generating circuit includes a first circuit 100, a second circuit 200, a third circuit 300, and a fourth circuit 400.

The first circuit 100 may mirror the first current I _PTAT that is proportional to the absolute temperature. The first circuit 100 may generate or supply a current having the same characteristics as the first current to mirror the first current I _PTAT , though there is no particular limitation.

Although not particularly limited, the first circuit 100 may include two pnp-type BJT devices (Q ₁ , Q ₂ ), as shown. The emitter and the emitter of the voltage V _eb1 and Q ₂ between the base and the voltage V _eb2 between the base of Q ₁ are as V _R1.

_{V eb1 -V eb2 = V R1 =} V T · ln (m)

In the above equation, V _T can be defined as kT / q as a thermal voltage. Where k is the Boltzmann constant, q is the charge of electrons, and T is the absolute temperature. m represents the area ratio of BJT Q ₁ and Q ₂ . Therefore, V _R1 can be a voltage proportional to the absolute temperature. Therefore, the current I _R1 flowing through R ₁ becomes V _R1 / R ₁ and can be a current proportional to the absolute temperature.

The first circuit 100 may include a mirroring circuit. Specifically mirroring circuit may comprise a PMOS transistor of the M _1, M _2, M ₃ and M ₄ as it is shown. The source and the drain of the PMOS transistor may be shared, respectively, so as to allow the same current to flow.

Here, the term "mirroring" is a concept including not only flowing the same current to another circuit but also flowing the current magnitude constantly. The area ratio of the PMOS transistors of M ₁ and M ₂ is 1, the area ratio of M ₃ is a, and the area ratio of M ₄ is b. According to this source area ratio of M ₃ - flows through the drain, the I _R1 is a boat, a source of M ₄ - may flow I is _R1 b is a drain times. The first current (I _PTAT ) may be the current flowing in the source-drain of M ₄ .

_{I PTAT = b · I R1 =} b · V R1 / R 1 = (b / R 1) · V T · ln (m)

As described above, the first current I _PTAT may be proportional to the absolute temperature.

The second circuit 200 may generate a second current I _CTAT that is inversely proportional to the absolute temperature. The second circuit 200 may have I _Q3 mirrored with a times I _R1 of the pnp type BJT. The second current (I _CTAT ) can be generated using the characteristics between the emitter and base of the pnp-type BJT. The voltage between the emitter and base of the pnp-type BJT is inversely proportional to the absolute temperature. Thus, the voltage V _R2 across the resistor R ₂ connecting the emitter and base of Q3 in parallel can be a voltage inversely proportional to the absolute temperature. Thus, the current flowing in the R ₂ may be inversely proportional to the absolute temperature as V _R2 / R _2.

I _CTAT = I _R2 = V _eb3 / R ₂

As described above, the second current I _CTAT becomes a current flowing through R ₂ and can be inversely proportional to the absolute temperature.

The third circuit 300 includes a reference current generation circuit 310 and a conversion resistor unit 320.

The reference current generating circuit 310 may generate the reference current I _REF by adding the first current I _PTAT and the second current I _CTAT . Since the first current I _PTAT is a current proportional to the absolute temperature and the second current ICTAT is a current inversely proportional to the absolute temperature, the sum of both currents can be a temperature-independent current.

_{I REF = I PTAT + I CTAT} = (b / R 1) · V T · ln (m) + V eb3 / R 2

The first current I _PTAT and the second current I _CTAT can be adjusted by adjusting m, b, R ₁ , and R ₂ , as in the above equation.

Referring to Figure 2, the slope of the first current (I _PTAT) and a second current (I _CTAT) differ only in sign from each other equal to the absolute value so combined by adjusting m, b, R _1, R _2, independent of the temperature A constant reference current I _REF can be generated.

Referring again to FIG. 1, the reference current generating circuit 310 may mirror the reference current I _REF . The reference current generating circuit 310 can mirror the reference current I _REF using the NMOS transistors M ₅ and M ₆ and the PMOS transistors M ₇ and M _{8 as} shown in FIG. have.

The reference current generating circuit 310 generates a reference current I _{REF by combining} the first current I _PTAT and the second current I _CTAT by using M ₅ and M ₆ as the current path 311 Mirroring is possible. The reference current generating circuit 310 can mirror the reference current I _REF using M ₇ and M ₈ on the current path 311. The conversion resistor unit 320 may generate the reference voltages V _REF1 and V _REF2 using the mirrored reference current I _REF . Although not particularly limited, the conversion resistor section 320 may include a plurality of resistors R ₃ and R ₄ connected in series or in parallel.

Referring to FIG. 2, the reference voltages V _REF1 and V _REF2 are products of the reference current I _REF and the resistance, so that they are constant regardless of the temperature.

Referring again to FIG. 1, reference voltages V _REF1 and V _{REF2 in} the case of two series-connected conversion resistors 320 are as follows.

_{V REF1 = I REF × (R} 3 + R 4) = ((b / R 1) · V T · ln (m) + V eb3 / R 2) × (R 3 + R 4)

V _REF2 = I _{REF × R 4 = ((b /} R 1) · V T · ln (m) + V eb3 / R 2) × R 4

As described above, when R ₃ and R ₄ are adjusted, the difference between the supply voltage VDD and V _{SD - M8} (the minimum source-drain voltage required for the M ₈ device to operate in the saturation region) (GND).

The conventional reference voltage generating circuit generates a reference voltage exceeding 1 V, but the reference voltage generating circuit according to an embodiment of the present invention can generate and provide a reference voltage of 1 V or less. Therefore, it is possible to realize a circuit with a more precise resolution.

The fourth circuit 400 may generate an operation-off signal when the temperature of the reference voltage generation circuit according to the embodiment of the present invention is above the first threshold temperature. The fourth circuit 400 may include an NMOS transistor. The NMOS transistor is turned on when the voltage between the gate and the source exceeds a certain voltage. This is called a threshold voltage (V _T ).

The 4 M ₁₀ of the circuit 400 may be provided with a reference current (I _REF) from the PMOS transistor M ₉ to mirror a reference current (I _REF). Specifically, the reference current I _REF may be provided as a drain of M ₁₀ .

Referring to FIG. 3, M ₁₀ is a NMOS transistor having a threshold voltage, and its threshold voltage has a characteristic of decreasing with increasing temperature. The graph of FIG. 3 shows data obtained by measuring the threshold voltage of an actual NMOS transistor three times.

Referring back to Figure 1, M ₁₀ is is above a first limit temperature set in advance is the threshold voltage of M ₁₀ can be not more than the reference voltage (V _REF2). Therefore, M ₁₀ can be turned on. When M ₁₀ is turned on, a thermal shutdown signal may be applied.

M ₁₀ is a device with a low threshold voltage (LTV) and can have a threshold voltage value of less than 500mV at typical room temperature (about 25 ° C). In general, an npn type BJT element may have a characteristic in which a threshold voltage decreases when a temperature rises. However, since the reference voltage generating circuit according to the embodiment of the present invention can be manufactured using a CMOS process, which is a low-cost semiconductor integrated process, an npn type BJT may not be used. Circuits containing npn-type BJTs must use the BiCMOS process, which may increase the cost of circuit design. Therefore, the reference voltage generating circuit of the present invention can be manufactured by using a CMOS process using a PMOS transistor, an NMOS transistor, and a pnp-type BJT, thereby reducing the cost.

The fourth circuit 400 may include a noise filter 410. Although not particularly limited, the noise filter 410 may use a low-pass filter using the resistor R ₅ and the capacitor C ₁ as shown in the figure. The noise filter 410 may reduce the noise of the output.

The fifth circuit 500 may impart a hysteresis characteristic to the fourth circuit 400. The Specifically, the first threshold if the claim 4 M ₁₀ of the circuit 400 is turned on in the temperature and the voltage reference circuit operating near a first threshold temperature, the phenomenon that the whole circuit is often turned on and turned off when the noise is generated Lt; / RTI > Thus, M ₁₀ is turned on, but if more than the first threshold temperature, once the turn-on state, there can be solved the problem not to immediately turn-off may be less than the first threshold temperature. That is, M ₁₀ in a small second threshold temperature above the first temperature limit should be such that the turn-off.

The fifth circuit 500 may include a PMOS transistor (M _12). M ₁₂ may be provided by mirroring the reference current I _REF by M ₁₁ . The reference current I _REF may be provided to the source of M ₁₂ . M ₁₂ can be turned off when M ₁₀ is turned on. Also, M ₁₂ can be turned on when M ₁₀ is turned off.

M ₁₂ can share drain with M ₁₀ . Thus, the drain of M ₁₀ may be provided with two reference currents I _REF (by M ₉ and M ₁₁ ). However, when M ₁₀ is turned on, M ₁₂ is turned off, and the reference current I _REF by M ₁₁ is cut off. Therefore, the amount of current supplied to the drain of M ₁₀ is reduced.

Referring to FIG. 4, when two reference currents I _REF are provided before M ₁₀ is turned on, the threshold voltage of M ₁₀ according to the temperature is equal to 1. However, when M ₁₀ is turned on and M ₁₂ is turned off as described above, only one reference current I _REF is provided to the drain of M ₁₀ , so that the characteristic of the threshold voltage according to the temperature of M ₁₀ is It can change as well.

Therefore, even if the temperature becomes equal to or less than the first threshold temperature, the M < _{10 >} does not turn off when the temperature is equal to or higher than the second threshold temperature, and the stability of the circuit can be improved.

Hereinafter, the driving of the reference voltage generating circuit according to the embodiment of the present invention will be described with reference to FIGS. 5 and 6. FIG. However, the description overlapping with the above embodiment will be omitted.

FIG. 5 is a flowchart for explaining driving of the reference voltage generating circuit of FIG. 1, and FIG. 6 is a circuit diagram for explaining driving of the reference voltage generating circuit of the flowchart of FIG.

Referring to FIG. 5, a proportional to absolute temperature (PTAT) current proportional to an absolute temperature is generated (S500).

Specifically, referring to FIG. 6, I _R1 is generated in the first circuit 100. I _R1 can be generated using two pnp type BJTs. I _R1 can be mirrored b times by M ₁ , M _2, and M ₄ to provide a first current (I _PTAT ).

Referring again to FIG. 5, a proportional to absolute temperature (CTAT) current inversely proportional to the absolute temperature is generated (S510).

Specifically, referring to FIG. 6, I _R2 can be generated using the voltage between the emitter and the base of the pnp-type BJT which is inversely proportional to the absolute temperature. The second current I _CTAT is equal to I _R2 and may be inversely proportional to the absolute temperature.

Referring again to FIG. 5, a reference current I _REF is generated (S520).

Specifically, referring to FIG. 6, the reference current I _REF may be generated by adding the first current I _PTAT and the second current I _CTAT . The generated reference current I _REF may be mirrored and flowed in the current path 311.

Referring again to FIG. 5, reference voltages V _REF1 and V _REF2 are generated (S530).

6, the reference current I _REF flows through the conversion resistor 320 to generate various reference voltages V _REF1 and V _REF2 .

Referring again to FIG. 5, it is determined whether the reference voltage generating circuit is above the first threshold temperature (S540).

Specifically, referring to FIG. 6, since the threshold voltage of M ₁₀ decreases as the absolute temperature rises, the threshold voltage of M ₁₀ at the first threshold temperature or higher may be lower than the reference voltage V _REF2 . Thus M can ₁₀ may be turned on at least a first temperature threshold accordingly.

Referring again to FIG. 5, an operation-off signal is generated (S550).

Specifically, referring to FIG. 6, when M ₁₀ is turned on, V _TEMP may be close to 0V. Therefore, the operation-off signal can be outputted as the VDD value through the three inverters I ₁ , I ₂ , and I ₃ .

Since V _TEMP is substantially close to 0V, M ₁₀ can be very large. However, if the size of M ₁₀ is large, the stability of the circuit can be enhanced. This is because the threshold voltage of the MOS transistor is very sensitive to process variations. The larger the size (width and channel length) of the MOS transistor, the less the rate of change of the threshold voltage with respect to the process variation It is because.

Referring again to FIG. 5, I _TEMP is decreased (S560).

Specifically, referring to FIG. 6, when M ₁₀ is turned on, V _TEMP becomes close to 0 V, and the gate voltage of M ₁₂ can be VDD by the inverter. Since M ₁₂ is a PMOS transistor, the gate voltage is large and can be turned off. Thus, the two reference currents I _REF provided by M ₉ and M ₁₁ can be reduced to one reference current I _REF provided by M ₉ . Thus, I _TEMP can be reduced.

Referring again to FIG. 5, it is determined whether the reference voltage generating circuit is below a second threshold temperature (S570).

Specifically, referring to FIG. 6, as the I _TEMP decreases, the decreasing ratio of the threshold voltage to the temperature increases (see (2) in FIG. 4), and accordingly, the preset reference voltage V _REF2) and can be equal to the threshold voltage of M _10. That is, the threshold voltage may be _greater than the reference voltage V _REF2 below the second threshold temperature. Thus, M ₁₀ can be turned off below the second threshold temperature.

Referring again to FIG. 5, the operation-off signal is canceled (S580).

Specifically, referring to FIG. 6, when M ₁₀ is turned off, the value of V _TEMP may be VDD. Therefore, the operation-off signal can be output to 0 V through the three inverters I ₁ , I ₂ , and I ₃ .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: first circuit 200: second circuit
300: third circuit 400: fourth circuit
500: fifth circuit

Claims (7)

In the reference voltage generating circuit,
A first circuit comprising a mirroring element for mirroring a first current proportional to an absolute temperature;
A second circuit for generating a second current that is inversely proportional to the absolute temperature;
A third circuit for generating a reference current by summing the first current and the second current and generating a reference voltage using the reference current; And
And a fourth circuit receiving the reference voltage and the reference current and generating an operation-off signal when the temperature of the reference voltage generation circuit becomes equal to or higher than the first threshold temperature,
The second circuit includes a pnp type BJT that receives the first current to the emitter,
And a resistor connecting the emitter of the pnp-type BJT and the base in parallel,
Wherein the fourth circuit includes an NMOS transistor whose threshold voltage is less than or equal to the reference voltage when the temperature of the reference voltage generating circuit is above the first threshold temperature. The method according to claim 1,
The third circuit includes a reference current generation circuit for mirroring the reference current,
And a conversion resistor section for converting the reference current mirrored by the reference current generation circuit into a plurality of reference voltages having different magnitudes. delete The method according to claim 1,
And a fifth circuit for receiving the reference current and controlling an amount of current flowing into the drain of the NMOS transistor of the fourth circuit to turn off the NMOS transistor at a second threshold temperature less than the first threshold temperature, Voltage generating circuit. 5. The method of claim 4,
Wherein the fifth circuit includes a PMOS transistor having a reference current supplied to a source, turned off when the NMOS transistor is turned on, and turned on when the NMOS transistor is turned off. The method according to claim 1,
And the fourth circuit further comprises a noise filter for reducing noise of the operation-off signal. A reference voltage generating circuit for providing a reference voltage,
A first circuit for providing a reference voltage;
An NMOS transistor whose threshold voltage is equal to or lower than the reference voltage when the temperature of the reference voltage generation circuit becomes equal to or higher than the first threshold temperature;
A PMOS transistor that is turned off when the NMOS transistor is turned on and is turned on when the NMOS transistor is turned off, and shares the drain with the NMOS transistor;
And a second circuit for providing the same reference current to the drain of the NMOS transistor and the source of the PMOS transistor,
Wherein the amount of current of the NMOS transistor is reduced as the NMOS transistor is turned on so that the threshold voltage of the NMOS transistor becomes larger than the reference voltage at a second threshold temperature lower than the first threshold temperature.

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