JP2008204148A - Reference voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage circuit which is available with a power supply voltage of 1V or less, and reduces power consumption and increases temperature stability. <P>SOLUTION: This reference voltage circuit comprises two FETs (M<SB>1</SB>, M<SB>2</SB>) operating in a weak reverse region and current bias circuits (M<SB>3</SB>, M<SB>4</SB>or the like) for applying current bias to each FET, and configured to apply reverse bias for the source/back gate connection of the FET (M<SB>1</SB>), and to apply zero bias for the source/back gate connection of the FET (M<SB>2</SB>), and to output a difference voltage between the gate/source voltage of the FET (M<SB>1</SB>) and the gate/source voltage of the FET (M<SB>2</SB>) as a reference voltage V<SB>ref</SB>. Thus, it is possible to equalize the temperature curves of the gate/source voltages of the FETs (M<SB>1</SB>, M<SB>2</SB>) by adjusting the size of elements. Then, the difference voltage of the gate/source voltages of the both FET (M<SB>1</SB>, M<SB>2</SB>) is made constant, so that it is possible to output this difference voltage as the reference voltage Vref, and to obtain a fine temperature-independent reference voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reference voltage circuit that monitors a reference voltage circuit that generates a reference voltage, and more particularly to a reference voltage circuit that operates with a low voltage and low power consumption and can be designed with extremely small temperature dependence of an output voltage.

  In recent years, research and development of wireless sensor network (WSN) technology has progressed as part of ubiquitous network technology, and energy that has been discarded in the conventional environment such as sunlight, weak radio waves, and vibrations. Have been developed to obtain the sensor node drive energy from (see Non-Patent Documents 1 and 2). Since the sensor nodes of these wireless sensor networks are operated by a weak energy source obtained from the environment, they are required to operate with extremely low power consumption. In designing such an ultra-low power consumption LSI constituting a sensor node, a reference voltage circuit with low power consumption and high accuracy is required.

  Also, in the last few years, the power supply voltage of the CMOS circuit is expected to drop to 1 V or less. In that case, the circuit structure of the conventional bandgap reference (see Non-Patent Document 3) is not practical.

  Under such circumstances, an ultra-low voltage / ultra-low power consumption reference voltage circuit that is less dependent on the output voltage with respect to variations in temperature and power supply voltage has become important in general analog circuits.

  As a conventional reference voltage circuit, Non-Patent Document 4 presents a CMOS reference voltage circuit having a power supply voltage of 1.2 V and a power consumption of about 4.3 μW. This reference voltage circuit uses a MOSFET that operates in a weak inversion region, and its temperature coefficient (temperature coefficient (T.C.)) is 119 ppm / ° C.

  Non-Patent Document 5 presents a CMOS reference voltage circuit based on a weighted difference between gate-source voltages of two MOSFETs operating in a saturation region. The minimum power supply voltage of this circuit is 1.4 V, and the power supply current is 9.7 μA.

  Non-Patent Documents 6 and 7 present a reference voltage circuit based on a threshold voltage difference between two MOSFETs, and Non-Patent Document 8 presents a reference voltage circuit based on a threshold voltage sum of two MOSFETs.

  Non-Patent Document 9 presents a pure CMOS threshold reference voltage circuit. Non-Patent Documents 10 and 11 present reference voltages based on peaking current sources.

  As described above, an ultra low power consumption LSI used in micro power electronics such as a sensor node of a WSN requires a reference voltage circuit that can be operated with a power supply voltage of 1 V or less. However, the reference voltage circuits of Non-Patent Documents 4, 5, and 9 to 11 do not satisfy the above voltage condition because the power supply voltage is as high as 1.2 V and the power consumption is about 4.3 μW. Therefore, it is not suitable for use in an ultra-low power consumption LSI with a power supply voltage of 1 V or less.

  In addition, the reference voltage circuits described in Non-Patent Documents 6 to 8 require an additional manufacturing process for general CMOS technology.

  A conventional bandgap voltage reference cannot be designed to have a power supply voltage of 1.2V or less because the bandgap circuit generates a voltage of 1.2V. Therefore, in order to lower the reference voltage, several circuit techniques have been proposed and devised to lower the power supply voltage to 1 V or less (see Non-Patent Documents 12-14).

FIG. 9 shows a reference voltage circuit described in Non-Patent Document 12. This reference voltage circuit includes three p-channel MOSFETs (M ₁ , M ₂ , M ₃ ), one operational amplifier (AMP), four resistors (R ₁ , R ₂ , R ₂ , R ₃ ), and two It is composed of bipolar transistors (Q ₁ , Q ₂ ). In the circuit of FIG. 9, the reference voltage V _ref is given by the following equation (1).

Where V _T (= kT / q≈26 mV (at T = 300 ° K)) is a thermal voltage, k is a Boltzmann's constant, q is an electronic charge, T is an absolute temperature, and N is Q ₁ to Q ₂ emitter area ratio.
S. Roundy, PK Wright, and JM Rabaey, "Energy Scavenging for Wireless Sensor Networks with Special Focus on Vibrations", New York: Kluwer, 2004. J. Pan, BC Xue, and Y. Inoue, "A Self-Powered Sensor Module Using Vibration-Based Energy Generation for Ubiquitous Systems," Proc, ASICON, pp.443-4465 Oct. 2005. PR Gray et al., “Analog Integrated Circuit Design Technology (Part 1)”, Original 4th Edition, Baifukan, 2003, pp. 377-381. G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutri, "A low-voltage low-power voltage reference based on sub-threshold MOSFETs", IEEE J. Solid-State Circuits, vol.38, no.1 , pp.151-154, Jan. 2003. KN Leung and PKT Mok, "A CMOS voltage reference based on weighted Vgs for CMOS low-dropout linear regulators," IEEE J. Solid-State Circuits, vol.38, no.1, pp.146150, Jan. 2003. RA Blauschiid, PA, Tucci, RS Muller, and RG Meyer, A new NMOS temperature-stable voltage reference, IEEE J. Solid-State Circuits, vol.SC-13, no, 6, pp.76? -774, Dec. 1978 HJ Song and C. Kim, "A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET's," IEEE J. Solid State Circuits, vol.28, no.6, pp.671-677, June 1993 . M. Ugajin, K. Suzuki, and T. Tsukaraha, "A 0.6-V supply, voltage-reference circuit based on threshold-voltage summation architecture in fully-depleted CMOS / SOI," IEICE trans. Electron, vol.E85-C , no.8, pp.1588-1595, Aug. 2002. T. Matsuda, R. Minami, A. Kanamori, Ijf. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, and S. Nakajima, "A temperature and supply voltage independent CMOS voltage reference circuit," IEICE Trans. Electron ., vol.E88-C, no.5, pp.1087-1093, May 2005. K. Kimura, "Low temperature coefficient CMOS voltage reference circuit," IEICE Trans. Fundamentals, vol.E77-A, no.2, pp.398-402, Feb. 1994. MH Cheng and ZW Wu, "A low-power low-voltage reference using peaking current mirror circuit," Electron. Lett., Vol.41, no.10, pp.572-573, May 2005. H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-State Circuits, vol.34, no.5, pp, 670-674, May 1999. H. Neuteboom, BMJ Kup, and M. Janssens, "A DSPbased hearing instrument IC," IEEE J. Solid-State Circuits, vol.32, no.11, pp.1790-1806, Nov. 1997. KN Leung and PKT Mok "A sub-1-V 15-ppm / ℃ CMOS bandgap voltage reference without requiring low threshold voltage device," IEEE J. Solid-State Circuits, vol.37, no.4, pp.525-530 , Apr. 2002. YH Cheng and CM Hu, "MOSFET Modeling & BSIM3 user's Guide," New York: Kluwer, 1999.

According to the circuit of FIG. 9, the power supply voltage _Vdd can be lowered. However, in an actual IC design, there is a problem that a mismatch between two R ₂ occurs due to the intersection. Furthermore, in the reference voltage circuit of FIG. 9, three circuit branches (the branches of M ₁ , M ₂ , and M ₃ ) are required. Thus, the manufacturing tolerances, even a high-gain amplifier AMP by _{V ds1 = V ds2 (V ds1} , V ds2 respectively _M 1, the drain of _{M 2} - source voltage) as could be _{realized, V ds3} is _{V ds1} And V _ds1 may not be exactly equal.

Therefore, an error voltage depending on the power supply voltage and temperature is generated in the reference voltage V _ref due to an error caused by these manufacturing tolerances.

Furthermore, since current flows through each of the three circuit branches, there is a problem that the total power consumption increases. Therefore, it is conceivable to increase R ₁ in order to reduce the total power consumption. In this case, from the equation (1), the values of R ₂ and R ₃ increase accordingly. Therefore, there arises a problem that the circuit mounting area increases.

  Accordingly, an object of the present invention is to provide a reference voltage circuit that can be used even with a power supply voltage of 1 V or less, has low power consumption, and can be designed with extremely low temperature dependence of the output voltage. There is.

  The first configuration of the reference voltage circuit according to the present invention provides at least two field-effect transistors (hereinafter referred to as “FETs”) operating in a weak inversion region, and applies a current bias to each of the FETs. The source-back gate junction of a current bias circuit and one of the FETs (hereinafter referred to as “specified FET”) is a reverse bias, and the source-back gate junction of another FET. Is a reverse bias shallower than the reverse bias of the specific FET, or zero bias or forward bias, and a difference voltage between the gate-source voltage of the specific FET and the gate-source voltage of any other FET It outputs as a reference voltage.

According to this configuration, the source-back gate junction of a specific FET is a reverse bias, and the source-back gate junction of another FET is a reverse bias, zero bias, or forward bias that is shallower than the reverse bias of the specific FET. Thus, it is possible to independently adjust the temperature dependence of the gate-source voltage of a specific FET and the temperature dependence of the gate-source voltage of another FET. This temperature dependence adjustment adjusts the size of each FET element. By adjusting the temperature dependence, the voltage difference between the gate-source voltage of a specific FET and the gate-source voltage of any other FET can be made constant at each temperature within the operating temperature range. It is. Therefore, if this difference voltage is output as the reference voltage V _ref , a minute reference voltage having no temperature dependency can be obtained.

  Further, since the difference voltage between the gate-source voltage between one specific FET and one other FET is used as the output voltage, the power consumption is small because it is composed of a pair of current branches. Also, the effect of errors caused by manufacturing tolerances is small. Also, since the difference voltage between the gate-source voltages of the two FETs is used as a reference voltage output, the temperature dependence is small and stable compared to a conventional reference voltage circuit using resistors, and the circuit mounting size is also reduced. be able to. It is also easy to generate a minute reference voltage.

  Here, as the “current bias circuit”, in addition to the constant current circuit, a current bias circuit including a normal resistor may be used. “Reverse bias is“ shallow ”” means that the reverse bias voltage applied to the pn junction is small. “Deep” in the reverse bias applied to the pn junction means that the reverse bias voltage is large.

  A second configuration of the reference voltage circuit according to the present invention is characterized in that, in the first configuration, the current bias circuit is a constant current circuit.

  In this way, by using a constant current circuit for the current bias circuit, fluctuations in the bias current to each FET due to the power supply voltage and temperature are reduced, thereby further reducing the power supply voltage dependency and temperature dependency of the reference voltage output. be able to.

  According to a third configuration of the reference voltage circuit of the present invention, in the first or second configuration, the first FET (M1) as the specific FET and the second FET (M2) as the other FET are used as the FET. ), The source-back gate junction of the second FET (M2) is zero bias, the source-back gate junction of the first FET (M1) is reverse-biased, and the first FET A difference voltage between the gate-source voltage of the FET (M1) and the gate-source voltage of the second FET (M2) is used as a reference voltage output.

  In this way, if two FETs, the first FET (M1) and the second FET (M2) are used, the circuit structure is symmetric when mounted on a chip, and the effects of crossing and noise errors during manufacturing are reduced. It can be made smaller. In addition, the source-back gate junction of the second FET (M2) is set to zero bias, which simplifies the circuit structure at the time of mounting, achieves downsizing and low power consumption, and stabilizes the back gate voltage. Can be made less susceptible to noise.

  According to a fourth configuration of the reference voltage circuit of the present invention, in the third configuration, the first FET (M1) and the second FET (M2) are diode-connected, and the first FET A first voltage drop circuit connected in series to the source of (M1), and the back gate of the second FET (M2) is connected to the source or drain of the first FET (M1). ) Is connected to the source of the back gate via the first voltage drop circuit.

  In this way, by connecting the back gate of the first FET (M1) to the source via the first voltage drop circuit, a reverse bias can be applied to the back gate-source junction.

  Here, the “voltage drop circuit” refers to a circuit that performs a voltage drop by a constant voltage, and includes a diode, a diode-connected transistor, and other general voltage drop circuits. Note that it is preferable to use a voltage drop circuit having a small voltage dependency of the drop voltage.

  According to a fifth configuration of the reference voltage circuit of the present invention, in the fourth configuration, the reference voltage circuit is connected in series to the source of the second FET (M2), and the source potential of the first FET (M1) A second voltage drop circuit for adjusting the source potential of the second FET (M2) to an equipotential is provided.

  This simplifies the circuit structure because the difference voltage between the drain voltage of the specific FET and the drain voltage of another FET may be output as the reference voltage.

  A sixth configuration of the reference voltage circuit according to the present invention is characterized in that, in the fourth or fifth configuration, the first or second voltage drop circuit is a diode or a diode-connected transistor.

  In this way, if a diode or a diode-connected transistor is used as the voltage drop circuit, the mounting area and power consumption of the voltage drop circuit are small and the drop voltage is stable, so that downsizing and low power consumption can be achieved. The stability of the voltage output can be improved.

  Here, the “transistor” includes various transistors such as a bipolar transistor, an FET, and an insulated gate bipolar transistor.

  A seventh configuration of the reference voltage circuit according to the present invention includes a voltage equalization circuit that equalizes the voltage of the source electrode of the specific FET and the voltage of the source electrode of the other FET in the first or second configuration. It is characterized by having.

  This makes it possible to output the difference voltage between the drain voltage of a specific FET and the drain voltage of another FET as a reference voltage, thereby simplifying the circuit structure and stabilizing the reference voltage output against fluctuations in power supply voltage and temperature. Can be improved.

  Here, as the “voltage equalization circuit”, a differential amplifier or the like that amplifies the difference voltage between the source voltage of a specific FET and the source voltage of another FET and negatively feeds back to the source current of each FET can be used. .

  As described above, according to the present invention, a reference voltage circuit that can be used even with a power supply voltage of 1 V or less, has low power consumption, and can be designed with extremely low temperature dependence of the output voltage. Can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

1 is a diagram illustrating a configuration of a reference voltage circuit according to a first embodiment of the present invention. The reference voltage circuit of this embodiment includes six p-channel MOSFETs (M ₁ , M ₂ , M ₃ , M ₄ , Md ₁ , Md ₂ ), one resistor R _b , and one differential amplifier AMP. It is comprised by. The differential amplifier AMP has two input terminals (+, −) and one output terminal, amplifies the differential voltage between the + side terminal and the − side terminal and outputs the amplified voltage to the output terminal. Further, MOSFETs Md ₁ and Md ₂ having the same size are used.

In the MOSFETs M ₃ and M ₄ , the power supply potential V _dd is applied to the source and the back gate, and the gates are connected to each other. The differential amplifier AMP is one of the two input terminals, the positive terminal is connected to the drain of the MOSFET M _3, - the side terminal connected to the drain of the MOSFET M _4, the output terminal MOSFET M _{3, M 4} Connected to the gate. These MOSFETs M ₃ and M ₄ constitute a current mirror circuit. This current mirror circuit creates a pair of current branches through which a constant ratio of current flows. In FIG. 1, the current branch passing through the channel of MOSFET M ₃ is current branch 1, and the current branch passing through the channel of MOSFET M ₄ is current branch 2.

A diode-connected MOSFET Md ₁ and a diode-connected MOSFET M ₁ are connected in this order to the current branch 1 between the drain of the MOSFET M ₃ and the ground plane so that the channel is in series. . The back gate of MOSFET Md ₁ is connected to its source electrode. Further, the back gate of the MOSFET M ₁ is connected to the source electrode of the MOSFET Md ₁ . That is, the back gate of the MOSFET M ₁ is a potential higher by _{V SgMd1} than its source voltage. Here, V _sgMd1 is a source-gate voltage of the MOSFET Md ₁ .

On the other hand, a diode-connected MOSFET Md ₂ and a diode-connected MOSFET M ₂ are connected in this order to the current branch 2 between the drain of the MOSFET M ₄ and the ground plane so that the channel is in series. Subsequently, a resistor _Rb is connected in series. The back gate of MOSFET Md ₂ is connected to its source electrode. The back gate MOSFET M ₂ is also connected to its source electrode.

The diode-connected MOSFETs M ₁ and M ₂ and the resistor R _b determine the current level of each current branch. The differential amplifier AMP generates two equal voltage input voltages (V _gM3 , V _gM4 ). Drain voltage of MOSFET M ₁ and MOSFET M ₂ is a reference voltage _{V ref.} The current _Ib is a current that flows through the resistor _Rb . In FIG. 1, a start-up circuit is omitted.

  The operation of the reference voltage circuit according to this embodiment configured as described above will be described below.

In this reference voltage circuit, MOSFETs M ₁ , M ₂ , Md ₁ and Md ₂ operate in the weak inversion region. In addition, the back gates of all MOSFETs except MOSFET M ₁ are set to the same potential as their sources, and there is no bias at the substrate (back gate) -source PN junction. On the other hand, the substrate-source PN junction of the MOSFET M ₁ is reverse-biased by the source-gate voltage V _{sgMd 1} of the MOSFET Md ₁ .

The current mirror circuit composed of the MOSFETs M ₃ and M ₄ supplies a constant ratio of current to the current branches 1 and 2, but the difference between the drain potentials of the MOSFETs M ₃ and M ₄ is amplified by the operation amplifier AMP. Thus, negative feedback is provided to the gates of the MOSFETs M ₃ and M ₄ . The gain of the operation amplifier AMP is very large, the potential difference is a large current flow is reduced MOSFET M _3, the difference in the drain potential of _{M 4} is generated in the channel of the MOSFET _{M 3,} M _4. As a result, the difference between the drain potentials of the MOSFETs M ₃ and M ₄ is stabilized in a state of approximately 0V. Therefore, it can be considered that the source voltages of the MOSFETs Md ₁ and Md ₂ are equal.

On the other hand, MOSFET _Md 1, Md ₂ because identical size, the source of the MOSFET Md ₁ - gate voltage _{V SgMd1} and source of the MOSFET Md ₂ - gate voltage _{V SgMd2} are equal. Therefore, the reference voltage V _ref is expressed by the following equation (2).

Here, V _sg1 and V _sg2 are the source-gate voltages of the MOSFETs M ₁ and M ₂ , respectively. When V _sg is expressed, the code is V _s -V _g , and when V _gs is expressed, the code is V _g -V _s . Others are the same.

In order to simplify the analysis, the source-gate voltage V _sgd1 of the MOSFET Md ₁ is approximated by the following equation (3) (see Non-Patent Document 4).

Here, _Vth is a threshold voltage. K _Md1 is a temperature coefficient of V _sgd1 and takes a negative value. T is a temperature, and T ₀ is a reference temperature selected as the center temperature of the operating temperature region.

On the other hand, in the weak inversion region, the relationship between the surface potential φ _s and the source-gate voltage V _sg1 of the MOSFET M ₁ is expressed by the following equation (4) (see Non-Patent Document 15).

Here, V _th1 is a threshold voltage, n (T) is a weak inversion slope factor, and φ _B is a bulk Fermi potential.

Further, the temperature model of the threshold voltage V _th1 is set as in the following equation (5) (see Non-Patent Document 15).

Here, V _th1 (T ₀ ) is the threshold voltage at temperature T ₀ , K _T1 is the temperature coefficient of the threshold voltage, K _T2 is the substrate bias coefficient of the temperature effect of V _th1 , and V _bs1 is the back gate-source of MOSFET M ₁ Voltage. In the circuit of FIG. 1, V _bs1 = V _sgd1 .

Also, φ _s (T) −2φ _B (T) is expressed as the following equation (6) as a function of temperature.

Further, n (T) ≈n (T ₀ ) may be set in the normal operating temperature range (see Non-Patent Document 4).

From the above equations (3), (4), (5), and (6), the temperature characteristic of V _{sg1 in} the reverse bias connection can be expressed by the following equation (7).

In Equation (7), the first term represents the temperature coefficient of MOSFET M ₁ without the substrate effect, and the second term represents the additional effect caused by the reverse bias substrate effect. Note that in the circuit of FIG. 1, the back gate-source junction of MOSFET M ₁ is reverse biased. Thus, the absolute value of the threshold voltage of the MOSFET M ₁ is increased by a reverse bias.

2, the source of MOSFET M ₁ in the with and without reverse bias - shows a gate voltage-temperature characteristics. In the graph of FIG. 2, the horizontal axis represents temperature, and the vertical axis represents V _sg . The difference between V _sg1 and reversely biased V _sg2 is the reference voltage V _ref .

As is well known, as the temperature increases, the threshold voltage of MOSFET M ₁ is increased, the voltage difference between the reverse bias connection without _{V sg1} and _{V sg2} also increases.

On the other hand, the difference voltage V _ref between V _sg1 and V _sg2 having the reverse bias connection is kept almost constant even when the temperature rises.

The second term (K _T2 / T ₀ ) [K _Md1 ((T / T ₀ ) −1) + V _sgd1 ] in equation (7) is positive and decreases with increasing temperature. Therefore, the temperature coefficient of the MOSFET M ₁ with a reverse bias connection is less than the temperature coefficient of the MOSFET M ₁ with no reverse bias connection. Accordingly, by appropriately selecting the size ratio of M ₁ to M _{2 and} the size ratio of M ₃ to M ₄ , the temperature coefficient of the reverse bias connected MOSFET M ₁ is the same as that of the MOSFET M ₂ without reverse bias connection. It can be modified to be similar to the temperature coefficient. Therefore, by using the reverse bias substrate effect, it is possible to obtain the reference voltage V _ref independent of temperature.

From the above, the advantages of the reference voltage circuit according to the present embodiment are summarized as follows.
(1) In order to obtain an appropriate magnitude of V _ref , the threshold voltage of the MOSFET can be changed using the substrate effect.
(2) The temperature coefficient of the MOSFET having a substrate effect can be appropriately changed by selecting the element size.
(3) The bias voltage between the source and the back gate is a dynamic voltage that varies with temperature.

  In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert).

  Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET).

Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

Furthermore, the two diode-connected MOSFETs Md ₁ and Md ₂ may be replaced with a diode.

FIG. 3 is a diagram illustrating the configuration of the reference voltage circuit according to the second embodiment of the invention. The reference voltage circuit of the present embodiment includes two resistors R ₀ and R _b , two diodes D ₁ and D ₂ , and two p-channel MOSFETs M ₁ and M ₂ . Here, the diodes D ₁ and D ₂ may be diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 when mounted on a semiconductor chip. The MOSFETs M ₁ and M ₂ operate in the weak inversion region.

The power supply voltage V _dd is applied to one end of the resistor R ₀ , and the other end is commonly connected to the anode side of the diodes D ₁ and D ₂ . Between the cathode and the ground potential of the diode _{D 1,} channel MOSFET M ₁ is connected. MOSFET M ₁ has its gate connected to its drain and its back gate connected to the anode electrode of diode D ₁ .

On the other hand, between the cathode and the ground potential of the diode _{D 2,} the channel of MOSFET M ₂ and resistor _{R b} is connected in this order. MOSFET M ₁ has its gate connected to its drain and its back gate connected to its source electrode.

In this circuit, as in Example 1, the voltage between the drain of the MOSFET M ₁ and MOSFET M ₂ is a reference voltage _{V ref.}

In this embodiment, instead of the low voltage constant current sources (M ₃ , M ₄ , AMP) of FIG. 1, a resistor R ₀ connected to a power source is used as a current bias circuit, and MOSFETs Md ₁ , Md _The only difference is that ₂ is replaced by D ₁ and D ₂ , and the rest is the same as in the first embodiment. In this case also, diodes of the same size are used as the diodes D ₁ and D ₂ in order to make the source potentials of the MOSFETs M ₁ and M ₂ equal.

  Since the operation principle of the circuit of this embodiment is the same as that of the first embodiment, detailed description thereof is omitted.

  If the configuration of this embodiment is used, the configuration is simpler than that of the circuit of Embodiment 1, so that the circuit mounting area can be reduced and the power consumption can be reduced. On the other hand, the stability against fluctuations in the power supply voltage is inferior to that in the first embodiment.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

FIG. 4 is a diagram illustrating the configuration of the reference voltage circuit according to the third embodiment. The reference voltage circuit of the present embodiment includes three resistors R ₁ , R ₂ , R _b , a differential amplifier AMP, two diodes D ₁ , D ₂ , and two MOSFETs M ₁ , M ₂ . MOSFETs M ₁ and M ₂ operate in the weak inversion region.

  The reference voltage circuit of this embodiment is different from the second embodiment only in the current bias circuit portion, and the other portions are the same as those in the second embodiment, so that the description thereof is omitted.

In this embodiment, a current bias circuit is configured by using the differential amplifier AMP and the resistors R ₁ and R ₂ . The differential amplifier AMP amplifies the difference between the anode voltages of the diodes D ₁ and D ₂ and negatively feeds back the amplified voltage to the node p to which the resistors R ₁ and R ₂ are commonly connected. Further, it is assumed that the gain of the differential amplifier AMP is sufficiently large.

In this circuit, when the difference between the anode voltages of the diodes D ₁ and D ₂ becomes a finite value (a value other than 0), the difference is amplified and a large voltage is applied to the common node p of the resistors R ₁ and R ₂ . As a result, the anode voltages of the diodes D ₁ and D ₂ are raised, a large current flows through the diodes D ₁ and D _2, and the difference between the anode voltages is suppressed. Therefore, the difference between the anode voltages of the diodes D ₁ and D ₂ is always set to near zero.

  Other voltage generation operations are the same as in the first and second embodiments.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel. Further, when the diodes D ₁ and D ₂ are mounted on a semiconductor chip, diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 may be used.

FIG. 5 is a diagram illustrating a configuration of a reference voltage circuit according to the fourth embodiment. The reference voltage circuit of the present embodiment includes four MOSFETs M ₁ , M ₂ , M ₃ , M ₄ , two diodes D ₁ , D ₂ , a differential amplifier AMP, and a resistor R _b . The two diodes D ₁ and D ₂ can be replaced with diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 when mounted on a semiconductor chip. The MOSFETs M ₁ and M ₂ operate in the weak inversion region.

Comparing the reference voltage circuit of the present embodiment with the reference circuit of the first embodiment, the MOSFET Md ₁ and Md ₂ are replaced with diodes D ₁ and D ₂ , and the two input terminals of the differential amplifier AMP are MOSFETs The only difference is that they are connected to the sources of M ₁ and M ₂ , respectively. As a result, the source potentials of the _two MOSFETs M ₁ and M ₂ are set to be approximately equal.

  Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

FIG. 6 is a diagram illustrating a configuration of a reference voltage circuit according to the fifth embodiment. The reference voltage circuit of this embodiment includes four MOSFETs M ₁ , M ₂ , M ₃ , M ₄ , one diode D ₁ , a differential amplifier AMP, and a resistor R _b . The two diodes D ₁ and D ₂ can be replaced with diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 when mounted on a semiconductor chip. The MOSFETs M ₁ and M ₂ operate in the weak inversion region.

When comparing the reference voltage circuit of the present embodiment with the reference circuit of the first embodiment, the MOSFET Md ₁ is replaced by the diode D _1, and the two input terminals of the differential amplifier AMP are used as the sources of the MOSFETs M ₁ and M ₂ . They are different from each other in that they are connected and the MOSFET Md ₂ is omitted.

As described in the first embodiment, in this circuit, the current bias circuit MOSFETs M ₃ and M ₄ supply a constant ratio of current to the channels of the MOSFETs M ₁ and M ₂ . Further, the source potentials of the MOSFETs M ₁ and M ₂ are kept substantially equal by the differential amplifier AMP.

Diode _D 1 is the back gate MOSFET M ₁ - have been used to a reverse bias junction between the source.

  Also with this configuration, a low voltage and low power consumption reference voltage circuit with stable temperature characteristics can be obtained as in the first embodiment.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

FIG. 7 is a diagram illustrating a configuration of a reference voltage circuit according to the sixth embodiment. The reference voltage circuit of this embodiment includes four MOSFETs M ₁ , M ₂ , M ₃ , M ₄ , four diodes D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ , a differential amplifier AMP, and a resistor R _b . ing. The four diodes D ₁₁ , D ₁₂ , D ₂₁ , and D ₂₂ can be replaced with diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 when mounted on a semiconductor chip. The MOSFETs M ₁ and M ₂ operate in the weak inversion region.

Comparing the reference voltage circuit of this example with the reference circuit of Example 1, the points where MOSFETs Md ₁ and Md ₂ are replaced by diodes D ₁₁ and D ₂₁ , and diodes D ₁₂ and D ₂₂ are diodes D ₁₁ , respectively. between the cathode and the source of MOSFET M _1, point newly added between the cathode and the source of MOSFET M ₂ of the diode _{D 21,} the source electrode of its own back-gate MOSFET M ₂ via the diode _{D 22} The connection is different.

In this configuration, the back gate MOSFET M ₂ - joined by a shallow reverse bias the junction between the source, back gate MOSFET M ₁ - so that the deeper reverse bias is applied to the junction between the source. Thus, by applying a reverse bias to both of the MOSFETs M ₁ and M ₂ and changing the depth of the bias, a reference voltage circuit having a very small temperature dependency of the reference voltage can be obtained as in the first embodiment. Can be designed.

  However, the reference voltage circuit according to the present embodiment is more disadvantageous than the circuit according to the first embodiment in terms of low voltage and low power consumption because one extra diode is added compared to the first embodiment.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

FIG. 8 is a diagram illustrating a configuration of a reference voltage circuit according to the seventh embodiment. The reference voltage circuit of the present embodiment includes four MOSFETs M ₁ , M ₂ , M ₃ , M ₄ , two diodes D ₁ , D ₂ , a differential amplifier AMP, and a resistor R _b . The two diodes D ₁ and D ₂ can be replaced with diode-connected MOSFETs such as Md ₁ and Md _{2 in} FIG. 1 when mounted on a semiconductor chip. The MOSFETs M ₁ and M ₂ operate in the weak inversion region.

Comparing the reference voltage circuit of this example with the reference circuit of Example 1, the points where MOSFETs Md ₁ and Md ₂ are replaced by diodes D ₁₁ and D ₂₁ , and the back gate of MOSFET M ₂ serves as its own drain electrode. The connection is different.

In this case, the back gate of the MOSFET M ₁ - between the source junction reverse bias is applied, the back gate of the MOSFET M ₂ - a forward bias is applied between the source junction.

  Even with this configuration, a low voltage and low power consumption reference voltage circuit with stable temperature characteristics can be obtained as in the first embodiment.

In this embodiment, zero is shown in which a reference voltage circuit is configured using a p-channel MOSFET, but a circuit similar to this embodiment can be configured using an n-channel MOSFET (however, the voltage polarity is Invert). Further, instead of each MOSFET, it can generally be replaced with various field effect transistors (such as MISFET). Also, the resistor _Rb can be replaced with a resistor using a MOSFET channel.

It is a figure showing the structure of the reference voltage circuit which concerns on Example 1 of this invention. The source of MOSFET M ₁ in the with and without reverse bias - is a graph showing a gate voltage-temperature characteristics. It is a figure showing the structure of the reference voltage circuit which concerns on Example 2 of this invention. FIG. 10 is a diagram illustrating a configuration of a reference voltage circuit according to a third embodiment. FIG. 10 is a diagram illustrating a configuration of a reference voltage circuit according to a fourth embodiment. FIG. 10 is a diagram illustrating a configuration of a reference voltage circuit according to a fifth embodiment. FIG. 10 is a diagram illustrating a configuration of a reference voltage circuit according to a sixth embodiment. FIG. 10 is a diagram illustrating a configuration of a reference voltage circuit according to a seventh embodiment. Reference voltage circuit described in Non-Patent Document 12.

Explanation of symbols

_{M 1, M 2, M 3} , M 4, Md 1, Md 2 MOSFET
_{D 1, D 2, D 11} , D 12, D 21, D 22 diodes _{R b, R 0, R 1} , R 2 resistor AMP differential amplifier

Claims (7)

At least two field effect transistors (hereinafter referred to as “FETs”) operating in the weak inversion region;
A current bias circuit for applying a current bias to each FET;
Among each of the FETs, a source-back gate junction of one FET (hereinafter referred to as “specific FET”) is set as a reverse bias,
The source-back gate junction of another FET is a reverse bias shallower than the reverse bias of the specific FET, or a zero bias or a forward bias.
A reference voltage circuit characterized in that a differential voltage between a gate-source voltage of the specific FET and a gate-source voltage of any other FET is output as a reference voltage.   The reference voltage circuit according to claim 1, wherein the current bias circuit is a constant current circuit. The FET includes a first FET (M1) that is the specific FET and a second FET (M2) that is the other FET,
The source-back gate junction of the second FET (M2) is zero bias, the source-back gate junction of the first FET (M1) is reverse biased,
The differential voltage between the gate-source voltage of the first FET (M1) and the gate-source voltage of the second FET (M2) is used as a reference voltage output. Reference voltage circuit. The first FET (M1) and the second FET (M2) are diode-connected,
A first voltage drop circuit connected in series to a source of the first FET (M1);
The back gate of the second FET (M2) is connected to the source or drain thereof,
4. The reference voltage circuit according to claim 3, wherein the back gate of the first FET (M1) is connected to the source of the first FET (M1) via the first voltage drop circuit.   A second voltage drop connected in series to the source of the second FET (M2) and adjusting the source potential of the first FET (M1) and the source potential of the second FET (M2) to be equipotential The reference voltage circuit according to claim 4, further comprising a circuit.   6. The reference voltage circuit according to claim 4, wherein the first or second voltage drop circuit is a diode or a diode-connected transistor.   3. The reference voltage circuit according to claim 1, further comprising a voltage equalization circuit for equalizing the voltage of the source electrode of the specific FET and the voltage of the source electrode of the other FET.

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