JP4761361B2 - Reference circuit - Google Patents

Description

  The present invention relates to a reference circuit technique for generating a reference voltage or a reference current, and more particularly, to a reference circuit technique that operates at a constant voltage and low power consumption and can suppress a change in a reference voltage or a reference current due to temperature. .

  One of the promising research fields in microelectronics is the development of an ultra-low power consumption analog LSI composed of a subthreshold MOSFET. In order to configure such an LSI, it is first necessary to develop a voltage / current reference circuit that operates with ultra-low power loss.

  On the other hand, in the near future, it is believed that a “ubiquitous” network system will be developed. In such a system, many sensing LSIs and smart sensors are required. These sensors must be operated from an extremely low power source because they must obtain the necessary energy from environmental energy such as sunlight, weak radio waves, and vibration-based energy.

  In addition, with the recent miniaturization and low power consumption of the CMOS process, the power supply voltage of the CMOS circuit is expected to drop to about 1.0 V within the past few years.

  By the way, a band gap reference circuit widely used conventionally generates a voltage of 1.2 V or more. Therefore, when the power supply voltage is less than 1V, there is a problem that the performance of the conventional bandgap reference deteriorates. Therefore, a new voltage / current reference circuit technology is required to realize a power supply circuit that operates with the low voltage and low power consumption as described above.

  Non-patent documents 1 to 4 and patent documents 1 to 3 are known as voltage / current reference circuit technologies that operate with low voltage and low power consumption.

  Non-Patent Document 1 reports many current reference circuits that operate in a strong inversion region. Here, a beta-multiplier self-biasing circuit is widely used as a current reference circuit for a MOSFET.

  Patent Documents 1 to 3 describe a bandgap reference voltage source that operates with low voltage and low power consumption. FIG. 9 shows a circuit configuration of the band gap reference voltage source.

This circuit has the same configuration as that of a normal band gap reference voltage source except that MOSFETs T1 and T2 are connected between the back gate and the gate. Therefore, in this circuit, the output reference voltage V _out is obtained as a voltage between the terminal 107 and the terminal 105.

The output reference voltage _Vout includes a voltage between the resistors RS and a source-gate voltage of the MOSFET T1, or a voltage between the resistors RS, a voltage between the resistors RRF, and a source-gate voltage of the MOSFET T2. Therefore, the output reference voltage _Vout is expressed by the following equation.

The output reference voltage _Vout of the conventional bandgap reference circuit is 1.2V or more. On the other hand, in the circuit of FIG. 9, the MOSFETs T1 and T2 are connected between the back gate and the gate in order to lower the source-gate voltage of the MOSFETs T1 and T2. As a result, the output reference voltage _Vout is lowered, and operation can be performed with low voltage and low power consumption.

The main operating principle of this circuit is the same as that of a conventional bandgap reference circuit.
US Pat. No. 5,942,876 International Publication No. 98/21635 Pamphlet JP 2000-503443 A DA Johns and K. Martin, "Analog Integrated Circuits Design," John Wiley & Sons, 1997. HJ Oguey and D. Aebischer, "CMOS current reference without resistance," IEEE J. Solid-State Circuits, vol.32, no.7, pp.1132-1135, July 1997. AE Buck, CL Mcdonald, SH Lewis, and TR Viswanathan, "A CMOS bandgap reference without resistors," IEEE J. Solid-State Circuits, vol.37, no.1, pp.81-83, Jan. 2002. T. Hirose, T. Matsuoka, K. Taniguchi, T. Asai, and Y. Amemiya, "Ultralow-power current reference circuit with low temperature dependence," IEICE TRANS. ELECTRON., Vol.e88-c, no.6, June 2005.

  The current reference circuit described in Non-Patent Document 1 has a problem that the reference current increases as the temperature rises. Similarly, the current reference circuit (see Non-Patent Document 2) reported by Oguey and Aebischer in 1997 also has a problem that the reference current increases as the temperature rises.

  The circuit proposed by Buck, Mcdonald, Lewis, and Viswanathan in 2002 (see Non-Patent Document 3) has a problem that it cannot be used in the operating region at low voltage and low power consumption.

  The circuit proposed by Hirose et al. In 2005 (see Non-Patent Document 4) is similar to the circuit of Buck et al. Also, the temperature characteristics are not very good (± 4%) under the condition that the minimum power supply voltage is 1.5V dc in 0.25μm technology.

In the band gap reference circuits described in Patent Documents 1 to 3 (see FIG. 9), the currents flowing through the resistors RRF and RS increase in proportion to the temperature rise. That is, it has a positive temperature coefficient. On the other hand, the temperature coefficient of the source-gate voltage V _sg of the MOSFETs T1 and T2 is negative. Therefore, in order to cancel _out the temperature coefficient of _Vout , two resistors are required corresponding to the MOSFETs T1 and T2, but there is no such resistance in the circuit of FIG. Therefore, the bandgap reference circuit of FIG. 9 also has a problem that the reference current changes as the temperature rises.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a constant current / constant voltage reference circuit that operates with a low voltage and low power consumption and that can suppress fluctuations in the reference voltage and reference current with respect to temperature.

  A reference circuit according to the present invention is characterized in that, in a reference circuit including a current mirror circuit and a MOS peaking current source, the back gate of the MOSFET on the output side of the MOS peaking current source is connected to the gate side of the MOSFET. And

  According to this configuration, only the MOSFET on the output side of the MOS peaking current source is connected between the back gate and the gate in order to change the threshold voltage. This MOSFET operates in the subthreshold region over a wide temperature range.

  And the difference between the source-gate voltage of the other MOSFET that is not connected between the back gate and the gate in the MOS peaking current source and the source-gate voltage of the MOSFET that is connected between the back gate and the gate is: Used to generate voltage and current references with very low temperature coefficients. In the peaking current source circuit, it is known that the difference between the source and gate voltages increases as the temperature rises because of the MOSFET in which the back gate and gate are not connected. Therefore, in this circuit, the temperature dependence of the output reference voltage can be canceled by using only one resistor connected in series to the MOSFET that is not connected between the back gate and the gate.

  As described above, according to the present invention, it is possible to provide a reference circuit that operates with a power supply voltage of a minimum of 0.8 V in the standard CMOS 0.35 μm digital technology. Further, the power loss of the entire circuit can be 1 μW or less. Also, no analog process options are required for circuit configuration.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

First, for comparison, a conventional peaking current source circuit is shown in FIG. The MOSFETs M1, M2 and the resistor Rb constitute a peaking current source. MOSFETs M1 and M2 are designed to operate in the subthreshold region as required by a low power supply voltage, and can achieve low power consumption. However, in this circuit, the output reference currents I _ref1 and I _ref2 also increase in proportion to the temperature rise.

  FIG. 2 is a diagram illustrating the configuration of the reference circuit according to the first embodiment of the invention. The operation principle of this circuit is as follows.

In FIG. 2, the reference circuit is composed of two parts, a current mirror circuit 1 and a peaking current source 2. The current mirror circuit 1 is a normal one and includes MOSFETs MC1, MC2, and MC3. The peaking current source 2 includes MOSFETs M1 and M2 .

  MOSFETs M1 and M2 operate in the subthreshold region. The back gate terminal (substrate terminal) of the MOSFET M2 is connected to the power supply Vdd as usual. However, the back gate terminal of MOSFET M1 is connected to the gate terminal. A voltage reference and a current reference are generated in the resistor Rb. Reference currents Iref1 and Iref2 equivalent to the reference current Iref are connected in parallel with the MOSFET M1, connected in parallel with the drain terminal of the MOSFET M3 connected between the back gate and the gate, and the MOSFET MC1 of the current mirror circuit. Generated at the drain terminal of the MOSFET MC3.

As is well known, the threshold voltage V _TH of a MOSFET device is expressed as:

ここで、Φ_ｍｓはゲート・基板間の接合電位差；
Φは関連するバンドの曲がり（band bending）（フラットバンド電圧）；
Ｖ_Ｔ（Ｎ_ｉ）は深さｄ_ｉのチャネル・インプラント（channel implant）Ｎ_ｉに起因する閾値シフト；
γ（Ｎ_ｓ，ｔ_ｏｘ，Ｌ，Ｗ）は、基板ドーピングＮ_ｓ，ゲート絶縁膜厚ｔ_ｏｘ，チャネル長Ｌ，及びチャネル幅Ｗに依存する基板バックバイアス係数（substrate backbias factor）；
Ｖ_ＳＢはソース・基板間バイアス；
Ｖ_ｏは打ち込み閾値シフトに起因する修正項である。

Where Φ _ms is the gate-substrate junction potential difference;
Φ is the associated band bending (flat band voltage);
V _T (N _i ) is a threshold shift due to a channel implant N _i of depth d _i ;
γ (N _s , t _ox , L, W) is a substrate backbias factor that depends on the substrate doping N _s , gate insulating film thickness t _ox , channel length L, and channel width W;
V _SB is the source-substrate bias;
V _o is a correction term resulting from the driving threshold shift.

  here,

Therefore, V _ref is expressed as follows.

V _sb1 = V _gs1 , V _sb2 = 0,

とおくと、

After all,

From the above equation (6), the factors that may cause the temperature dependence of the voltage reference V _ref are V _gs1 , Φ, and V _T. Therefore, by using MOSFETs M1 and M2 having different size ratios, the temperature dependence of V _ref can be made almost zero.

In the circuit of FIG. 2, the connection position of the resistor Rb may be between the power supply _Vdd and the source terminal of the MOSFET M1.

〔simulation result〕
FIG. 3 shows simulation results regarding the temperature dependence of the voltage reference of the circuit of FIG. The horizontal axis represents temperature, and the vertical axis represents the voltage reference V _ref . The scale on the horizontal axis is −40 ° C. to 100 ° C., and the scale on the vertical axis is 225.8 to 227.6 mV.

FIG. 4 shows simulation results for the temperature dependence of the current reference of the circuit of FIG. The horizontal axis represents temperature, and the vertical axis represents the current reference I _ref . The scale on the horizontal axis is −40 ° C. to 100 ° C., and the scale on the vertical axis is 451.4 to 455.4 nA.

As can be seen from the simulation results, according to the reference circuit of this embodiment, the temperature dependence of the voltage reference V _ref and the current reference I _ref can be made almost zero.

FIG. 5 is a diagram illustrating a configuration of a reference circuit according to the second embodiment of the present invention. Even with such a reference circuit, the temperature dependence of the output current / voltage references I _ref and V _ref can be made almost zero.

〔simulation result〕
FIG. 6 shows simulation results regarding the temperature dependence of the voltage reference of the circuit of FIG. The horizontal axis represents temperature, and the vertical axis represents the voltage reference V _ref . The scale on the horizontal axis is −40 ° C. to 100 ° C., and the scale on the vertical axis is 245.8 to 247.1 mV.

FIG. 7 shows simulation results regarding the temperature dependence of the current reference of the circuit of FIG. The horizontal axis represents temperature, and the vertical axis represents the current reference I _ref . The scale of the horizontal axis is −40 ° C. to 100 ° C., and the scale of the vertical axis is 22.83 to 22.7 nA.

As can be seen from the simulation results, the temperature dependence of the voltage reference V _ref and the current reference I _ref can be made almost zero even by the reference circuit of this embodiment.

FIG. 8 shows a simulation result regarding the operating voltage of the current reference of the circuit of FIG. The horizontal axis represents the power supply voltage _Vdd , and the vertical axis represents the voltage reference _Vref . The scale on the horizontal axis is −0.8 to 3.3 Vdc, and the scale on the vertical axis is 245 to 246 mV.

As can be seen from the simulation results, the reference circuit of this example operates normally when the power supply voltage V _dd is about 800 mV, and can be operated at an extremely low power supply voltage.

It is a circuit diagram which shows the conventional peaking current source circuit. 1 is a diagram illustrating a configuration of a reference circuit according to Embodiment 1 of the present invention. It is a figure which shows the simulation result regarding the temperature dependence of the voltage reference of the circuit of FIG. It is a figure which shows the simulation result regarding the temperature dependence of the current reference of the circuit of FIG. It is a figure showing the structure of the reference circuit which concerns on Example 2 of this invention. It is a figure which shows the simulation result regarding the temperature dependence of the voltage reference of the circuit of FIG. It is a figure which shows the simulation result regarding the temperature dependence of the current reference of the circuit of FIG. It is a figure which shows the simulation result regarding the operating voltage of the current reference of the circuit of FIG. It is a circuit diagram which shows the circuit structure of the band gap reference voltage source of patent documents 1-3.

Explanation of symbols

1 Current mirror circuit 2 Peaking current source M1, M2, M3 MOSFET
MC1, MC2, MC3 MOSFET
Rb resistance

Claims (1)

A current mirror circuit or two MOSFETs are provided, the gates of the MOSFETs are connected to each other, the sources of the MOSFETs are connected to a common power source, and the drains of the MOSFETs are connected to two input terminals of the differential amplifier. A current supply circuit configured to connect to each other and connect the output terminal of the differential amplifier to the gate of each MOSFET;
In a reference circuit comprising a MOS peaking current source,
Said MOS peaking current source of the current output side of the MOSFET as the back gate of the (M1) connected to the gate side of the MOSFET (M1), the MOS peaking current source other back gates the MOSFET of the MOSFET (M2) of (M2 ) Is connected to the source side of the reference circuit.

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