JP2007251507A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit capable of substantially extending a common mode input voltage range at an input stage. <P>SOLUTION: First and second P-channel MOS transistors 1, 2 provided to execute a differential amplification operation configure the input stage, the differential amplifier circuit is provided with first and second threshold voltage control circuits 101a, 101b configured to control a back gate level of the transistors 1, 2 in response to a level of an input signal applied to respective gates of the two transistors 1, 2, and the common mode input voltage range for the first and second transistors configuring the input stage is extended. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit, and more particularly to a circuit in which an in-phase input voltage range is expanded.

Conventionally, in an operational amplifier configured using C-MOS semiconductor elements (hereinafter referred to as “C-MOS operational amplifier”), the threshold voltage Vth of the P-channel MOS transistor in the input stage determines the common-mode input voltage range. It is already known to be one of the following.
Normally, the threshold voltage of a transistor used in the input stage of a C-MOS operational amplifier has two types of threshold voltage VTH0 at the time of zero bias determined by its use process and threshold voltage VTH1 at the time of substrate bias determined by the back gate potential VBG. It is determined based on the data. Conventionally, the back gate voltage VBG, which is one factor determining VTH1 at the time of substrate bias, is conventionally fixed between the source potential ≦ VBG ≦ power supply voltage, and accordingly, the threshold voltage VTH1 at the time of substrate bias. Therefore, the common-mode input voltage range is constant at VTH1 regardless of the input signal.

FIGS. 9 and 10 show circuit configuration examples of such a conventional C-MOS operational amplifier.
That is, in the differential amplifier circuit shown in FIG. 9, the input stage is composed of two P-channel MOS transistors Tr15 and Tr16, and the back gates of both transistors Tr15 and Tr16 are both connected to the source, The back gate potential is fixed to the source potential.

  In the differential amplifier circuit shown in FIG. 10, the back gates of the two P-channel MOS transistors Tr15 and Tr16 constituting the input stage are connected to the power supply line, and the back gate potential is fixed to the power supply voltage V +. It becomes the composition.

On the other hand, when the input stage of the C-MOS operational amplifier is conventionally composed of N-channel MOS transistors, the back gate voltage VBG, which is one factor that determines VTH1 at the time of substrate bias, is the minimum potential ≦ VBG ≦ source voltage. Was set to be.
FIG. 11 and FIG. 12 show an example of setting the potential of the back gate in the C-MOS operational amplifier in which the input stage is composed of N-channel MOS transistors in this way.
That is, in the differential amplifier circuit shown in FIG. 11, the back gates of the two N-channel MOS transistors Tr17 and Tr18 constituting the input stage are connected to the source, and the back gate potential is fixed to the source potential. It is configured as follows.
In the differential amplifier circuit shown in FIG. 12, the back gates of the N-channel MOS transistors Tr17 and Tr18 are connected to the ground, and the back gate potential is fixed to the lowest potential, that is, the ground potential. It has been made.

  As described above, in the conventional C-MOS operational amplifier, the back gate potential VBG of the transistor constituting the input stage satisfies the source potential ≦ VBG ≦ the power supply voltage or the lowest potential ≦ VBG ≦ the source voltage. As a result, the threshold voltage at the time of substrate bias of the transistors constituting the input stage is also fixed, the common-mode input voltage range is constant regardless of the input signal, and the dynamic range of the input signal is not sufficient.

  As a measure for solving such a problem, for example, a source follower circuit is provided as an input buffer circuit, and an input signal is applied to two transistors constituting the input stage of the differential amplifier via the source follower circuit. Have been proposed (see, for example, Patent Document 1).

JP-A-8-37431 (page 2-5, FIGS. 1-5)

  However, in the circuit disclosed in the above publication, the back gate potentials of the two transistors constituting the input stage of the differential amplifier circuit are still fixed, and the input stage is constituted by the source follower circuit as the input buffer circuit. The input range of the two transistors is only apparently expanded, and the original input range of the two transistors constituting the input stage is not essentially expanded.

The present invention has been made in view of the above circumstances, and provides a differential amplifier circuit capable of further expanding the common-mode input voltage range of the input stage as compared with the related art.
Another object of the present invention is to provide a differential amplifier circuit capable of essentially expanding the common-mode input voltage range in the input stage.

In order to achieve the above object of the present invention, a differential amplifier circuit according to the present invention includes:
A differential amplifier circuit in which an input stage is configured by two MOS transistors provided to perform a differential amplification operation,
For each of the two MOS transistors, a threshold voltage control circuit that controls the back gate potential of the MOS transistor according to the level of the input signal applied to the respective gate and enables the common-mode input voltage range to be expanded. It is provided.
In this configuration, the threshold voltage control circuit is provided by push-pull connection between the first P-channel MOS transistor for control circuit and the second N-channel MOS transistor for control circuit, and the respective gates are connected to each other. While the input signal is applied, the drains are connected to each other, and the third P-channel MOS transistor for the control circuit and the fourth N-channel MOS transistor for the control circuit, which are also connected by push-pull connection, are connected to each other. The drains of the third P-channel MOS transistor for control circuit and the drain of the fourth N-channel MOS transistor for control circuit are connected to each other and connected to the gate of the fifth P-channel MOS transistor for control circuit. Connected to
While the power supply voltage is applied to the source and back gate of each of the first, third and fifth P channel MOS transistors for the control circuit, the source of the second and fourth N channel MOS transistors for the control circuit A constant current source is provided between the
The drain of the fifth P-channel MOS transistor for the control circuit is connected to the back gate of the MOS transistor constituting the input stage of the differential amplifier circuit, and the input stage of the differential amplifier circuit is connected via a resistor. What is connected to the source of the said MOS transistor to comprise is suitable.
The threshold voltage control circuit is provided by push-pull connection of a first P-channel MOS transistor for control circuit and a second N-channel MOS transistor for control circuit, and each gate is connected to each other to input signal. Is applied to the drain, and the drain is connected to each other, and the third P-channel MOS transistor for the control circuit and the fourth N-channel MOS transistor for the control circuit, which are also provided in a push-pull connection, are connected to each other. The drains of the third P-channel MOS transistor for control circuit and the fourth N-channel MOS transistor for control circuit are connected to each other and connected to the gate of the fifth P-channel MOS transistor for control circuit. And
While a power supply voltage is applied to the source of each of the first and third P channel MOS transistors for the control circuit and the back gate of the first, third and fifth P channel MOS transistors for the control circuit, The sources and back gates of the second and fourth N-channel MOS transistors for the control circuit are connected to each other, and a constant current source is provided between the connection point and the ground.
A voltage higher than the power supply voltage is applied to the source of the fifth P-channel MOS transistor for the control circuit, while the drain is connected to the back gate of the MOS transistor constituting the input stage of the differential amplifier circuit. In addition, the one connected to the ground through a resistor is also preferable.

  According to the present invention, the back gate potential is changed in accordance with the magnitude of the input signal so that the threshold voltage of the MOS transistor at the time of substrate bias can be changed. Unlike this, it is possible to provide a differential amplifier circuit that can be enlarged essentially, not apparently, and can handle a larger in-phase signal.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first basic configuration example of the differential amplifier circuit according to the embodiment of the present invention will be described with reference to FIG.
FIG. 1 particularly shows a basic configuration example in an input stage of a differential amplifier circuit. The input stage includes first and second transistors connected in a differential operation (in FIG. 1, And "Tr1" and "Tr2") are provided corresponding to the first and second transistors 1 and 2, respectively, and the threshold value of the transistor according to the magnitude of the input signal will be described in detail later. First and second threshold voltage control circuits for controlling voltage (in FIG. 1, "VTHCONT (1)" and "VTHCONT (2)" respectively) 101a and 101b are configured as main components. It has become.

Hereinafter, the circuit configuration will be specifically described.
First, P-channel MOS transistors are used for the first and second transistors 1 and 2, and the sources of the first and second transistors 1 and 2 are connected to each other and at the power supply voltage V +. It is connected to a first constant current source 21 that operates and outputs a constant current I1.
In addition, the drain of the first transistor 1 is connected to the first resistor 25 (denoted as “R1” in FIG. 1), and the drain of the second transistor 2 is connected to the second resistor (in FIG. 1). Are each connected to the ground via the R 26) and connected to the input stage of the subsequent amplifier 11 (shown as “A 1” in FIG. 1).
The gate of the first transistor 1 is a first differential input terminal (indicated as “IN1” in FIG. 1) 31 and the gate of the second transistor 2 is a second differential input terminal (shown in FIG. 1). In FIG. 1, they are connected to each other, and an input signal is applied from the outside.

  The first threshold voltage control circuit 101a has an input stage connected to the gate of the first transistor 1 and an output stage connected to the back gate of the first transistor 1, while the second threshold voltage control circuit The circuit 101 b has an input stage connected to the gate of the second transistor 2 and an output stage connected to the back gate of the second transistor 2. These first and second threshold voltage control circuits 101a and 101b basically have the same circuit configuration.

  In this configuration, when the level of the input signal applied to the first and second differential input terminals 31 and 32 is high, the first and second threshold voltage control circuits 101a and 101b cause the first and second transistors. On the other hand, when the level of the input signal is low while the back gate potential of 1 and 2 is controlled to be low, the first and second transistors 1 and 2 are controlled by the first and second threshold voltage control circuits 101a and 101b. As the back gate potential of the first and second transistors 1 and 2 is controlled accordingly, the control common-mode input voltage range is secured wider than in the conventional case. ing.

Next, a second basic configuration example of the differential amplifier circuit according to the embodiment of the present invention will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, different points will be mainly described.
This second basic configuration example is different from the first basic configuration example shown in FIG. 1 in place of the so-called active load instead of the resistive load provided on the drain side of the first and second transistors 1 and 2. The difference is that the load is provided.

More specifically, first, the active load is constructed by connecting the third and fourth transistors 3 and 4 to the drain side of the first and second transistors 1 and 2 as described below. It is provided as you do.
That is, N-channel MOS transistors are used for the third and fourth transistors (represented as “Tr3” and “Tr4” in FIG. 2), respectively, and the drain of the third transistor 3 is The gates of the third and fourth transistors 3 and 4 are connected to the drain of the first transistor 1 together with the gates thereof. On the other hand, the drain of the fourth transistor 4 is connected to the drain of the second transistor 2 and to the input stage of the subsequent amplifier 12 (denoted as “A2” in FIG. 2).
Further, the sources and back gates of the third and fourth transistors 3 and 4 are both connected to the ground.

  Also in such a configuration, the threshold voltages of the first and second transistors 1 and 2 are controlled by the corresponding first and second threshold voltage control circuits 101a and 101b, respectively, and the common-mode input voltage range is expanded. This is basically the same as the basic configuration example shown in FIG.

Next, specific circuit examples of the first and second threshold voltage control circuits 101a and 101b will be described with reference to FIGS. In the following description, the first threshold voltage control circuit 101a and the second threshold voltage control circuit 101b are referred to as the threshold voltage control circuit 101 when it is not necessary to distinguish them.
First, a first specific circuit configuration example of the threshold voltage control circuit will be described with reference to FIG.
In the first specific circuit configuration example, the threshold voltage control circuit 101 includes fifth, seventh, and ninth transistors that are P-channel MOS transistors (in FIG. 3, “Tr5”, “Tr7”, “Tr9”, respectively). 5), 7 and 9, N-channel MOS transistors 6 and 8 (referred to as “Tr6” and “Tr8” in FIG. 3, respectively) 6, 8 and second constants. The current source 22 is configured as a main component.

Hereinafter, specific circuit connections will be described. First, the fifth and sixth transistors 5 and 6 constituting the input stage of the threshold voltage control circuit 101 are provided by so-called push-pull connection. That is, the gates of the fifth and sixth transistors 5 and 6 are connected to each other, and the first differential input terminal 31 or the second differential input is used as the input terminal as described in FIG. The terminal 32 is connected.
The power supply voltage V + is applied to the source and back gate of the fifth transistor (first P-channel MOS transistor for control circuit) 5, while the drain is connected to the sixth transistor 6. Along with the drain, it is connected to the gates of the seventh and eighth transistors 7 and 8.
The sixth transistor (second N-channel MOS transistor for control circuit) 6 has its back gate open, while its source is connected to the source of the eighth transistor 8, its connection point and ground Is connected to a second constant current source 22 that outputs a constant current I2.

  The seventh and eighth transistors (the third P-channel MOS transistor for the control circuit and the fourth N-channel MOS transistor for the control circuit) 7 and 8 are so-called push-pull, like the fifth and sixth transistors 5 and 6. Connected and provided. That is, the seventh and eighth transistors 7 and 8 are connected to the gate of the ninth transistor (fifth P-channel MOS transistor for control circuit) 9 while the drains are connected to each other. The power supply voltage V + is applied to the source and back gate of the transistor 7 as in the fifth transistor 5. The back gate of the eighth transistor 8 is open.

The ninth transistor 9 is configured such that the power supply voltage V + is applied to the source and the back gate, while one end of a third resistor (indicated as “R3” in FIG. 3) 27 is connected to the drain. It is connected.
The connection point between the drain of the ninth transistor 9 and the third resistor 27 is the back gate of the transistor whose threshold voltage is to be controlled, that is, the first or second transistor shown in FIG. The other end of the third resistor 27 is connected to the source of the transistor whose threshold voltage is to be controlled, that is, the source of the first or second transistor 1 or 2. It is supposed to be.
In the above configuration, it is preferable to appropriately use C-MOS transistors for the P-channel MOS transistor and the N-channel MOS transistor.

Next, the operation in this configuration will be described.
First, when an input signal is applied to the gates of the fifth and sixth transistors 5 and 6 via the first or second differential input terminals 31 and 32, the fifth or sixth transistor 5 or 6 depends on the signal level. One of the transistors 5 and 6 is turned on. That is, when the signal level is high, the sixth transistor 6 is turned on, while the fifth transistor 5 is turned off. Therefore, the seventh transistor 7 in the next stage is turned on, while the eighth transistor 8 is turned off. As a result, the ninth transistor 9 is turned off.

Since the ninth transistor 9 is turned off, the drain potential thereof is substantially the same as the source of the first or second transistor 1 or 2 connected via the third resistor 27.
Since the drain of the ninth transistor 9 is connected in series with the source of the first or second transistor 1 or 2, the source of the first or second transistor 1 or 2 is finally connected to the back. The gate is at the same potential.
In such a state, the threshold voltage VTH of the P-channel MOS transistor is expressed by the following equation.

VTH = VTH0−γ {(| 2φF + VSB |) ^1/2 − (| 2φF |) ^1/2 } Equation 1

Here, VTH0 is a threshold voltage at the time of zero bias, and is obtained as VTH0 = φMS + 2φF + Qdep / Cox.
Qdep = (4qεsi | φF | Psub) ^1/2 and φF = (KT / q) ln (Psub / ni).
Here, γ is the recombination rate, φF is the Fermi level, VSB is the source-back gate voltage, φMS is the work function difference between the polygate and the silicon substrate, Qdep is the charge amount of the depletion layer, and Cox is the gate. The capacitance of the oxide film, εsi is the relative dielectric constant of silicon, Psub is the impurity concentration of the P substrate, and ni is the hole density in the intrinsic semiconductor.

As described above, since the source and back gate of the first or second transistor 1 or 2 have the same potential, VSB = 0 in Equation 1. Therefore, it can be seen that when the signal level is high, VTH = VTH0.
By the way, the gate-source potential VGS is expressed by the following equation.

VGS = (2ID / K) ^1/2 (L / W) ¹ / ^2- VTH Formula 2

Here, ID is the drain current, K is the Boltzmann constant, L is the channel length, and W is the channel width.
As described above, when the level of the input signal is high, VTH = VTH0. In this case, the gate-source potential VGS is VGS = (2 ID / K) ^1/2 (L / W) ^1/2 −. VTH0.

  On the other hand, contrary to the above, when the input signal level to the first or second differential input terminals 31 and 32 is low, the fifth transistor 5 is turned on, while the sixth transistor 6 is turned off. It becomes a state. When the fifth transistor 5 is turned on, the eighth transistor 8 in the next stage is turned on, while the seventh transistor 7 is turned off. As a result, the ninth transistor 9 becomes conductive. Due to the conduction of the ninth transistor 9, the drain potential becomes the highest potential, that is, substantially the same potential as the power supply voltage V +. As a result, the back gate potential of the first or second transistor 1 or 2 is also the same as the power supply voltage V +.

Therefore, since VSB ≠ 0, if this is applied to the previous equation 1, VTH ≦ VTH0.
For this reason, the gate-source potential VGS obtained by the above equation 2 is lower than the gate-source potential VGS when the input signal level is high as described above.
As described above, when the input signal level is high, the back gate potential is lowered and the gate-source potential VGS is lowered. On the other hand, when the input signal level is low, the back gate potential is raised and the gate-source potential is increased. By increasing the source potential VGS, the common-mode input voltage range is expanded according to the input signal.

Next, a second specific circuit configuration example of the threshold voltage control circuit 101 will be described with reference to FIG.
Note that the same components as those shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, different points will be mainly described.
The second specific circuit configuration example is different from the circuit shown in FIG. 3 in the following points.
That is, first, the back gates of the sixth and eighth transistors 6 and 8 are connected to the respective sources.
In the ninth transistor 9, the highest potential is applied to the source. In this configuration example, the maximum potential may be a voltage equal to or higher than the power supply voltage V +.
Further, the other end of the third resistor 27, that is, the other end connected to the source of the first or second transistor 1 or 2 in FIG. 3 is connected to the ground (lowest potential). It has become a thing.

  Even in such a configuration, basically, as described with reference to FIG. 3, when the input signal level is high, the back gate potential is lowered and the gate-source potential VGS is lowered, while the input signal level is reduced. Is low, the back gate potential is raised and the gate-source potential VGS is raised, so that the common-mode input voltage range is expanded in accordance with the input signal.

5 to 8 show various characteristic examples of the differential amplifier circuit according to the embodiment of the present invention, and these characteristic examples will be described below.
First, FIG. 5 shows a characteristic example showing a change characteristic of the input offset voltage with respect to the common-mode input voltage in the differential amplifier circuit when the circuit configuration shown in FIG. 3 is used as the threshold voltage control circuit 101. In the same figure, the vertical axis represents the input offset voltage, and the horizontal axis represents the common-mode input voltage. 6 to 8, the vertical axis and the horizontal axis are the same as those in FIG.

In FIG. 5, the characteristic line represented by a solid line (indicated as “Variable VTH Circuit” in FIG. 5) is the common-mode input of the differential amplifier circuit according to the embodiment of the present invention using the circuit configuration shown in FIG. The change in the input offset voltage with respect to the voltage, and the characteristic line represented by a dotted line (indicated as “VBG = Vsource” in FIG. 5) are the common-mode inputs in the conventional differential amplifier circuit having the circuit configuration shown in FIG. The change of the input offset voltage with respect to the voltage is shown respectively. The characteristics shown in FIG. 5 were measured under the conditions of V + = 7 V and an ambient temperature of 25 ° C. The measurement conditions are the same for FIGS. 6 to 8 described later.
Thus, according to FIG. 5, it is confirmed that in the differential amplifier circuit according to the embodiment of the present invention, the input range of the common-mode input voltage is expanded to about 0.8 V toward the negative side as compared with the conventional circuit. It can be done (see the location of symbol A in FIG. 5).

Next, FIG. 6 will be described. In the same figure, the characteristic example of the conventional circuit shown in FIG. 10 is shown together with the characteristic example of the differential amplifier circuit in the embodiment of the present invention.
The characteristic example of the differential amplifier circuit according to the embodiment of the present invention shown in FIG. 6 is the same as that shown in FIG. 5, and therefore detailed description thereof is omitted here. .
On the other hand, in FIG. 6, the change in the input offset voltage with respect to the common-mode input voltage in the conventional differential amplifier circuit having the circuit configuration shown in FIG. 10 is indicated by a dotted characteristic line (indicated as “VBG = V +” in FIG. 6). It is shown.

  According to FIG. 6, in the differential amplifier circuit according to the embodiment of the present invention, it can be confirmed that the input range of the common-mode input voltage is expanded to about 0.5 V toward the positive electrode side as compared with the conventional circuit (FIG. 6). (Refer to the location of symbol B in FIG. 6).

Next, FIG. 7 will be described. In the figure, a characteristic line showing a change characteristic of the input offset voltage with respect to the common-mode input voltage in the differential amplifier circuit when the circuit configuration shown in FIG. 4 is used is shown together with the characteristic line in the conventional circuit.
In the figure, the characteristic line represented by a solid line (indicated as “Variable VTH Circuit” in FIG. 7) is the common-mode input of the differential amplifier circuit according to the embodiment of the present invention using the circuit configuration shown in FIG. The change in the input offset voltage with respect to the voltage and the characteristic line (indicated as “VBG = Vsource” in FIG. 7) represented by a dotted line are the common-mode inputs in the conventional differential amplifier circuit having the circuit configuration shown in FIG. The change of the input offset voltage with respect to the voltage is shown respectively.

  According to FIG. 7, in the differential amplifier circuit according to the embodiment of the present invention, it can be confirmed that the input range of the common-mode input voltage is expanded to about 0.6 V toward the positive side as compared with the conventional circuit (FIG. 7). 7)

Next, FIG. 8 will be described. In this figure, a characteristic example of the conventional circuit shown in FIG. 12 is shown together with a characteristic example of the differential amplifier circuit in the embodiment of the present invention.
Since the characteristic example of the differential amplifier circuit in the embodiment of the present invention shown in FIG. 8 is the same as that shown in FIG. 7, detailed description thereof will be omitted here. .
On the other hand, the change of the input offset voltage with respect to the common-mode input voltage in the conventional differential amplifier circuit having the circuit configuration shown in FIG. 12 is indicated by a dotted characteristic line (indicated as “VBG = V +” in FIG. 8).

  According to FIG. 8, in the differential amplifier circuit according to the embodiment of the present invention, it can be confirmed that the input range of the common-mode input voltage is expanded to about 0.4 V toward the negative side as compared with the conventional circuit (FIG. 8). (Refer to the location of reference numeral 8 in FIG. 8).

It is a block diagram which shows the 1st example of a basic circuit structure of the differential amplifier circuit in embodiment of this invention. It is a block diagram which shows the 2nd basic circuit structural example of the differential amplifier circuit in embodiment of this invention. It is a circuit diagram which shows the 1st specific circuit structural example of the threshold voltage control circuit used for the differential amplifier circuit in embodiment of this invention. It is a circuit diagram which shows the 2nd specific circuit structural example of the threshold voltage control circuit used for the differential amplifier circuit in embodiment of this invention. FIG. 10 is a characteristic diagram showing a change characteristic of the input offset voltage with respect to the common-mode input voltage in the differential amplifier circuit using the threshold voltage control circuit shown in FIG. 3 together with the characteristics of the conventional circuit shown in FIG. 9. FIG. 11 is a characteristic diagram illustrating a change characteristic of an input offset voltage with respect to an in-phase input voltage in a differential amplifier circuit using the threshold voltage control circuit illustrated in FIG. 3 together with characteristics of the conventional circuit illustrated in FIG. 10. FIG. 12 is a characteristic diagram showing a change characteristic of an input offset voltage with respect to an in-phase input voltage in a differential amplifier circuit using the threshold voltage control circuit shown in FIG. 4 together with characteristics of the conventional circuit shown in FIG. 11. FIG. 13 is a characteristic diagram showing a change characteristic of the input offset voltage with respect to the common-mode input voltage in the differential amplifier circuit using the threshold voltage control circuit shown in FIG. 4 together with the characteristic of the conventional circuit shown in FIG. 12. It is a circuit diagram which shows the 1st circuit structural example of the conventional differential amplifier circuit. It is a circuit diagram which shows the 2nd circuit structural example of the conventional differential amplifier circuit. It is a circuit diagram which shows the 3rd circuit structural example of the conventional differential amplifier circuit. It is a circuit diagram which shows the 4th circuit structural example of the conventional differential amplifier circuit.

Explanation of symbols

5 ... Fifth transistor (first P-channel MOS transistor for control circuit)
6 ... Sixth transistor (second N-channel MOS transistor for control circuit)
7 ... Seventh transistor (third P-channel MOS transistor for control circuit)
8: Eighth transistor (fourth N-channel MOS transistor for control circuit)
8. Ninth transistor (fifth P-channel MOS transistor for control circuit)
101a ... first threshold voltage control circuit 101b ... second threshold voltage control circuit

Claims (3)

A differential amplifier circuit in which an input stage is configured by two MOS transistors provided to perform a differential amplification operation,
For each of the two MOS transistors, a threshold voltage control circuit that controls the back gate potential of the MOS transistor according to the level of the input signal applied to the respective gate and enables the common-mode input voltage range to be expanded. A differential amplifier circuit characterized by being provided. The threshold voltage control circuit is provided by push-pull connection between a first P-channel MOS transistor for control circuit and a second N-channel MOS transistor for control circuit, and each gate is connected to each other to apply an input signal. On the other hand, the drains are connected to each other, and the third P-channel MOS transistor for control circuit and the fourth N-channel MOS transistor for control circuit, which are also connected by push-pull connection, are connected to each other. The drains of the third P-channel MOS transistor for control circuit and the fourth N-channel MOS transistor for control circuit are connected to each other and connected to the gate of the fifth P-channel MOS transistor for control circuit,
While the power supply voltage is applied to the source and back gate of each of the first, third and fifth P channel MOS transistors for the control circuit, the source of the second and fourth N channel MOS transistors for the control circuit A constant current source is provided between the
The drain of the fifth P-channel MOS transistor for the control circuit is connected to the back gate of the MOS transistor constituting the input stage of the differential amplifier circuit, and the input stage of the differential amplifier circuit is connected via a resistor. 2. The threshold voltage control circuit according to claim 1, wherein the threshold voltage control circuit is connected to a source of the MOS transistor constituting the MOS transistor. The threshold voltage control circuit is provided by push-pull connection between a first P-channel MOS transistor for control circuit and a second N-channel MOS transistor for control circuit, and each gate is connected to each other to apply an input signal. On the other hand, the drains are connected to each other, and the third P-channel MOS transistor for control circuit and the fourth N-channel MOS transistor for control circuit, which are also connected by push-pull connection, are connected to each other. The drains of the third P-channel MOS transistor for control circuit and the fourth N-channel MOS transistor for control circuit are connected to each other and connected to the gate of the fifth P-channel MOS transistor for control circuit,
While a power supply voltage is applied to the source of each of the first and third P channel MOS transistors for the control circuit and the back gate of the first, third and fifth P channel MOS transistors for the control circuit, The sources and back gates of the second and fourth N-channel MOS transistors for the control circuit are connected to each other, and a constant current source is provided between the connection point and the ground.
A voltage higher than the power supply voltage is applied to the source of the fifth P-channel MOS transistor for the control circuit, while the drain is connected to the back gate of the MOS transistor constituting the input stage of the differential amplifier circuit. The threshold voltage control circuit according to claim 1, wherein the threshold voltage control circuit is connected to the ground via a resistor.

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