JPS62229416A - Voltage limit circuit - Google Patents

Abstract

PURPOSE:To form a voltage limit circuit that can be easily integrated in a single chip and consumes an extremely small current by constituting such that a voltage limited to a fixed value is obtained from the 1st and 3rd nodes. CONSTITUTION:One end of a resistance 26 is connected to a node 11 to which a potential VDD is supplied, and the drain of an N transistor 27 is connected to the other end of the resistance 26. The source of the transistor 27 is connected to a node 13, and a bias voltage VB generated by a bias voltage generator circuit 15 is supplied to a gate. A reference voltage V1 is outputted at a connection point between the resistance 26 and the drain of the N transistor 27.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a voltage limiting circuit that limits the output voltage of a solar cell or the like to a constant value.

(Prior Art) In integrated circuits that use a power source whose generated voltage fluctuates significantly, such as a thick i-cell, conventionally, a circuit consisting of a resistor and a light emitting diode is connected in parallel to the thick battery. Efforts are being made to stabilize the voltage. However, connecting the light emitting diodes in this manner increases the number of parts and manufacturing costs, which is undesirable.

Therefore, in the past, the voltage II that can be built into an integrated circuit has been roughly
A limiting circuit has been developed. This is configured as shown in FIG. 13, for example. In this circuit, a pair of resistors 81.
82, a constant voltage circuit 83 forms a constant voltage, a voltage comparator circuit 84 compares the voltage v1 with the constant voltage, and the output controls a bipolar transistor 85 to connect a resistor 8G. By adjusting the value of the flowing N current and generating a voltage drop across this resistor 86, a portion of the output voltage of the solar cell 87 is absorbed to generate a constant voltage between nodes 88 and 89.

However, in order to keep the current consumption in such a circuit as low as several tens of nA to several hundred eights, the value of the voltage dividing resistor 81. However, when trying to configure many such high resistances within an integrated circuit,
The area it occupies is extremely large, and this resistor occupies most of the chip, which is not practical.

(Problems to be Solved by the Invention) As described above, there is a problem in that the conventional voltage limiting circuit cannot be integrated into a single chip.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a voltage limiting circuit that can be easily integrated into a single chip and has extremely low current consumption. There is a particular thing.

[Structure of the Invention] (Means for Solving Problems) The voltage limiting circuit of the present invention includes a first node to which a first power supply potential is supplied and a second node to which a second power supply potential is supplied. a third node separated from the second node by a first resistance element, and a bias voltage generating means inserted between the first and third nodes to generate a predetermined bias voltage. and a second node between the first and third nodes.
a resistance element and a reference voltage generating means for generating a reference voltage in which a MOS transistor whose gate is supplied with a predetermined bias voltage generated by the bias voltage generating means are inserted in series, and between the first and third nodes. multiple MOs in
Voltage dividing means in which S transistors are inserted in series to divide the voltage between the first and third nodes; and voltage dividing means provided between the eleventh and third nodes to divide the reference voltage and the divided voltage by the voltage dividing means. voltage comparison means for comparison, and the first
, a current path means including a bipolar transistor having a collector and an emitter inserted between the third nodes and having a base supplied with the output of the voltage comparison means, from the first and third nodes. The circuit is configured to obtain an output voltage.

(Function) In the voltage limiting circuit of the present invention, a power supply voltage is supplied between the first node and the second node, and the first resistance element is connected between the second node and the third node. By applying a part of the voltage supplied between the first node and the second node to both ends of the first resistance element, the first resistance element is
A voltage limited to a constant value 1r# is applied from the third node.

Further, in order to apply a voltage having a difference from the power supply voltage exceeding the constant voltage value to both ends of the first resistance element, a bias voltage is applied between the first and third nodes. The generating means, the reference voltage generating means, the voltage dividing means, the voltage comparing means, and the current path means are connected, the bias voltage generating means generates a predetermined bias voltage, and this voltage is supplied to the reference voltage generating means to generate a reference voltage. the voltage dividing means divides the voltage between the first and third nodes, the voltage comparing means compares the reference voltage and the divided voltage, and the current path means is operated according to the comparison result. I try to let them do it.

In addition, in order to reduce the current consumption of the entire circuit, the value of the bias voltage generated by the bias voltage generating means is set such that each MOS transistor constituting the circuit operates in a weakly inverted region of gate and drain characteristics. I am trying to set it. In other words, in general, the gate voltage (VGS) - drain current (goa IDS) characteristic of a MOS transistor is shown in the characteristic diagram of Fig. 12. In such a characteristic, it is called a weak inversion region, and the current is exponential with respect to the gate bias. There is a region A where the current flows functionally.On the other hand, there is a region B called the strong inversion region where the current flows in proportion to the square of the gate bias.The threshold voltage of the MOS transistor is near the boundary between this region A and 8. When operating in the above region B, even if an MO3I transistor is configured with the minimum size that can be realized, a current of several μ is consumed.

However, if the MOS transistor is operated in the weak inversion region of region A, the current consumption can be suppressed to about several + nA to several hundred nA.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the node 11 is supplied with a potential Voo on the high potential side of the voltage generated by a solar cell (not shown).

Similarly, the potential VEE on the low potential side is supplied to the node 12. A resistor 14 is connected between the node 11 and another node 13 to generate a voltage drop. Further, a bias voltage generation circuit 15, a reference voltage generation circuit 16, a voltage division circuit 17, a comparator 18, and a current path circuit 19 are connected between the nodes 11 and 13, respectively.

The bias voltage generation circuit 15 has a potential VO at the node 11.
A predetermined DC bias voltage VB is generated from the potential difference between O and the potential ■8B (ground potential) of the node 13. This DC bias voltage VB is set to a value such that the MOS transistor whose gate is supplied with this voltage VB operates in the weak inversion irl region. The bias voltage VB generated by the bias voltage generation circuit 15 is supplied to the reference voltage generation circuit 16 and the comparator 18.

Based on the bias voltage VB, the reference voltage generation circuit 16 generates a reference voltage V1 that is always lower than the potential Voo by a constant potential with Vss as a reference.

This reference voltage (1) is supplied to the comparator 18.

The voltage dividing circuit 17 divides the voltage Voo based on Vss at a constant ratio to generate a divided voltage v2. This voltage V2 is also supplied to the comparator 18.

The comparator 18 compares the reference voltage (1) with the divided voltage V2, and outputs a voltage v3 according to the comparison result. The output voltage v3 from this comparator 18 is supplied to a current path circuit 19.

The current path circuit 19 receives the output voltage of the comparator 18
A voltage drop is generated at the resistor 14 by flowing an li current corresponding to the voltage between the nodes 11 and 13.

FIG. 2 is a circuit diagram that does not show the specific configurations of the bias voltage generation circuit 15 and reference voltage generation circuit 16. The bias voltage generation circuit 15 is configured as follows. The source of a P-channel MOS transistor (hereinafter referred to as P transistor) 21 is connected to the node 11 to which the potential of VD (l) is supplied.Similarly, the node 11
The source of the P transistor 22 is connected to. The gate and drain of the P transistor 21 are connected,
Roughly speaking, the gate of the P transistor 22 is connected to the gate of this P transistor 21. That is, both the above P
The transistors 21 and 22 constitute a current mirror circuit in which a current proportional to the current flowing to the transistor 21 side flows to the transistor 22 side.

Further, a resistor 23 is connected to the drain of the P transistor 22.
is connected at one end. The other end of this resistor 23 is connected to the drain of an N-channel MO8 transistor (hereinafter referred to as an N transistor) 24. The source of this N transistor 24 is connected to the node 13 to which the potential of Vss is supplied, and the gate is connected to the resistor 23.
connected to one end of the The drain of the N transistor 25 is connected to the drain of the P transistor 21 . The source of this N transistor 25 is connected to the node 13, and the gate is connected to the other end of the resistor 23. That is, a resistor 23 is inserted between the drain and gate of the N transistor 24, and the gate potentials of the N transistors 24 and 25 differ by the voltage drop of this resistor 23.
4 and 25 constitute a current mirror circuit in which a current proportional to the current flowing to the transistor 24 side flows to the transformer/raster 25 side. The bias voltage VB is output from the other end of the resistor 23. The bias voltage generation circuit 15 having such a configuration operates so as to settle on a single stable point due to the self-correction function of the circuit itself.
The gate voltages of the transistors 21 and 22 have a value lower than VDO by a bias voltage valve such that each is in a set weak inversion region. The gate voltages of the transistors and transistors 25 and 24 are similarly higher than Vss by the bias voltage valve.

The reference voltage generation circuit 16 is configured as follows. A resistor 2 is connected to the node 11 to which the potential of Voo is supplied.
One end of 6 is connected. The other end of this resistor 26 has N
The drain of transistor 2 is connected. The source of this N transistor 2 is connected to the node 13, and the gate is connected to the bias voltage generating circuit 15.
A bias voltage VB generated by the voltage VB is supplied. The reference voltage V1 is output from a connection point between the resistor 26 and the drain of the N transistor 21.

FIG. 3 is a circuit diagram showing a specific configuration of the voltage valve IF circuit 17. Here, the voltage dividing circuit 17 is configured as follows. The drain and gate of an N transistor 31 are connected to the node 11 to which the potential of the VDO is supplied. The back gate (substrate) and source of this 1-transistor 31 are connected. Further, the drain of the N transistor 32 and the gate 1- are connected to the connection point between the back gate and the source of the transistor 31. The back gate and source of this transistor 32 are connected. Further, the drain and gate of an N transistor 33 are connected to the connection point between the back gate and the source of this transistor 32. The back gate and source of this transistor 33 are connected to the node 13 to which the potential of V08 is supplied.

The element dimensions of each of the transistors 31 to 33 are all made equal. In other words, this voltage dividing circuit 17 is constructed by connecting three N transistors in series between the nodes 11 and 13, each having a drain and a gate connected to each other, and a back gate and a source connected to each other. The divided voltage (2) is outputted from the connection point between the transistors 31 and 32. Therefore, the divided voltage V2
is set to correspond to 2/3 of the voltage of 17i1 between VDO and Vss.

Note that in this voltage dividing circuit 11, the voltage is V. A voltage of 1/3 of the voltage between 0 and Vas is applied to each transistor 31 to 33.
It is applied between each gate and source. In this case, the maximum value of Voo is the transistor 31
It is assumed that the gate bias voltage for each of 33 to 33 does not exceed three times the gate bias voltage such that each of the gate bias voltages operates in the weak inversion region.

FIG. 4 is a circuit diagram showing a specific configuration of the comparator 18 and current path circuit 19. Comparator 18 is configured as follows. The source of the P transistor 41 is connected to the node 11 to which the potential of Voo is supplied. Similarly, the source of a P transistor 42 is connected to the node 11. The gate and drain of the P transistor 41 are connected, and the P transistor 4
The gate of P transistor 41 is connected to the gate of P transistor 41 . That is, both the P transistors 41 and 4
2 constitutes a current mirror type load circuit in which a current proportional to the current flowing to the transistor 41 side flows to the transistor 42 @.

The drain of the P transistor 41 is connected to the drain of the N transistor 43. The above P transistor 42
The drain of the N transistor 44 is connected to the drain of the N transistor 44 . The sources of both transistors 43 and 44 are connected in common. The drain of the N transistor 45 is connected to this source common connection point. The source of this transistor 45 is connected to the node 13. The gate of this transistor 45 is supplied with the bias voltage VB output from the bias voltage generating circuit 15, and the gate of the transistor 43.
The reference voltage (1) outputted from the reference voltage generating circuit 16 and the divided voltage V2 outputted from the voltage dividing circuit 17 are supplied to each gate of 44, respectively. Also node 11
The source of P transistor 4G is connected to. The drain of this P transistor 46 is connected to an N transistor 47.
The drain of the N transistor 47 is connected to the node 13, and the source of the N transistor 47 is connected to the node 13.

The gate of the transistor 46 is supplied with the voltage at the connection point between the transistors 42 and 44, and the gate of the transistor 47 is supplied with the bias voltage VB output from the bias voltage generation circuit 15. . And the voltage v3 is the same as that of the transistors 46 and 4.
It is designed to be output from connection point 7.

The current path circuit 19 is configured as follows.

The collectors of NPN bipolar transistors 48 and 49 are connected to the node 11 to which the potential of Voo is supplied. The emitter of one transistor 48 is connected to the base of the other transistor 49, whose emitter is connected to the node 13. That is, this current path circuit 19 is a Darrington circuit consisting of two transistors, and the output voltage V3 of the comparator 18 is supplied to the base of the first stage transistor 48.

FIG. 5 is a circuit diagram in which the embodiment circuit of FIG. 1 is rewritten using each of the specific circuits of FIGS. 2 to 4.

Next, the operation of the circuit configured as above will be explained.

Now assume that a current of 11 flows through the transistor 24 in the bias voltage generating circuit 15 of FIG. A constant current (2) according to the element size ratio of the transistors 21 and 22 flows through the transistor 25. At this time, transistor 2
A voltage corresponding to the threshold voltage of this transistor 25 is generated at the gate of transistor 5. Since this voltage is supplied as VB to the gate of the transistor 27 in the reference voltage generating circuit 16, a constant current I3 corresponding to the element size ratio of the transistors 25 and 27 flows through the transistor 27. Here, the value of each of the above R currents 1 to 13 is the potential V
Even if DD changes, it is always kept constant. Therefore, in the reference voltage generation circuit 16, a certain voltage drop occurs across the resistor 26. Here, if the value of the resistor 26 is R1, then this resistor 2
6, a voltage drop of R1Xl3 occurs. For this reason,
The value of the reference voltage (1) is obtained by subtracting the above voltage drop from VDD (Voo-R1X13).

FIG. 6 is a characteristic diagram showing the characteristics of voltages VB and vl with respect to VOO.

On the other hand, the voltage dividing circuit 17 shown in FIG. 3 outputs a voltage corresponding to 2/3 of the voltage between Voo and Vss as a divided voltage V2.

Now, in the comparator 15 of FIG. 4, the divided voltage V2
is larger than the reference voltage V1, the difference voltage V2-
V1 is amplified in a comparator circuit 18 consisting of transistors 41 to 47, and v3 is lowered. Since the degree of amplification in the weak inversion region is very large, VB is almost at the Vss level, and no base current flows in the bipolar transistor 48 and no current flows in the current path circuit 19, so the value of the potential Vss at the node 13 remains constant. On the other hand, when VDD increases and the reference voltage (1) exceeds the divided voltage (2), the voltage difference between Vl and V2 is amplified, and (3) becomes almost the Voo level or an intermediate level, and the voltage is increased through the transistor 46. A base current begins to flow through the bipolar transistor 48. When the base current begins to flow in the transistor 48, the collector ff current flows in the bipolar transistors 48 and 49, and as a result, current begins to flow in the current path circuit 19. The current flowing through this current path circuit 19 is then controlled by the comparator circuit 18 so that the divided voltage V2 is on the verge of becoming larger than the M quasi-voltage v1, and the current flows to the set constant voltage v.
Since the potential difference between VDD and Voo is controlled to occur in the resistor 14, it increases in proportion to the rise in VDD. Therefore, the voltage drop v4 across the resistor 14 increases at the same slope as Voo on the value VSjX of Voo at the time when the reference voltage V1 exceeds the divided voltage v2, as shown in the characteristic diagram of FIG. I will do it. As a result, there is Vo between nodes 11 and 13.
A voltage difference between o and V4 is obtained. Here, since the slope of V4 is equal to Voo, a constant voltage is generated between nodes 11 and 13 when VDD is 75 or more.

Here, the transistor 21 in the bias voltage generation circuit 15
．． The circuit constants of the circuits 22, 24, and 25 are set so that they operate in the weak inversion region. Therefore, each of these transistors operates in a weak inversion region. Therefore, the value of current consumption in the bias voltage generation circuit 15 is kept low. Furthermore, since the bias voltage VB is applied to the gate of the transistor 21 in the reference voltage generation circuit 16, this transistor 27 also operates in the weak inversion region. Therefore, this reference voltage generation circuit 16
The current consumption value is also kept low.

Roughly speaking, even in the voltage divider circuit 17, the number of series stages and the potential 5 are set so that the gate bias is set so that each transistor connected in series operates in the weak inversion region. Current consumption is kept low. Similarly, in the comparator 18, the bias voltage VB is supplied to the gates of the transistors 45 and 47 that act as current sources, and since each operates in the weak inversion region, the current consumption value of the comparator 18 is also low. Being held down.

That is, in this embodiment circuit, each MOS transistor operates in a weak inversion region, so that the overall current consumption value is extremely low.

In addition, since the current path circuit 19 is composed of bipolar transistors, even if the element size is relatively small, it can be used as a MOS transistor.
A larger current can flow compared to an L-transistor. Therefore, the slope of (4) can be brought closer to Voo, and the value of the limited output voltage can be kept constant. The bipolar transistors 48 and 49 constituting this current path circuit 19 can be easily formed as odd transistors on a semiconductor substrate on which MOS transistors of other circuits are formed.

A cross-sectional view of FIG. 8 shows an element structure when the bipolar transistor is formed as such a parasitic transistor. In the figure, 51 is an N-type silicon substrate, 52 and 53 are P-type well regions, 54 and 55 are P+-type so-called guard ring regions provided around the surface of each of the P-type well regions 52 and 53, and 56 and 57 is P
The N+ type regions 58 and 59 are located in the N+ type well regions 52 and 53 and are provided so as to surround the P type well regions 52 and 53. The bipolar transistor 48 at the front stage is N
The type substrate 51 is a collector region, the N+ type region 58 is a collector contact region, and the P type well region 52 is a base ft41.
1i! , a P+ type guard ring region 54 serves as a base contact region, and an N+ type region 56 serves as an emitter region. Similarly, the subsequent bipolar transistor 49 uses the N-type substrate 51 as a collector region, the N+-type region 59 as a collector contact region, the P-type well region 53 as a base region, the P+-type guard ring region 55 as a base contact region, and the N+-type region as a base contact region. Region 57 is configured as an emitter region. The N+ type region 5859 is connected to the common collector electrode 60, and the guard ring region [54
is used as a base electrode 61, and further, the N" type region 56 and the guard ring region 55 are connected, and the N+ type region 57 is used as an emitter electrode 62.

FIGS. 9 to 11 are circuit diagrams each showing a configuration of a modified example of the present invention.

FIG. 9 shows a structure of the bias voltage generation circuit 15 and reference voltage generation circuit 16 that is different from that of FIG. 2. That is, in this modified example circuit, the MO of the circuit shown in FIG.
The channels of the S transistors are replaced with opposite ones.

That is, the P channel in FIG. 2 is the N channel in FIG.
It has been changed to channel. Therefore, in FIG. 9, the parts corresponding to those in FIG. 2 are given the suffix b and their explanations are omitted. In this case, the reference voltage v1 corresponds to the product of the current flowing through the resistor 26b and the value of this resistor.

FIG. 10 shows the configuration of another example of the voltage dividing circuit 17. That is, in this modified circuit, only two N transistors 31 and 32 are used to obtain a divided voltage. If VDD does not rise too high,
In this way, the division may be performed using only two MOS transistors. On the other hand, if the VOD becomes high, three or more MOs connected in series may be used.
It is necessary to divide Voo using an S transistor.

FIG. 11 shows the comparator 18 and the current path circuit 19.
The configuration of another example is shown below. That is, in this modified circuit, the channels of the MOS transistors in the circuit of FIG. 4 are replaced with the opposite ones, as in the circuit of FIG. 9 described above. That is, the P channel in FIG. 4 has been changed to the N channel in FIG. 11. Therefore, in FIG. 11, the parts corresponding to those in FIG. 4 will be given the suffix "b" and their explanation will be omitted. In addition, in the case of this modified example circuit, the transistor 47 for the N current source
b is connected to the Voo side, the driving MOS transistor 46b is connected to the Vss side, and the driving MOS transistor 46b is connected to the Vss side.
A bipolar transistor cannot be directly driven by the OS transistor 46b.

Therefore, in this case, the output voltage of the comparator 18 is set to P
The voltage is once received by an inverting circuit 73 consisting of a transistor 71 and an N transistor 72, and the bipolar transistor 48 is driven by the output voltage of this inverting circuit 73. Further, in this inverting circuit 73, for example, the gate potential of the transistor 21b is supplied as the gate bias of the N transistor 72 which acts as a current source.

In this way, in the voltage limiting circuit of the present invention, all of the circuits can be integrated into a single chip. Therefore, no external parts are required, and manufacturing costs can be reduced. In addition, there is no voltage division based on resistance ratios as in the past, and each MO8 is configured to operate in a weak inversion region where current consumption is extremely low. can be reduced.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a voltage limiting circuit that can be easily integrated into a single chip and consumes much less current.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
2 to 4 are circuit diagrams showing specific configurations of each part of the above embodiment circuit, FIG. 5 is a circuit diagram specifically showing the circuit in FIG. 1, and FIGS. 6 and 7 are FIG. 8 is a cross-sectional view showing a specific configuration of a part of the example circuit, and FIGS. 9 to 11 are circuit diagrams showing configurations of modified examples of the present invention, respectively. FIG. 12 is a characteristic diagram of a general MOS l-transistor, and FIG. 13 is a circuit diagram of a conventional circuit. 11, 12.13... Node, 14... Resistor, 15
...Bias voltage generation circuit, 16...Reference voltage generation circuit, 17...Voltage separation circuit, 18...Comparator, 19-...Current path circuit, 21, 22.41.42
．． 46...P channel MOS transistor, 24.2
5.27.31.32.33.43.44.45.47
...N-channel MOS transistor, 23.26...
-Resistors 548, 49...NPN type bipolar transistors. Applicant's Representative Patent Attorney Takehiko Suzue Figure 4 Figure 6 Figure 7 Figure 9 ] 3 Figure 10 N n Figure

Claims (5)

[Claims] (1) A first node to which a first power supply potential is supplied, a second node to which a second power supply potential is supplied, and the second node are separated via a first resistance element. a third node, a bias voltage generating means inserted between the first and third nodes to generate a predetermined bias voltage, a second resistance element between the first and third nodes, and a bias voltage generating means inserted between the first and third nodes to generate a predetermined bias voltage; a reference voltage generating means for generating a reference voltage in which MOS transistors whose gates are supplied with a predetermined bias voltage generated by the bias voltage generating means are inserted in series; and a plurality of MOS transistors between the first and third nodes. Voltage dividing means in which transistors are inserted in series to divide the voltage between the first and third nodes, and voltage dividing means provided between the first and third nodes to divide the reference voltage and the divided voltage by the voltage dividing means. The current path means includes a voltage comparing means for comparing, and a bipolar transistor having a collector and an emitter inserted between the first and third nodes and having a base supplied with the output of the voltage comparing means. . A voltage limiting circuit configured to obtain a voltage limited to a constant value from between the first and third nodes. (2) The bias voltage generating means has a source connected to the first
a first MOS transistor of a first channel connected to a node of the first MOS transistor, and a first MOS transistor whose source is connected to the first node, whose gate is connected to the gate of the first MOS transistor, and whose gate and drain are connected. a one-channel second MOS transistor, a resistor having one end connected to the drain of the first MOS transistor, a drain connected to the third node, a source connected to the other end of the resistor, and a gate connected to the resistor; a third MOS transistor of the second channel connected to one end of the resistor, and a source connected to the third MOS transistor;
a fourth MOS transistor of the second channel, the other end of which is connected to the drain of the first MOS transistor, and the gate of which is connected to the other end of the resistor; A voltage limiting circuit according to claim 1, which is configured to generate a bias voltage. (3) The voltage dividing means is constructed by inserting a plurality of MOS transistors in series between the first node and the third node, each having a gate and a drain connected to each other, and a source and a back gate connected to each other. A voltage limiting circuit according to claim 1. (4) The voltage comparison means includes a first channel first MOS transistor whose source is connected to the first node and whose drain and gate are connected, and a first MOS transistor whose source is connected to the first node and whose gate is connected. a second MOS transistor of a first channel connected to the gate of the first MOS transistor; and a second MOS transistor of a second channel whose drain is connected to the drain of the first MOS transistor and whose gate is supplied with the divided voltage. a second channel fourth MOS transistor whose drain is connected to the drain of the second MOS transistor, whose source is connected to the source of the third MOS transistor, and whose gate is supplied with the reference voltage; and a source connected to the third node and a drain connected to the third and fourth MOS
a second channel fifth MOS transistor whose source is connected to the common connection point of the transistors and whose gate is supplied with a predetermined bias voltage generated by the bias voltage generating means; and whose source is connected to the first node and whose gate is The first MOS transistor connected to the drain of the second MOS transistor
A sixth MOS transistor of the channel has a drain connected to the drain of the sixth MOS transistor, a source connected to the second node, and a gate supplied with a predetermined bias voltage generated by the bias voltage generating means. 2. The voltage limiting circuit according to claim 1, comprising a seventh MOS transistor of a second channel, and configured to obtain an output from a connection point between the sixth and seventh MOS transistors. (5) The voltage limiting circuit according to claim 1, wherein the current path means is constituted by a Darrington transistor.