JPH109967A - Reference voltage circuit and temperature detection circuit using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage circuit suppressed in the fluctuations of reference voltage output caused by the irregularity of the leak current of the leak path generated by production irregularity. SOLUTION: In a reference voltage circuit 82 equipped with an operational amplifier 61, a plurality of resistors 62-64 and a plurality of the transistors 65-70 connected to the diode formed on one semiconductor substrate, the transistors 65-70 are formed to both ends of the resistor 78 on the earth terminal side of the series circuit of two resistors 77, 78 connected across the output voltage terminal and earth terminal of the reference voltage circuit 82 to connect a leak path 79 having the same structure as a parasitically generated leak path. By this constitution, even if irregularity is generated in the leak current of the leak path by the irregularity of impurity concn. caused by production irregularity, this effect is negated by a dummy leak path and the fluctuations of reference voltage output by the irregularity of a leak current can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage circuit formed on a semiconductor substrate and a temperature detecting circuit using the same, and more particularly, to a circuit configuration technology having less temperature dependency.

[0002]

2. Description of the Related Art A temperature detection circuit is an application example in which a reference voltage circuit is provided, and its temperature characteristics are important. Hereinafter, the temperature detection circuit will be described as an example. FIG. 6 shows a conventional temperature detecting circuit using a reference voltage circuit formed on a semiconductor substrate. FIG. 7 shows FIG.
FIG. 6 is a diagram showing the temperature dependence of the voltage of each part of the circuit of FIG. Less than,
The circuit configuration and operation of a conventional example will be described with reference to FIGS. This circuit is a temperature detection circuit using a band gap reference (hereinafter referred to as BGR) reference voltage circuit.

First, the circuit configuration will be described. Reference voltage circuit 2
1 is an operational amplifier (operational amplifier) 1, resistors 2 to 4,
NPN transistors (hereinafter, transistors are referred to as Tr) 5 to 7 having diode-connected emitter areas A ₁ ,
And Tr8~10 emitter area A _2, and BGR circuit consisting resulting leakage path 11 to 16 Metropolitan parasitically by configuring the Tr, the BGR output (reference voltage output)
And resistors 17 and 18 for dividing the resistance.
Reference numeral 19 denotes a reference voltage output terminal, and reference numeral 20 denotes a temperature sense output terminal. It is assumed that the respective Trs are formed on the same semiconductor substrate and all the resistors are manufactured by the same process. The reference voltage circuit 21 and the comparator (comparator) 22 constitute a temperature detection circuit.

Next, the operation will be described with reference to FIG. Here, description will be made assuming that there is no influence of the leak paths 11 to 16 for the time being. In FIG. 7, the vertical axis represents the voltage of each part of the circuit, and the horizontal axis represents the temperature of the semiconductor substrate incorporating this circuit. Vbgr is a BGR output (≒ 3.6 [V]) and has no dependency on the semiconductor substrate temperature. aVbgr
Is a reference voltage output obtained by dividing the resistance of the BGR output [division coefficient a
= A _{R 5 / (R 4 + R} 5) ], there is no dependence of the semiconductor substrate temperature similar to the Vbgr. Vfb is a temperature sense output, which corresponds to three base-emitter voltages of diode-connected Trs 8 to 10, and is usually -6 [mV / C].
It has a degree of temperature dependence. Therefore, by appropriately selecting the values of the resistors 17 and 18, a point where aVbgr and Vfb intersect at a certain temperature can be created. This point is detected temperature T
If x is detected by the comparator 22, it can be detected that the temperature of the semiconductor substrate has reached Tx.
That is, when the state of Vfb> aVbgr changes to Vfb <aVbgr, the output of the comparator 22 changes from the Low level to the Hi level.

[0005] The voltage of each part of the circuit is expressed by the following equation. In the following description, the operational amplifier 1
And the comparator 22 are operating in an ideal state (ie, the state where the input bias current and the input offset voltage are zero).

(1) BGR output voltage Vbgr The potentials Vfa and Vfb at the point where diode-connected Trs are connected in three stages in series are expressed by the following equations (1) and (2).

[0007]

(Equation 1)

Where k: Boltzmann's constant q: elementary charge T: temperature A ₁ : emitter area of Tr 5 to 6 Iso: reverse saturation current density A ₂ : emitter area of Tr 8 to 11 Also, due to the imaginary short circuit of the operational amplifier 1, The voltage ΔVf applied to both ends of the resistor 4 (R ₃ ) is given by
It becomes as shown in the formula. ΔVf = Vfa−Vfb (Equation 3) By substituting the equations (1) and (2) into the equation (3), the following equation (4) is obtained.

[0009]

(Equation 4)

The current flowing in the circuit is caused by the imaginary short circuit of the operational amplifier, the following equation (5), and the following equation (6).
It becomes as shown in the formula. I ₁ · R ₁ = I ₂ · R ₂ (Equation 5) I ₁ = I ₂ (R ₂ / R ₁ ) (Equation 6) Also, I ₂ and ΔVf are as shown in the following equation (7). Have a relationship. I ₂ = ΔVf / R ₃ (Equation 7) The output voltage of the BGR circuit is expressed by the following (Equation 8). Vbgr = Vfa + I ₁ · R ₁ (Equation 8) By substituting the equations (1), (4), (6) and (7) into the above equation (8), the following equation is obtained. 9) is obtained. Equation (9) is an equation indicating the BGR output voltage Vbgr.

[0011]

(Equation 9)

(2) Reference voltage output aVbgr Since the voltage division coefficient a is a = R ₅ / (R ₄ + R ₅ ) as described above, this a is multiplied by Vbgr to obtain the following equation (10). As shown, a reference voltage output aVbgr is obtained.

[0013]

(Equation 10)

(3) Temperature Sense Output Vfb The temperature sense output Vfb is as shown in the above equation (2).

Next, when the above-described circuit is actually formed on a semiconductor substrate, it is necessary to consider the influence of a parasitic device (leak path) which is structurally generated. Hereinafter, the influence of the leak path will be described. First,
The structure of the leak paths 11 to 16 will be described. FIG. 8 is a diagram showing an example of the device structure of Tr used in the reference voltage circuit. In FIG. 8, Tr represents first P + diffusion regions 30, 31, 32 and first N + diffusion regions 33, 34.
, P-well region 35, second N + diffusion region 36, and N-wel
1 region 37, an N- buried region 38, a P-epi region 39, and a P-sub region 40;
Is the emitter region, P-well region 35 is the base region, N-
The well region 37 corresponds to a collector region. In addition, P-su
The b region 40 and the P-epi region 39 are connected to GND (ground). By connecting the base and collector of this Tr, it is used as a diode.

In the case of the above-mentioned device structure, the junction between the collector region and the substrate region which is GND is separated by reverse bias. This portion is a leak path, and a leak current exists. As the temperature of the semiconductor substrate increases, the value increases, and the circuit currents I ₁ and I ₂ (FIG. 6)
Depending on the size of the project). As described above, in the circuit configuration of FIG.
16 results.

FIG. 9 is a plan view showing an example of the arrangement of N-well region groups forming Tr and leak paths in the conventional example. In FIG. 9, 51 to 53 correspond to Tr8 to 10, and 54 to 56 correspond to Tr5 to Tr7. Reference numeral 49 denotes a reference voltage circuit forming area, and reference numeral 50 denotes a temperature detecting circuit forming area.

Next, the operation of the reference voltage circuit in consideration of the influence of the leak paths 11 to 16 will be described. In proceeding with the description, first, the voltage equations of the respective parts when a leak path is considered will be described.

(1) BGR output voltage Vbgr (when there is an influence of a leak path) First, the potentials Vfa and Vfb at the point where three diode-connected Trs are connected in series are expressed by the following equation (11). Become.

[0020]

[Equation 11]

Here, the voltage between the leak paths is approximately 0.4 [V] in the leak path 13 and approximately 1.2 in the leak path 11 in the detection temperature range (for example, 150 to 200 ° C.).
[V], which is almost the same as the leakage current value.
Therefore, if Ix ₁₁ = Ix ₁₂ = Ix ₁₃ = Ixa in the equation (11), the following equation (12) is obtained.

[0022]

(Equation 12)

If the leak current density of the N-well group in the Tr formation region is Ix and the N-well area of Tr5 to Tr7 is A _T1 , then Ixa = IxA _T1 . Therefore, Vfa is represented by the following (expression 13).

[0024]

(Equation 13)

In the equation (13), the underlined part is a term indicating the influence of the leak path, and is similarly shown in the following equation.

On the other hand, with respect to Vfb, Nw
Assuming that the ell area is A _T2 and Ix ₂₁ = Ix ₂₂ = Ix ₂₃ = IxA _T2 , the following equation (14) can be obtained if it is obtained in the same manner as above.

[0027]

[Equation 14]

The voltage ΔVf applied across the resistor 4 (R ₃ ) due to the imaginary short-circuit of the operational amplifier is expressed by the above equation (3). Then, (Equation 3)
By substituting the expressions (3) and (Equation 14), the following (Equation 15) is obtained.

[0029]

(Equation 15)

Equations (6), (7),
From the equations (8) and (15), Vbgr considering the influence of the leak path is expressed as the following equation (16).

[0031]

(Equation 16)

(2) Reference voltage circuit output aVbgr (when there is an influence of a leak path) The reference voltage circuit output aVbgr is the same as the above equation (10), but the content of Vbgr in the equation is the above (equation 16) It is an expression.

(3) Temperature sense output Vfb (when there is an influence of a leak path) The temperature sense output Vfb is the same as the above equation (14).

Here, a comparison between the expression without the leak path and the expression with the leak path reveals that the expression with the leak path is exactly the same as the expression without the leak path, ignoring the term of the expression with the leak path. Further, the relationship between the emitter area parameters A ₁ and A ₂ of the diode-connected Tr is always A ₁ <A ₂ if I ₁ = I _{2 in} the BGR circuit. This is BG
This is because ΔVf in the equation (3) can have only a positive value to operate the R circuit (see FIG. 6). Therefore, in order to minimize the chip area, the N
The relationship between the -well area parameters A _T1 and A _T2 is A _T1 <A _T2
Becomes Here, if the ratio between A _T2 and A _T1 is m, then m = A _T2
/ A _T1 .

Next, based on the above formulas, the results obtained by roughly estimating the potential of each part when there is a leak current as compared to when there is no leak current under the following conditions are shown. Calculation conditions T = 175 [° C.] I ₁ = I ₂ = 15 [μA] Ix = 160 [μA / mm ² ] A _T1 = 0.0025 [mm ² ] A _T2 = 0.0075 [mm ² ] R ₂ / R ₃ = 10 R ₄ / R ₅ = 2/1 Calculation result Vbgr rises 135 [mV] aVbgr rises 45 [mV] Vfb falls 21 [mV] From the above calculation result, when the leak current increases, the reference voltage circuit It can be understood that the temperature sense output Vfb of the reference voltage falls and Vbgr and the reference voltage output aVbgr of the reference voltage circuit rise.

The effect of the temperature detection circuit based on the above results will be described with reference to FIG. FIG. 10 is a diagram showing the temperature dependence of the voltage of each part of the circuit, in which the vertical axis represents the voltage and the horizontal axis represents the temperature of the semiconductor substrate incorporating this circuit. In a low temperature range, the leakage current is extremely small and has little effect, but in a temperature range where the detection temperature is set, the effect of the leakage current appears. By applying the above calculation results to FIG. 10, it can be seen that an increase in the leakage current leads to a decrease in the detected temperature when viewed as a temperature detection circuit.

The leakage current varies due to manufacturing variations. This manufacturing variation is a variation in the impurity concentration of the region forming the leak path.
Therefore, the reference voltage output of the reference voltage circuit varies due to the variation of the leak current. Similarly, when viewed as a temperature detection circuit, even if the detection temperature is set assuming a certain leak current, the actual detection temperature will vary due to manufacturing variations.

The reason why the detected temperature has a variation will be described below. If the upper limit of the variation in the detected temperature is higher than the limit temperature of the package and the bonding wire, the reliability of the package or the bonding wire may be increased before the temperature detection circuit outputs an output indicating that the temperature of the semiconductor circuit has risen. May occur, and the function of the IC may be lost. In an IC with a built-in temperature detection circuit, the output of the temperature detection circuit is used.
Generally, the operation of the main circuit is stopped or limited. Therefore, if the lower limit of the variation in the detected temperature is within the operating temperature range of the main circuit, a situation occurs in which the operation of the main circuit is stopped or restricted in spite of the temperature at which normal operation is to be performed. Therefore, the detection temperature of the temperature detection circuit must be lower than the limit temperature of the package or the bonding wire and higher than the operating temperature range of the main circuit. That is, it is understood that it is necessary to minimize the variation in the detected temperature.

[0039]

As described above, in the conventional reference voltage circuit, the reference voltage output fluctuates due to the variation in the leak current of the leak path caused by the manufacturing variation, and when the reference voltage circuit is used in the temperature detection circuit, the detected temperature becomes lower. However, there was a problem that there was variation.

The present invention has been made in order to solve the above problems, and a first object of the present invention is to provide a reference circuit capable of suppressing fluctuations in a reference voltage output due to variations in leak current of a leak path caused by manufacturing variations. A second object is to provide a voltage detection circuit that suppresses variations in detection temperature for the same reason as described above.

[0041]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, in the bandgap reference type reference voltage circuit, a circuit for dividing a reference power supply voltage by a resistor and outputting the divided reference voltage as a reference voltage, wherein the reference voltage circuit is connected between an output voltage terminal and a ground terminal. A structure in which a leak path having the same structure as a leak path which is parasitically generated by forming a transistor of a reference voltage circuit is provided at both ends of a ground-side resistor in a series circuit of two connected resistors. . As described above, in the present invention, by connecting a dummy leak path having the same structure as the leak path in the BGR circuit to the point where the BGR output is divided by resistance, even if there is a variation caused by manufacturing variation in the leak current of the leak path. ,
The dummy leak path cancels this effect.

Further, claim 2 shows a specific configuration example of claim 1, and the dummy leak path is arranged at a position close to the leak path on the semiconductor substrate as described in claim 2.

Further, claim 3 shows a configuration of a temperature detection circuit using the reference voltage circuit of claim 1 or 2. The configurations of claims 1 to 3 correspond to, for example, a first embodiment shown in FIGS. 1 to 5 described later.

The fourth aspect of the present invention is directed to a temperature detecting circuit having a hysteresis circuit, wherein two MOS transistors constituting the hysteresis circuit are of the same conductivity type, and are inverted between their gates. It has a configuration in which a circuit is inserted. The configuration of claim 4 corresponds to, for example, a second embodiment shown in FIGS.

[0045]

According to the first to third aspects of the present invention,
The point where the BGR output in the reference voltage circuit is divided by resistance is BGR
By having the same structure as the leak path in the circuit and connecting the dummy leak path arranged near the leak path, even if the leak current of the leak path varies due to the variation of the impurity concentration due to the manufacturing variation, the dummy leak path may be used. Has the effect of canceling this effect and reducing fluctuations in the reference voltage output due to variations in leakage current. Therefore, in the temperature detection circuit using the reference voltage circuit, the effect of reducing the fluctuation of the detected temperature can be obtained.

According to the fourth aspect of the present invention, the two MOS transistors constituting the hysteresis circuit are of the same conductivity type and have a leak path structure of BGR.
By using the same structure as the leak path structure in the circuit, even in a temperature detection circuit having a hysteresis circuit, the variation in the detection temperature due to manufacturing variations can be effectively reduced by the same configuration as in the first to third aspects. The effect that it can be reduced is obtained.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. First, the circuit configuration will be described. 6 is different from the conventional example shown in FIG. 6 in that a dummy leak path 79 is provided in the reference voltage circuit. The reference voltage circuit 82 includes an operational amplifier 61 and resistors 62 to 64.
When, the emitter area A ₁ that is diode-connected Tr65~
67 and Tr 68 of emitter area A ₂ (m = A ₂ / A ₁ )
70, and a BGR circuit including leak paths 71 to 76 generated by configuring Tr, and a BGR output V
bgr (reference voltage output) is divided by resistors 77 and 78 and a dummy leak path 79, and has a reference voltage output terminal 80 and a temperature sense output terminal 81. Note that Tr
It is assumed that 65 to 70 are all formed on the same semiconductor substrate, and all the resistors are manufactured by the same process.

The above-described reference voltage circuit 82 and comparator 8
3 constitute a temperature detection circuit. When the temperature of the semiconductor substrate reaches a preset detection temperature, that is, when the temperature of the semiconductor substrate reaches a predetermined detection temperature, the output of the comparator 83 changes from the state of Vfb> aVbgr to Vfb.
When b <aVbgr, the level changes from low to high. Note that the + input terminal and the − input terminal of the comparator 83 may be interchanged. In such a connection, the output of the comparator 83 changes from the Hi level to the Low level when it reaches the detected temperature.

Next, FIG. 2 is a plan view showing an example of the arrangement of the N-well region (leak path region). N−w of each Tr
As shown in FIG. 2, the ell regions 91 to 96 are arranged close to each other, and the N-well region 97 serving as a dummy leak path is arranged in the vicinity thereof. The position indicated by the broken line may be used. Note that 91 to 93 correspond to Tr 68 to 70, and 94 to 96 correspond to Tr 65 to 67. Also, 8
Reference numeral 9 denotes a formation region of the reference voltage circuit, and reference numeral 90 denotes a formation region of the temperature detection circuit.

The arrangement shown in FIG. 3 may be adopted. In FIG. 3, N-well regions 100 to 103 are Tr.
68 to 70, and 104 to 106 correspond to Tr 65 to 67.
Is equivalent to N- 107 is a dummy leak path.
Indicates a well region. Reference numeral 99 denotes a formation region of the reference voltage circuit, and reference numeral 100 denotes a formation region of the temperature detection circuit.

FIG. 4 is a sectional view showing a device structure of a dummy leak path. The structure is such that the base region and the emitter region are removed from the configuration of Tr shown in FIG. In FIG. 4, 200 (30), 201 (3
2) is a first P + diffusion region, and 202 (34) is a first N + diffusion region.
The diffusion region, 203 (36), is the second N + diffusion region, 20
4 (37) is an N-well region, 205 (38) is an N-embedded region, 206 (39) is a P-epi region, and 207 (4
0) is a P-sub region. The numbers in the parentheses indicate the corresponding parts in FIG.

Next, the operation will be described. First, the relationship between the leak current of the leak path and the leak current of the dummy leak path will be described. As described above, the variation in the leak current of the leak path is caused by the variation in the impurity concentration of the leak path forming region on the semiconductor substrate. FIG. 11 is a diagram showing an example of the distribution of the impurity concentration on the semiconductor wafer. FIG.
As shown in FIG. 1, the distribution of the impurity concentration is two-dimensionally gently distributed on the wafer surface, and the N-well region group, which is a leak path, and a dummy leak path arranged near the N-well region group with respect to the distribution in the wafer. Can be said to be substantially the same in the N-well region. Therefore, even if the absolute value of the leak current itself varies in the semiconductor wafer surface, the relative value of the leak current value in the N-well region as a leak path and the leak current value in the N-well region of the dummy leak path arranged in the vicinity thereof is present. The relationship is the same everywhere in the wafer.

Next, the operation of this embodiment will be described. FIG. 5 is a characteristic diagram showing the temperature dependence of the voltage of each part in the present embodiment. The potential of Vfb having a negative temperature characteristic similarly to the characteristic of the conventional example shown in FIG. 10 decreases as the leak increases. Here, attention is paid to the node of aVbgr. As described in the above conventional example, this node moves in the direction of increasing the potential when the leak increases. On the other hand, in the dummy leak path, a leak current having a relative relationship with the leak current of the leak path flows, and acts to lower the potential of the aVbgr node. By appropriately setting the degree of influence of the dummy leak, the fluctuation of the reference voltage output can be reduced even if the absolute value of the leak current changes. Therefore, from the viewpoint of the temperature detecting circuit, the fluctuation of the detected temperature can be reduced as compared with the conventional example having no dummy leak path.

Further, effects of the present embodiment will be described based on mathematical expressions and simulation results. First, the equations for the voltage of each part are shown below. (1) BGR output voltage Vbgr This is expressed by the same (Equation 16) as in the conventional example. (2) Temperature sense output Vfb The temperature sense output is represented by the same equation (Formula 14) as that of the conventional example. (3) The leak current density of the N-well group in the reference voltage output aVbgr Tr forming region is defined as Ix,
Assuming that the area of the dummy leak path N-well is Ad, the reference voltage output aVbgr is expressed by the following equation (17).

[0055]

[Equation 17]

From the above equation, the difference between this embodiment and the conventional example is aVbgr. Comparing the conventional equation (Equation 10) with the equation (Equation 17), the aVbgr simply increases when the leak increases in the conventional example. However, in the present embodiment, there is a leak correction amount. It is clear that the effect of the leak can be reduced in comparison. Therefore, if the ratios of A _T1, A _T2, and Ad representing the area of the leak path and the dummy leak path and Ad, and the values of R ₄ and R ₅ for dividing the resistance of the BGR output are set to appropriate values, the reference based on the leak is compared to the conventional example. Fluctuations in voltage output can be reduced. Therefore, when viewed as a temperature detecting circuit, it is possible to reduce the fluctuation of the detected temperature Tx.

Next, an example of the simulation results is shown in the following (Table 1). The results shown in Table 1 indicate that the detected temperature is a region where the leakage current is not negligible with respect to the circuit currents I ₁ and I ₂ (150 ° C. or more), and is a general semiconductor package. In consideration of the limit temperature, the temperature was set to 175 [° C.], and the calculation was performed assuming that the leak current density varied by a factor of two (varied from 50% to 200% of the center value).

[0058]

[Table 1]

However, the simulation conditions are as follows. T = 175 [° C.] R ₁ = 152.5 [kΩ], R ₂ = 152.5 [kΩ], R
₃ = 17.5 [kΩ], R ₄ = 550 [kΩ], R ₅ = 19
0 [kΩ] Ix = 160 [μA / mm ² ], A _T1 = 0.0025 [m
m ² ], A _T2 = 0.0075 [mm ² ], Ad = 0.002
5 [mm ² ] The variation range of Ix is Ix = 160 [μA / mm]
² ] is the center value and is doubled, that is, 80 to 320.
It was determined to vary within the range of [μA / mm ² ].

As can be seen from the above simulation results, in this embodiment, the variation in the detected temperature is significantly reduced as compared with the conventional example. In the present embodiment, the number of diode-connected Trs has been described as being three. However, it is needless to say that the same effect can be obtained by optimizing the parameter setting with other numbers of stages.

(Second Embodiment) Next, a second embodiment will be described. In this embodiment, the present invention is applied to an example in which a hysteresis circuit is added to stabilize a temperature detection output near a detected temperature in a temperature detection circuit. FIG. 15 is a circuit diagram of a temperature detection circuit in which a hysteresis circuit is added to a conventional temperature detection circuit.
FIG. 6 is a characteristic diagram showing the temperature dependence of the circuit of FIG. Hereinafter, the circuit configuration and operation of the conventional example will be described with reference to FIGS.

First, the circuit configuration will be described. The BGR circuit is
An operational amplifier 1, the resistor 2~4 (R ₁ ~R _3), and Tr5~7 of diode-connected emitter area A _T1, and Tr8~10 emitter area A _T2, a leakage path 11 caused by configuring Tr ~ 16. The temperature detection circuit includes the BGR circuit and resistors 301 (R ₄₁ ) and 302
(R ₄₂ ), 18 (R ₅ ), P-type MOS-Tr 303 and N
Type MOS-Tr 304, the comparator 22, and the M
Leak path 3 caused by configuring OS-Tr 3
05 to 307.

Next, the operation will be described with reference to FIG. Here, leak paths 11-16, 305-307
The explanation is made assuming that there is no influence. In FIG. 16, the vertical axis represents the voltage, and the horizontal axis represents the temperature of the semiconductor substrate incorporating this circuit. The BGR output Vbgr, which is the output of the circuit, outputs a certain voltage (for example, about 3.6 [V]) and has no dependency on the semiconductor substrate temperature. In the following description, it is assumed that the operational amplifier 1 and the comparator 22 are operating in an ideal state (that is, an input bias current and an input offset voltage are zero).

When the semiconductor substrate temperature is low (detection temperature Tx
Is reached), the comparator 22 which is the temperature detection output
Is output, the P-type MOS-Tr 303 is turned off, the N-type MOS-Tr 304 is turned on, and the potential of aVbgr1 in FIG. It can be seen that the output of the comparator changes from Hi to Low when the temperature of the semiconductor substrate rises and the potential of aVbgr1 intersects with Vfb, which is Vf for three stages of diodes, to reach the preset detection temperature Tx. At this time, the output of the comparator 22 receives the P-type MO.
The S-Tr 303 is turned on, the N-type MOS-Tr 304 is turned off, and a-Vbg in FIG.
The potential of r2 is input. Therefore, the point at which the output of the comparator 22 changes when the temperature of the semiconductor substrate falls is the point of the return temperature Ty, which means that the temperature detection output has a hysteresis characteristic.

When the present circuit is actually formed on a semiconductor substrate, it is necessary to consider the influence of a parasitic device (leak path) which is structurally formed as described in the first embodiment. Hereinafter, the leak path in the present circuit will be described. The structure of the leak paths 11 to 16 formed in the BGR circuit is the same as that of the first embodiment. On the other hand, where a leak path occurs in the hysteresis circuit, the P-type MOS-Tr 303 and the N-type MOS-Tr 3
04.

FIG. 17 is a sectional view showing a device sectional structure of a leak path in a hysteresis circuit portion of the present circuit. In FIG. 17, a P-type MOS-Tr 303 includes a P-epi region 319, a P-sub region 320, and a first P + diffusion region 3.
09, 310, a gate electrode 317, a first N + diffusion region 312, a second N + diffusion region 315, and an N-well.
The first P + diffusion region 309 corresponds to a drain, the first P + diffusion region 310 corresponds to a source, and the N-well region 318 corresponds to a substrate region.

The N-type MOS-Tr 304 is a P-epi
A region 319, a P-sub region 320, first N + diffusion regions 313 and 314, and a gate electrode 316, the first N + diffusion region 314 is a drain, and the first N + diffusion region 313 Represents a source, and the P-epi region 319 corresponds to a substrate region. The P-sub area 320 and the P-epi area 31
9 is connected to GND.

In the case of such a device structure, a P-type MO
In the S-Tr 303, the N-well region 318 (including the N-embedded region 323) and the P-epi region 31 which is GND
During the N-type MOS-Tr 304, the drain 313,
Similarly, the junction between the source 314 and the P-epi region 319 which is GND is separated by reverse bias. This portion is a leak path, and a leak current exists. Then, as the temperature of the semiconductor substrate increases, the value of the leak current increases, and cannot be ignored depending on the scale of the circuit currents I ₁ and I ₂ (see FIG. 15).

As described above, in the circuit configuration of FIG.
In the GR circuit, leak paths 11 to 16 are generated, and a P-type MOS
A leak path 305 is generated in −Tr 303, and leak paths 306 and 307 are generated in the N-type MOS-Tr 304.
Occurs.

FIG. 18 is a plan view showing an example of the pattern arrangement of the N well region of Tr of the BGR circuit and the N + region of MOS-Tr of the hysteresis circuit which are leak paths in the above circuit. In FIG. 18, reference numeral 333 denotes an area for forming the temperature detection circuit, and reference numerals 324 to 326 denote Tr8 to Tr1 in FIG.
0, 327-329 correspond to Tr5-7, 3
30 corresponds to a P-type MOS-Tr 303, and 331 and 33
2 corresponds to the N-type MOS-Tr 304.

When the hysteresis circuit is added to the conventional temperature detection circuit as described above, the MOS of the hysteresis circuit
-A leak path is formed at Tr. The point to note here is P
The leak path of the MOS-Tr 303 has the same structure (N-well) as the dummy leak path described in the first embodiment.
And P-sub), whereas the N-type MOS-Tr30
The leak path No. 4 has a different structure (between N + and P-sub).

The idea of the first embodiment is to arrange a dummy leak path having the same structure as the leak path of the BGR circuit in the vicinity so that the two have a relative relationship, and the absolute value of the leak current value varies due to manufacturing variations. Also, a circuit configuration in which a dummy leak path cancels this is provided. However, when this concept is applied to the present circuit, the leak path of the P-type MOS-Tr 303 can be a dummy leak path similar to the above,
Since the leak path (between N + and P-sub) of the N-type MOS-Tr 304 has a completely different structure, its influence must be newly considered. That is, in the first embodiment, one type of leak path is considered, whereas in the present circuit, two types of leak paths need to be considered.

The problem in having two types of leak paths will be described below. Here, the leak path between N-well and P-sub is referred to as leak path 1, and the leak path between N + and P-sub is referred to as leak path 2. When the present circuit is configured at a certain point on the semiconductor substrate, it is assumed that the leak current value of leak path 1 is half the design type value. At this time, since the leak current value of the leak path 2 is completely different from that of the leak path 1, the leak current value may be half or twice the design type value. That is, it is difficult to associate the behavior of the leak path 2 with the leak path 1. That is, since there are two types of leak paths in the present circuit, the effect is very difficult to grasp, and there is a problem that it is very difficult to design a circuit using the concept of the first embodiment. The second embodiment solves the above problem.

Hereinafter, a second embodiment will be described with reference to the drawings. FIG. 12 is a circuit diagram showing the second embodiment. The circuit of FIG. 12 uses a P-type MOS-Tr 321 in place of the N-type MOS-Tr 304 constituting the hysteresis circuit in the circuit of FIG. 15, and connects the output terminal of the comparator 22 to the gate of the P-type MOS-Tr 321. An inverter (inverting circuit) 322 is provided between them. Other parts are the same as those in FIG. 15, and the same reference numerals as those in FIG. 15 indicate the same parts. As described above, in FIG.
The P-type M-type MOS-Tr for the hysteresis circuit has the same leak path structure as the BGR circuit.
Only OS-Tr is used.

FIG. 13 shows a P-type MOS for hysteresis.
It is sectional drawing which shows the device structure of Tr303,321. In FIG. 13, a P-type MOS-Tr 303 is composed of Pe-e
pi region 357, P-sub region 358, first P + diffusion regions 341 and 342, gate electrode 351, and first N
+ Diffusion region 346, a second N + diffusion region 348, and N-
The first P + diffusion region 341 corresponds to a source, the first P + diffusion region 342 corresponds to a drain, and the N-well region 353 corresponds to a substrate region. Similarly, the P-type MOS-Tr 321
-Epi region 357, P-sub region 358, and first P +
The diffusion regions 343 and 344, the gate electrode 352, and the first
N + diffusion region 347, a second N + diffusion region 349,
It is composed of an N-well region 354 and an N- buried region 356. The first P + diffusion region 343 corresponds to a source, the first P + diffusion region 344 corresponds to a drain, and the N-well region 354 corresponds to a substrate region. . As shown, the P-type MOS-Tr
303 and 321 have exactly the same device structure.

FIG. 14 shows a BGR which is a leak path.
NPN-Tr formation region in circuit and P-type MOS-Tr30
It is a top view which shows an example of the pattern arrangement of the formation area of 3,321. In FIG. 14, 360 to 362 correspond to Tr8 to 10 in FIG. 12, 363 to 365 correspond to Tr5 to 7, and 366 and 367 denote P-type MOS-Tr303 and 32.
Equivalent to 1. Reference numeral 368 denotes an area where the temperature detection circuit is formed. As shown in FIG. 14, when the leak paths are arranged at close positions, a relative relationship is created between the leak paths as described in the first embodiment.

Next, the operation will be described. Temperature is detected temperature T
Before reaching x, the temperature detection output of the comparator 22 is H
i is output, and the P-type MOS-Tr 303 is turned off.
On the other hand, the P-type MOS-Tr 321 is turned on because the inverter 322 is provided before the gate. In this state, the negative input terminal of the comparator 22 is connected to aVbgr1 in FIG.
Is input. When the temperature of the semiconductor substrate rises and reaches the detection temperature Tx, the output of the comparator 22 changes from Hi to Low. In response, P-type MOS-Tr3
03 is on, the P-type MOS-Tr 321 is off, and the potential of aVbgr2 in FIG. As a result, the point at which the output of the comparator 22 changes when the temperature of the semiconductor substrate falls is at the return temperature Ty (see FIG. 16), which means that the temperature detection output of the temperature detection circuit has hysteresis.

Next, the operation will be described. In the circuit of FIG. 12, the MOS-Tr for hysteresis is replaced by a P-type MOS-Tr.
Only one type of leak path structure
Can be easily introduced. Therefore, the design can be easily performed as compared with the conventional example shown in FIG.

In this embodiment, the P-type MO
Care must be taken in setting the threshold voltages of S-Tr 303 and 321. Hereinafter, the reason will be described.

For example, when the detected temperature is set to about 175 ° C. (for the reason, see the first embodiment), a
The potential of Vbgr1 becomes about 1.2 [V] (in the case of Vf of three steps of diodes as shown in FIG. 12), and the P-type MOS-
The source and substrate potentials of Tr 303 are the same. Therefore, in order to turn on the P-type MOS-Tr 303, its threshold voltage needs to be set lower than 1.2 [V]. The same can be said for the P-type MOS-Tr 321.

As described above, in the second embodiment, two MOS transistors forming a hysteresis circuit are used.
-Tr is formed with the same conductivity type,
Even in a temperature detection circuit having a hysteresis circuit, the influence of a leak path can be reduced in the same way as in the first embodiment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an example of an arrangement of an N-well region (leak path region) in the first embodiment.

FIG. 3 is a plan view showing another example of the arrangement of the N-well region (leak path region) in the first embodiment.

FIG. 4 is a sectional view showing a device structure of a dummy leak path according to the first embodiment.

FIG. 5 is a temperature characteristic diagram of a voltage of each part of the temperature detection circuit according to the first embodiment.

FIG. 6 is a circuit diagram of an example of a conventional device.

FIG. 7 is a temperature characteristic diagram of voltages of respective parts of a temperature detection circuit in a conventional device.

FIG. 8 is a sectional view showing a device structure of a transistor and a leak path in a conventional device.

FIG. 9 is a plan view showing an example of an arrangement of an N-well region (leak path region) in a conventional device.

FIG. 10 is a diagram showing the temperature dependence of the voltage of each part of the circuit in the conventional device.

FIG. 11 is a diagram showing an example of a distribution of an impurity concentration on a semiconductor wafer.

FIG. 12 is a circuit diagram according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing the structure of a P-type MOS-Tr forming a hysteresis circuit according to the second embodiment;

FIG. 14 is a plan view showing an example of the arrangement of an N-well region (leak path region) in the second embodiment.

FIG. 15 is a circuit diagram of a conventional example of a temperature detection circuit including a hysteresis circuit.

FIG. 16 is a temperature characteristic diagram of the voltage of each part of the circuit in the conventional example of FIG.

17 is a cross-sectional view showing a device structure of a transistor and a leak path in the conventional example of FIG.

18 is a plan view showing an example of the arrangement of N-well regions (leak path regions) in the conventional example of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Op amp 2-4 ... Resistance 5-10 ... NPN transistor 11-16 ... Leak path 17, 18 ... Resistance 22 ... Comparator 61 ... Op amp 62-64 ... Resistance 65-70 ... NPN transistor 71-76 ... Leak path 77, 78 ... Resistance 79: Dummy leak path 80: Reference voltage output terminal 81: Temperature sense output terminal 82: Reference voltage circuit 83: Comparator 301, 302 ... Resistance 303 ...
P-type MOS-Tr 304 ... N-type MOS-Tr 305-307 ... Leak path 321 ... P-type MOS-Tr 322 ... Inverter

Claims (4)

[Claims] 1. A semiconductor device comprising: a reference voltage source on one semiconductor substrate; and a voltage dividing circuit for dividing an output voltage of the reference voltage source by a resistor, and outputting the voltage divided by the voltage dividing circuit as a reference voltage. A circuit, wherein a dummy leak path having the same structure as a leak path of a junction separation surface which is parasitically generated by forming the reference voltage source is connected between a voltage dividing point of the voltage dividing circuit and a ground terminal, and A reference voltage circuit, wherein a leak path of the reference voltage source and the dummy leak path are arranged close to each other on the semiconductor substrate. 2. A semiconductor device comprising: an operational amplifier, first to fifth five resistors, a first element composed of n bipolar transistors, and n bipolar transistors on one semiconductor substrate. A second element having an emitter junction area that is A times that of the first element. Each of the bipolar transistors of the first element and the second element has a junction separated between its collector and the semiconductor substrate. The base and collector are connected and diode-connected, and the emitter of one bipolar transistor and the collector of the next bipolar transistor are sequentially connected and connected in series in n stages. One end of each of the first resistor, the second resistor, and the fourth resistor is connected to the output terminal, and the other end of the first resistor is connected to the end of the first element. And the other end of the second resistor and one end of the third resistor are connected to the inverting input terminal of the operational amplifier, and the other end of the third resistor is connected to the non-inverting input terminal of the operational amplifier. The other end of the second element is connected to one end of the second element, the other end of the fourth resistance is connected to one end of a fifth resistance and a reference voltage output terminal, and the first element and the second An emitter at an end of the element and the other end of the fifth resistor are grounded; the first element and the second element are an N-type first region formed on a P-type semiconductor substrate; The semiconductor device includes a P-type first region formed in the N-type first region, and an N-type second region formed in the P-type first region. A collector region; the P-type first region as a base region; and the N-type second region as an emitter region. A third element having the same structure as a junction isolation portion between the collector of the second element and the collector of the second element and the semiconductor substrate; and a collector region of the first element and the second element in the third element. Is connected to the reference voltage output terminal, the other end is grounded, and the respective formation regions of the first element, the second element, and the third element are arranged close to each other on the semiconductor substrate. The effect of the leakage current of the junction isolation structure between the collectors of the first and second elements and the semiconductor substrate is reduced by the effect of the leakage current of the junction isolation structure of the third element. A reference voltage circuit comprising: 3. The reference voltage circuit according to claim 2, wherein
A comparator, wherein a connection point between the fourth resistor and the fifth resistor is connected to one input terminal of the comparator, and a connection point between the third resistor and the second element is A temperature detection circuit connected to the other input terminal of the comparator and configured to detect the temperature by inverting the output of the comparator. 4. A semiconductor device comprising: an operational amplifier, first to sixth six resistors, a first element including n bipolar transistors, and n bipolar transistors on one semiconductor substrate. A second element having an emitter junction area that is A times that of the first element, wherein the first and second two identical conductive layers are formed in a substrate region insulated by junction isolation in the semiconductor substrate. And a comparator and an inverting circuit. Each of the bipolar transistors of the first element and the second element is insulated by junction separation between its collector and the semiconductor substrate. The base and collector are connected and diode-connected, and the emitter of one bipolar transistor and the collector of the next bipolar transistor are sequentially connected to form an n-stage series connection. One end of each of a first resistor, a second resistor, and a fourth resistor is connected to an output terminal of the operational amplifier, and the other end of the first resistor and the first element The other end of the second resistor is connected to the non-inverting input terminal of the operational amplifier. The other end of the second resistor and one end of the third resistor are connected to the inverting input terminal of the operational amplifier. The other end of the resistor is connected to the collector at the end of the second element, the other end of the fourth resistor is connected to one end of a fifth resistor, and the other end of the fifth resistor is connected to the sixth end. And the emitters at the ends of the first and second elements and the other end of the sixth resistor are grounded, and the connection point between the fourth resistor and the fifth resistor is connected. Above the first
And the substrate region of the first MOS transistor, and the second resistor is connected to the connection point of the fifth resistor and the sixth resistor.
Connecting the source of the second MOS transistor to the substrate region of the second MOS transistor, connecting the drains of the first and second MOS transistors to one input terminal of the comparator, 3 is connected to the other input terminal of the comparator, the output of the comparator is connected to the gate of the first MOS transistor, and the output of the comparator is connected to the other input terminal of the comparator. The second M
The first element and the second element are connected to a gate of an OS transistor, and the first element and the second element are an N-type first region formed on a P-type semiconductor substrate and a P-type region formed in the N-type first region. A first region of N-type, and a second region of N-type formed in the first region of P-type, wherein the first region of N-type is a collector region, and the first region of P-type is A base region; and the N-type second region as an emitter region. The first and second MOS transistors include an N-type first region formed on the P-type semiconductor substrate; A P-type first region and a second region formed in the N-type first region, wherein the N-type first region is a substrate region, the P-type first region is a source region, The P-type second region is a drain region, and the first and second MOS transistors are formed. Junction isolation portion between the substrate region and the semiconductor substrate that is the first
And the same structure as the junction separation portion between the collector and the semiconductor substrate in the bipolar transistor of the element and the second element, and forming regions of the first element and the second element, respectively. A temperature detection circuit, wherein a region where the first and second MOS transistors are formed is arranged at a position close to each other on the semiconductor substrate, and a temperature is detected by inverting an output of the comparator.