CN112068625A

CN112068625A - Reference voltage generating circuit

Info

Publication number: CN112068625A
Application number: CN202010446240.XA
Authority: CN
Inventors: 汤浅太刀男
Original assignee: Ablic Inc
Current assignee: Ablic Inc
Priority date: 2019-06-11
Filing date: 2020-05-25
Publication date: 2020-12-11
Also published as: JP7292117B2; TW202046045A; JP2020201754A

Abstract

The present invention provides a reference voltage generating circuit (1A) comprising: a current shunt circuit (10) having a first input terminal (11a), a second input terminal (11b), a power input terminal (12), a first output terminal (13a), a second output terminal (13b), a third output terminal (13c), an NMOS transistor (15), and PMOS transistors (16, 17, 18); a first resistance diode circuit (20) having a resistor (22), a diode (D1) and a resistor (23); a second resistor-diode circuit (30) having a resistor (32) and a diode (D2); a feedback control circuit (40) including an inverting input terminal (-), a non-inverting input terminal (+) and an output terminal (43); a resistance voltage-dividing circuit (50) including a resistance (52); and an output terminal (60) connected to the third output terminal (13c) and one end of the resistance voltage-dividing circuit (50).

Description

Reference voltage generating circuit

Technical Field

The present invention relates to a reference voltage generating circuit.

Background

There is known a reference voltage generating circuit which outputs a voltage stabilized at a predetermined voltage value as a reference voltage, without being affected by a power supply voltage or temperature. An example of the reference voltage generating circuit is disclosed in, for example, japanese patent laid-open No. 11-45125 (see patent document 1).

Fig. 8 is a circuit diagram showing an example of the configuration of a conventional reference voltage generating circuit 100, and is a circuit diagram substantially equivalent to the case where N is1, which is a case where N is one diode D2 in the reference voltage generating circuit shown in fig. 5 of patent document 1.

The reference voltage generating circuit 100 illustrated in fig. 8 includes field effect transistors (hereinafter referred to as "P-channel Metal Oxide Semiconductor (PMOS) transistors") 105 to 107 having P-type polarity,

diodes

111 and 112 and resistors 113,

diodes

115 and 116, a differential amplifier circuit 118, an output voltage circuit 120, and an output terminal 130.

The sources (sources) of the PMOS transistors 105 to 107 are connected to a power supply terminal 103 to which a power supply voltage VDD is supplied. The gates of the PMOS transistors 105 to 107 are connected to the output terminal of the differential amplifier circuit 118. The drain of the PMOS transistor 105 is connected to three points via a node N11. Specifically, as a first position, the drain of the PMOS transistor 105 is connected (grounded) to GND via a series circuit of a resistor 112 and a diode 111. As a second portion, the drain of the PMOS transistor 105 is connected (grounded) to GND via a resistor 113. As a third site, the drain of the PMOS transistor 105 is connected to the non-inverting input (+) of the differential amplifier circuit 118.

The drain of the PMOS transistor 106 is connected to three points via a node N12. Specifically, as a first portion, the drain of the PMOS transistor 106 is connected to the anode (anode) of the diode 115. The cathode (cathode) of the diode 115 is in turn connected (grounded) to GND. As a second portion, the drain of the PMOS transistor 106 is connected (grounded) to GND via a resistor 116. As a third portion, the drain of the PMOS transistor 106 is connected to the inverting input terminal (-) of the differential amplifier circuit 118.

The drain of the PMOS transistor 107 is connected to two points via a node N13. Specifically, as a first place, the drain of the PMOS transistor 107 is connected (grounded) to GND via the output voltage circuit 120 including the resistor 123. As a second portion, the drain of the PMOS transistor 107 is connected to the output terminal 130.

In the reference voltage generation circuit 100, drain currents of a predetermined ratio are output from the

PMOS transistors

105, 106, and 107. In the reference voltage generating circuit 100 configured as described above, the PMOS transistor 107 and the resistor 123 are removed from the entire circuit to form a feedback control circuit. As a result, the reference voltage generation circuit 100 operates as a band gap reference (band gap reference) circuit.

The drain current of the PMOS transistor 105 branches at the node N11 and flows through the resistor 113 and the series circuit of the resistor 112 and the diode 111, respectively. The drain current of the PMOS transistor 106 branches at node N12 and flows through the diode 115 and the resistor 116, respectively. The drain current of the PMOS transistor 107 flows through the resistor 123. Therefore, in the reference voltage generating circuit 100, a voltage equal to a voltage drop in the resistor 123 can be obtained as the output voltage VOUT.

[ Prior art documents ]

[ patent document ]

Patent document 1: japanese patent laid-open publication No. 11-45125

Disclosure of Invention

[ problems to be solved by the invention ]

However, the reference voltage generating circuit 100 illustrated in fig. 8 has the following problems: when the power supply voltage VDD sharply rises or falls, a voltage having a large amplitude although transient is superimposed on the output voltage VOUT. For example, when the power supply voltage VDD is changed from 1.5V to 6.0V or from 6.0V to 1.5V for several μ s, a variation in amplitude of several tens mV to several hundreds mV is superimposed on the output voltage VOUT.

The output of the reference voltage generation circuit is often used as a voltage reference for operation of other circuits. For example, the reference voltage is used as a reference for an output voltage of a power supply voltage output circuit such as a Low Dropout Regulator (LDO) or a Direct Current/Direct Current (DC/DC) converter (converter), or as a reference for an offset voltage or an amplitude voltage of a signal processing circuit such as an amplifier circuit or a filter (filter). The output voltages of these circuits that operate with the output voltage of the reference voltage generating circuit as a reference are affected by the variation of the output voltage of the reference voltage generating circuit, and vary in an equal or proportional relationship. Thus, the smaller the variation in the output voltage of the reference voltage generation circuit, the better the variation in the operation of the other circuits, and the error.

In order to solve the above-described problems, it is an object of the present invention to provide a reference voltage generating circuit capable of reducing amplitude variation of an output voltage due to a rapid variation even when a power supply voltage varies rapidly.

[ means for solving problems ]

In order to solve the problem, a reference voltage generating circuit of the present invention includes: a current shunt circuit having a first input terminal and a second input terminal, a power input terminal, first to third output terminals, a first field effect transistor, a second field effect transistor, a third field effect transistor, and a fourth field effect transistor, the first field effect transistor including a gate connected to the first input terminal, a drain connected to the power input terminal, and a source, and being electrically connected to a first power source via the power input terminal, the second field effect transistor including a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the first output terminal, the third field effect transistor having a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the second output terminal, the fourth field effect transistor has a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the third output terminal; a first resistor-diode circuit having a resistor and a diode, one end of which is connected to the first output terminal of the current shunt circuit, and the other end of which is connected to a second power supply; a second resistor-diode circuit having a resistor and a diode, one end of which is connected to the second output terminal of the current shunt circuit, and the other end of which is connected to the second power supply; a feedback control circuit including a first input terminal connected to the one end of the first resistance diode circuit, a second input terminal connected to the one end of the second resistance diode circuit, and an output terminal connected to the first input terminal of the current shunt circuit; a resistance circuit having a resistance, one end of which is connected to the third output terminal of the current dividing circuit, and the other end of which is connected to the second power supply; and an output terminal connected to the third output terminal of the current dividing circuit and the one end of the resistor circuit, wherein the first field effect transistor has a first polarity which is one of an n-type and a p-type, and the second to fourth field effect transistors have a second polarity which is the other of the n-type and the p-type.

In the reference voltage generating circuit, the resistor circuit includes a first resistor and a second resistor connected in series, and the resistor divider circuit is connected between a connection point of the first resistor and the second input terminal of the current dividing circuit.

In the above-described reference voltage generating circuit, the second input terminal of the current dividing circuit is electrically connected to the second power supply.

The reference voltage generating circuit includes: at least one phase compensation circuit selected from the first phase compensation circuit, the second phase compensation circuit, and the third phase compensation circuit. The first phase compensation circuit includes a capacitor and is connected between the output terminal of the feedback control circuit and the second power supply. The second phase compensation circuit includes a capacitor and is connected between the output terminal and the second power source. The third phase compensation circuit includes a capacitor and is connected between the second input terminal and the third output terminal of the current splitting circuit.

The reference voltage generating circuit includes: at least one phase compensation circuit selected from the fourth phase compensation circuit and the fifth phase compensation circuit. The fourth phase compensation circuit includes a capacitor and is connected between the first output terminal of the current splitting circuit and the first resistance diode circuit, and between the second power supply. The fifth phase compensation circuit includes a capacitor and is connected between the second output terminal of the current dividing circuit and the second resistance diode circuit and between the second power supply.

The reference voltage generating circuit includes: a resistor connected between the second input of the feedback control circuit and the one end of the second resistive diode circuit.

In the reference voltage generating circuit, the feedback control circuit may include a differential amplifier circuit that amplifies a difference between a first input voltage input to the first input terminal and a second input voltage input to the second input terminal, and outputs a voltage amplified by the differential amplifier circuit from the output terminal.

[ Effect of the invention ]

According to the present invention, even when the power supply voltage fluctuates rapidly, the amplitude fluctuation of the output voltage due to the fluctuation can be reduced.

Drawings

Fig. 1 is a circuit diagram showing a first configuration example of a reference voltage generating circuit according to a first embodiment.

Fig. 2 is a circuit diagram showing a second configuration example of the reference voltage generating circuit according to the first embodiment.

Fig. 3 is a circuit diagram showing an example of the configuration of the reference voltage generating circuit according to the second embodiment.

Fig. 4 (a) and 4 (B) are circuit diagrams each showing a configuration example of a phase compensation circuit connected between a current shunt circuit and a resistance diode circuit.

Fig. 5 is a circuit diagram showing an example of the configuration of the reference voltage generating circuit according to the third embodiment.

Fig. 6 is a circuit diagram showing an example of the configuration of the reference voltage generating circuit according to the first modification.

Fig. 7 is a circuit diagram showing an example of the configuration of a reference voltage generating circuit according to a second modification.

Fig. 8 is a circuit diagram showing an example of a conventional reference voltage generating circuit.

[ description of symbols ]

1A to 1F: reference voltage generating circuit

3. 103: power supply terminal

10. 80, 90: current shunt circuit

11 a: input terminal (first input terminal)

11 b: input terminal (second input terminal)

81. 91a, 91 b: input terminal

12. 82a to 82 c: power input terminal

13 a: output (first output)

13 b: output (second output)

13 c: output (third output)

43. 83a to 83c, 93a to 93 c: output end

15. 85-87, 96-98: NMOS transistor

16-18, 95, 105-107: PMOS transistor

20: resistance diode circuit (first resistance diode circuit)

22. 23, 32, 51, 52, 77, 112, 113, 116, 123, 741, 751: resistance (RC)

30: resistance diode circuit (second resistance diode circuit)

40: feedback control circuit

41. 118: differential amplifier circuit

50: resistance voltage-dividing circuit (resistance circuit)

55: resistance circuit

57: voltage source

60. 130, 130: output terminal

71-75: phase compensation circuit

100: reference voltage generating circuit

111. 115, D1, D2: diode with a high-voltage source

120: output voltage circuit

742. 752, C1-C3: capacitor with a capacitor element

I1-I5, Id 1-Id 3: electric current

Is 1-Is 3: source current

N1-N5, N11-N13: node point

P1, P2: connection point

VD 1: voltage across diode D1

VD 2: voltage across diode D2

VDD: supply voltage

VN1, VN 2: voltage of

VOUT: output voltage

Detailed Description

Hereinafter, a reference voltage generating circuit according to an embodiment of the present invention will be described with reference to the drawings.

[ first embodiment ]

Fig. 1 is a circuit diagram showing a configuration of a reference voltage generating circuit 1A as an example of a reference voltage generating circuit according to a first embodiment.

The reference voltage generating circuit 1A includes a current dividing circuit 10, a resistance diode circuit 20, a resistance diode circuit 30, a feedback control circuit 40, a resistance voltage dividing circuit 50, and an output terminal 60. In the reference voltage generation circuit 1A, a power supply terminal 3 electrically connected to the first power supply and a ground terminal electrically connected (grounded) to GND as the second power supply are arranged.

The current shunt circuit 10 has an input terminal 11a as a first input terminal, an input terminal 11b as a second input terminal, a power supply input terminal 12, an output terminal 13a as a first output terminal, an output terminal 13b as a second output terminal, and an output terminal 13c as a third output terminal.

The resistor-diode circuit 20 as a first resistor-diode circuit has one end connected to the node N1 and the other end grounded. The resistor-diode circuit 30 as a second resistor-diode circuit has one end connected to the node N2 and the other end grounded.

The feedback control circuit 40 includes: a differential amplifier circuit 41 including an inverting input terminal (-) connected to the output terminal 13a as a first input terminal, a non-inverting input terminal (+) connected to the output terminal 13b as a second input terminal, and an output terminal; and an output terminal 43 connected to the output terminal of the differential amplifier circuit 41.

The resistance voltage divider circuit 50 as a resistance circuit includes a resistor 51 and a resistor 52 connected in series, one end of the resistor 51 side end is connected to the output terminal 13c, and the other end of the resistor 52 side end is grounded.

The output terminal 13a is connected to the node N1, and is connected to one terminal of the resistor diode circuit 20 and the inverting input terminal of the differential amplifier circuit 41 via the node N1. The output terminal 13b is connected to the node N2, and is connected to one terminal of the resistor diode circuit 30 and the non-inverting input terminal of the differential amplifier circuit 41 via the node N2. In addition, the output terminal 43 is connected to the input terminal 11 a. Thus, a feedback loop (loop) is formed by the current shunt circuit 10 and the feedback control circuit 40.

The current shunt circuit 10 is connected to the resistance diode circuit 20 via a node N1, and is connected to the resistance diode circuit 30 via a node N2.

The input terminal 11b is connected to a node N3 which is a connection point of the resistor 51 and the resistor 52. The output terminal 13c is connected to one end of the resistance voltage divider circuit 50. Therefore, the current shunt circuit 10 is connected so that a voltage can be input from the resistance voltage divider circuit 50 and a voltage can be output to the resistance voltage divider circuit 50. An output terminal 60 is connected to a connection point between the output terminal 13c and one end of the resistance voltage divider circuit 50. Further, the power supply input terminal 12 is connected to the power supply terminal 3 to which the power supply voltage VDD is supplied.

Next, each circuit of the current dividing circuit 10, the resistance diode circuit 20, the resistance diode circuit 30, the feedback control circuit 40, and the resistance voltage dividing circuit 50 will be described.

The current shunt circuit 10 includes a field effect transistor (hereinafter referred to as an "NMOS transistor") 15 having an n-type polarity and field effect transistors (PMOS transistors) 16 to 18 having a p-type polarity, in addition to the input terminal 11a, the input terminal 11b, the power supply input terminal 12, and the output terminals 13a to 13 c.

The NMOS transistor 15 as the first field effect transistor has one of n-type and p-type polarities, i.e., n-type polarity as the first polarity. The NMOS transistor 15 includes a gate connected to the input terminal 11a, a drain connected to the power input terminal 12, and a source.

The PMOS transistor 16 as the second field effect transistor has the other of the n-type and p-type polarity, i.e., the p-type polarity as the second polarity. The PMOS transistor 16 includes a gate, a source connected to the source of the NMOS transistor 15, a back gate (back gate) connected (short-circuited) to the source, and a drain connected to the output terminal 13 a.

The PMOS transistor 17 as the third field effect transistor has a p-type polarity as the second polarity, and includes a gate, a source connected to the source of the NMOS transistor 15, a back gate connected to the source, and a drain connected to the output terminal 13 b.

The PMOS transistor 18 as the fourth field effect transistor has p-type polarity as the second polarity, and includes a gate, a source connected to the source of the NMOS transistor 15, a back gate connected to the source, and a drain connected to the output terminal 13 c.

The gate width of the PMOS transistor 17 is p (p is an arbitrary positive number) times larger than the gate width/gate length of the PMOS transistor 16 (hereinafter referred to as "gate width/gate length"). The gate width/gate length of the PMOS transistor 18 is q (q is an arbitrary positive number) times larger than the gate width/gate length of the PMOS transistor 17. That is, the ratio of the gate width/gate length of each of the

PMOS transistors

16, 17, 18 is 1: p: p.q.

The PMOS transistor 16 is connected to the gates of the

PMOS transistors

17 and 18 and the input terminal 11 b. The PMOS transistor 17 is connected to the gates of the

PMOS transistors

16 and 18 and the input terminal 11 b. The PMOS transistor 18 is connected to the gates of the

PMOS transistors

16 and 17 and the input terminal 11 b.

The resistor-diode circuit 20 includes a diode D1 and a resistor 22 forming a first current path (hereinafter referred to as a "path"), and a resistor 23 forming a second path. The first path is connected in parallel with the second path in the resistor diode circuit 20.

The first path is a path connecting node N1 and GND via resistor 22 and diode D1. In the first path, the node N1 is connected to one end of the resistor 22, and the other end of the resistor 22 is connected to the anode of the diode D1 and to the cathode of the diode D1. The cathode of diode D1 is connected to ground.

The second path is a path connecting node N1 and GND via resistor 23. In the second path, node N1 is connected to one end of resistor 23. The other end of the resistor 23 is connected to ground.

The resistance diode circuit 30 has a diode D2 and a resistor 32 connected in parallel between the node N2 and GND. The anode of the diode D2 is connected to the node N2, and the cathode is grounded. The area of the junction of the diode D2 is one-half (1/n) times (n is an arbitrary positive number) the area of the junction of the diode D1. In other words, the area of the junction of the diode D1 is n times the area of the junction of the diode D2. Resistor 32 has one end connected to node N2 and the other end connected to ground.

In the feedback control circuit 40, a first input terminal of the feedback control circuit 40 is connected to an inverting input terminal of the differential amplifier circuit 41. A second input terminal of the feedback control circuit 40 is connected to a non-inverting input terminal of the differential amplifier circuit 41.

The resistance voltage divider circuit 50 is a voltage divider circuit that obtains a divided voltage of the output voltage VOUT input to the output terminal 60 through a resistance 51 and a resistance 52 connected in series. The divided voltage of the output voltage VOUT is the voltage of the node N3.

Next, the operation and effect of the reference voltage generating circuit 1A will be described.

In the reference voltage generating circuit 1A, the current shunt circuit 10 generates the current Id1, the current Id2, and the current Id3 based on the voltage input from the input terminal 11A, the power supply voltage VDD input from the power supply input terminal 12, and the bias voltage input from the input terminal 11 b.

More specifically, the NMOS transistor 15 generates the current Id based on the voltage input from the input terminal 11a and the power supply voltage VDD input from the power supply input terminal 12. The generated current Id flows into the sources of the PMOS transistor 16, the PMOS transistor 17, and the PMOS transistor 18, respectively. The voltage input from the input terminal 11b is applied as a bias voltage to the gates of the

PMOS transistors

16, 17, and 18.

The PMOS transistor 16 draws a current Id1 from the drain based on the current input to the source and the bias voltage applied to the gate. The PMOS transistor 17 draws a current Id2 from the drain based on the current input to the source and the bias voltage applied to the gate. The PMOS transistor 18 draws a current Id3 from the drain based on the current input to the source and the bias voltage applied to the gate. The current ratio of the currents Id1, Id2 and Id3 is equal to the ratio of the gate width/gate length of the

PMOS transistors

16, 17 and 18, which is 1: p: p.q.

A current Id1 as a drain current is output from the output terminal 13a and flows into the resistor diode circuit 20. The current Id1 flowing into the resistor-diode circuit 20 is divided into the current I1 flowing through the resistor 23 and the current I2 flowing through the resistor 22 and the diode D1 via the node N1, and flows to GND.

The current Id2 as the drain current is output from the output terminal 13b and flows into the resistor diode circuit 30. The current Id2 flowing into the resistor-diode circuit 30 flows to GND through the node N2, and is divided into the current I3 flowing through the diode D2 and the current I4 flowing through the resistor 32.

The current Id3 as a drain current is output from the output terminal 13c and flows into the resistance voltage divider circuit 50. The current Id3 is equal to the current I5 flowing through the resistance voltage divider circuit 50, and flows to GND via the resistance 51 and the resistance 52. At a node N3, which is a connection point of the resistor 51 and the resistor 52, a divided voltage according to a resistance ratio of the resistor 51 and the resistor 52 is generated by a current flowing through the resistor 51 and the resistor 52. The divided voltage is supplied to the input terminal 11b as a bias voltage.

In addition, the voltage VN1 at the node N1 and the voltage VN2 at the node N2 are input to the feedback control circuit 40. More specifically, the voltage VN1 as the first input voltage is input to the inverting input terminal of the differential amplifier circuit 41, and the voltage VN2 as the second input voltage is input to the non-inverting input terminal of the differential amplifier circuit 41. The differential amplifier circuit 41 supplies a voltage proportional to the difference between two voltages input to the inverting input terminal and the non-inverting input terminal to the output terminal 43. The voltage supplied to the output terminal 43 is applied to the gate of the NMOS transistor 15 as an output voltage of the feedback control circuit 40 via the input terminal 11a of the current dividing circuit 10.

Further, an output voltage VOUT is output from the output terminal 60. The output voltage VOUT is obtained by solving the output voltage VOUT with the circuit equation set to vertical. The resistances of the resistor 22, the resistor 23, the resistor 32, the resistor 51, and the resistor 52 are set to R1, R2, R3, R4, and R5, respectively, each time the circuit equation is set to vertical. Voltages at both ends of the diode D1 and the diode D2 are VD1 and VD2, respectively. The thermal voltage VT is kB · T/qe (kB is Boltzmann constant, T is absolute temperature, qe is elementary charge). The reverse saturation currents of the diode D1 and the diode D2 are. The offset voltage (offset voltage) of the differential amplifier circuit 41 is Voffset. The following equations (1) to (7) can be obtained according to the conditions.

[ mathematical formula 1]

When the output voltage VOUT is solved using the above equations (1) to (7), the following equation (8) is obtained.

[ mathematical formula 2]

The equation of equation (8) includes the voltage VN1 of the node N1 and the voltage VN2 of the node N2, and thus cannot be said to be solved specifically for equation (8). Therefore, reference is further made to circuit conditions taking into account the actual usage form of the reference voltage generating circuit 1A. In general, in the differential amplifier circuit 41, two voltages input to the inverting input terminal and the non-inverting input terminal are substantially equal to each other. Therefore, the voltage VN1 input to the inverting input terminal and the voltage VN2 input to the non-inverting input terminal are regarded as being approximately equal to further clarify the right term of the expression (8). If the right term of the equation (8) is further modified, the output voltage VOUT is expressed by the following equation (9).

[ mathematical formula 3]

As can be seen from the equation (9), the output voltage VOUT can be set by a circuit constant. Therefore, the reference voltage generating circuit 1A has a large degree of freedom in circuit design. Here, it is assumed that the characteristic of the reference voltage generating circuit 1A is ideal, that is, the impedance (impedance) of the load connected to the output terminal 60 is infinite. If the characteristics of the reference voltage generation circuit 1A are ideal, the current Id3 flows through the resistance voltage division circuit 50 in its entirety, and therefore the current Id3 is equal to the current I5 flowing through the series-connected resistor 51 and resistor 52. Therefore, the output voltage VOUT is obtained by a product of the resistance value between one end and the other end of the resistor voltage-dividing circuit 50, that is, the resistance value of a resistor in which the resistor 51 and the resistor 52 are connected in series (R4 · R5/(R4+ R5)), and the current I5 (current Id 3).

On the other hand, the

resistors

22, 23, 32, 51, and 52 used in actual electronic circuits are not necessarily ideal characteristics, and the resistance values may vary depending on the operating conditions such as the ambient temperature and the potential difference between the resistor elements and the power supply voltage VDD or the ground potential. The resistance values R1 to R5 of the resistor 22, the resistor 23, the resistor 32, the resistor 51, and the resistor 52 appear as ratios to each other in the right term of the formula (9). Thus, the output voltage VOUT may be determined according to a relative value of the resistance values of the resistors of each other, rather than an absolute value of the resistance values of the resistors of each other.

In terms of the relative accuracy of the resistance value, when the resistance value is formed on an Integrated Circuit (IC), an accuracy difference as high as about 1/1000 is often obtained. Therefore, the characteristics of the output voltage VOUT are hardly affected by the variation characteristics of the resistance, and high accuracy can be obtained.

In addition, according to the above equation (9), the current IOUT flowing through the output terminal 60 is expressed by the following equation (10).

[ mathematical formula 4]

According to the equation (10), the output current IOUT directly affects the absolute accuracy of the resistance value R1 of the resistor 23. When the resistance value R1 of the resistor 23 can be accurately obtained without being affected by the environmental temperature or the operating conditions such as the potential difference with the power supply voltage VDD or the ground potential, the output current IOUT can be obtained with high accuracy. In other words, in this case, the reference voltage generating circuit 1A can function as a reference current generating circuit.

In this way, in the reference voltage generating circuit 1A, the NMOS transistor 15 generates the current Id based on the output of the feedback control circuit 40. Based on the current Id, currents Id1, Id2, and Id3 supplied to the resistor diode circuit 20, the resistor diode circuit 30, and the resistor voltage divider circuit 50 are generated.

The NMOS transistor 15 has a drain connected to the power supply terminal 3, but the remaining gate, back gate, and source are not connected to the power supply terminal 3. In general, an internal resistance between a drain and a source of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is, for example, several M Ω, and thus, the influence of a variation in the power supply voltage VDD on the current Id is limited.

Therefore, in the reference voltage generation circuit 1A, even if the power supply voltage VDD, which is the drain voltage of the NMOS transistor 15, suddenly changes, the ratio of the voltage superimposed on the current Id due to the fluctuation of the power supply voltage VDD can be reduced.

In the reference voltage generating circuit 1A, since the voltage VN1 and the voltage VN2 are input to the differential amplifier circuit 41, the in-phase component of the input signal can be cancelled (cancel). Therefore, even if fluctuations due to sudden changes in power supply voltage VDD overlap each of voltage VN1 and voltage VN2, the fluctuations can be eliminated. Further, in the reference voltage generating circuit 1A, the divided voltage of the stabilized output voltage VOUT is input to the gates of the

PMOS transistors

16, 17, and 18 via the input terminal 11 b. Thereby, the

PMOS transistors

16, 17, and 18 can stably operate.

Therefore, according to the reference voltage generation circuit 1A, even when the power supply voltage VDD fluctuates rapidly, the amplitude fluctuation of the output voltage VOUT due to the fluctuation can be reduced. In addition, according to the reference voltage generation circuit 1A, by appropriately selecting the PMOS transistor 16, the PMOS transistor 17, and the PMOS transistor 18, the ratio (shunt ratio) of the current Id1, the current Id2, and the current Id3 can be arbitrarily selected.

In the reference voltage generating circuit 1A, the bias voltage input from the input terminal 11b to the current shunt circuit 10 is a divided voltage of the output voltage VOUT derived from the resistance voltage dividing circuit 50, but is not limited thereto. As described with reference to fig. 2, the input bias voltage may not necessarily be a divided voltage of the output voltage VOUT.

Fig. 2 is a circuit diagram showing the configuration of a reference voltage generating circuit 1B as another example of the reference voltage generating circuit of the first embodiment.

The reference voltage generating circuit of the present embodiment may be configured to input a voltage generated by a voltage source that supplies a predetermined voltage to the input terminal 11B, as in the reference voltage generating circuit 1B, for example. The reference voltage generating circuit 1B differs from the reference voltage generating circuit 1A in that a resistance circuit 55 is provided instead of the resistance voltage dividing circuit 50, and a source for supplying the bias voltage is not the resistance voltage dividing circuit 50 but an external voltage source 57, and the other points are the same.

The resistor circuit 55 is configured by omitting the resistor 52 from the resistor voltage-dividing circuit 50, that is, by including the resistor 51. The voltage source 57 includes a negative terminal connected to GND and a positive terminal connected to the input terminal 11b as a second input terminal. According to the reference voltage generating circuit 1B configured as described above, even when the divided voltage of the output voltage VOUT is not applied from the input terminal 11B, the same effect as that of the reference voltage generating circuit 1A can be obtained.

In addition, although the reference voltage generating circuit 1B has been described as the case where the input terminal 11B is connected to the voltage source 57, the input terminal 11B and the voltage source 57 do not necessarily need to be connected. The reference voltage generation circuit 1B may be configured to input the output voltage VOUT to the input terminal 11B, for example, in such a manner that the input terminal 11B is not connected to the voltage source 57 but is connected to the output terminal 13c (the input terminal 11B and the output terminal 13c are short-circuited). If the design conditions do not allow this, the input terminal 11b may be electrically connected to GND.

In this way, in the reference voltage generating circuit 1B in which the output terminal 13c and the input terminal 11B are connected (short-circuited), the reference voltage generating circuit 1B electrically connected to the voltage source 57, and the reference voltage generating circuit 1B electrically connected to GND, the influence of the sudden change of the power supply voltage VDD can be reduced, and the circuit configuration can be simplified.

[ second embodiment ]

Fig. 3 is a circuit diagram showing a configuration of a reference voltage generating circuit 1C as an example of a reference voltage generating circuit according to a second embodiment.

The reference voltage generating circuit 1C is different from the reference voltage generating circuit 1A in that it further includes phase compensation circuits 71 to 75 and a resistor 77, and is otherwise the same. Therefore, in the present embodiment, the phase compensation circuits 71 to 75 and the resistor 77 are mainly described, and redundant description with the reference voltage generating circuit 1A is omitted. In fig. 3, from the viewpoint of ensuring the clarity of the drawing, some of the constituent elements such as the input terminal 11A and the input terminal 11b that overlap with the reference voltage generating circuit 1A are omitted.

The phase compensation circuit 71 as a first phase compensation circuit includes a capacitor C1, and is connected between an output terminal (not shown in fig. 3) of the feedback control circuit 40 and GND. The phase compensation circuit 72 as a second phase compensation circuit includes a capacitor C2, and is connected between the output terminal 60 and GND. The phase compensation circuit 73 as a third phase compensation circuit includes a capacitor C3, and is connected between a node N4 corresponding to the input terminal 11b not shown in fig. 3 and a node N5 corresponding to the output terminal 13C not shown in fig. 3.

The phase compensation circuit 74 as a fourth phase compensation circuit is connected to the connection point P1. The node P1 is disposed between the drain of the PMOS transistor 16 and one end of the resistor-diode circuit 20, more specifically, the node N1. The phase compensation circuit 75 as a fifth phase compensation circuit is connected to the connection point P2. The connection point P2 is connected between the drain of the PMOS transistor 17 and one end of the resistor-diode circuit 30, more specifically, the node N2. As shown in fig. 4 (a) and 4 (B), the phase compensation circuit 74 and the phase compensation circuit 75 are configured to include at least a capacitor 742 and a capacitor 752.

The resistor 77 is connected between the non-inverting input terminal of the differential amplifier circuit 41 and one end of the resistor diode circuit 30, more specifically, between the nodes N2.

In the reference voltage generating circuit 1C configured as described above, the phase compensation circuits 71 to 75 have a large margin in phase. In the

phase compensation circuits

71 and 72, one ends of the capacitors C1 and C2 are also ac-grounded (grounded) to GND which is a ground point. Accordingly, the phase compensation circuit 71 and the phase compensation circuit 72 increase the margin of the phase, and improve the stability of the sudden change of the node in the reference voltage generation circuit 1C with respect to the power supply voltage VDD.

In the phase compensation circuit 73, since the drain of the PMOS transistor 18 is connected to the gate thereof and further to the resistance voltage divider circuit 50, the capacitor C3 can obtain a mirror effect. The mirror effect causes the phase compensation circuit 73 to function similarly to the case where a capacitor equal to or larger than the actual capacitance of the capacitor C3 is connected.

The resistor 77 reduces the difference between the ac impedances seen from the two input terminals of the differential amplifier circuit 41 to the outside.

When the diode D1 is considered to be an ideal diode, the first ac impedance viewed from the inverting input terminal of the differential amplifier circuit 41 to the outside is substantially equal to the resistance value of the resistor 22. When the resistor 77 is not present and the diode D2 is regarded as an ideal diode, the second ac impedance seen from the non-inverting input terminal of the differential amplifier circuit 41 to the outside is substantially zero. Therefore, when the resistor 77 having a resistance value equal to the resistance value of the resistor 22 is connected between the non-inverting input terminal of the differential amplifier circuit 41 and GND, the first ac impedance and the second ac impedance can be substantially matched.

According to the reference voltage generating circuit 1C, since the phase compensation circuits 71 to 75 are provided, the feedback control circuit 40 for negative feedback can prevent the phase from largely varying within the band bandwidth and substantially changing to positive feedback. Therefore, the reference voltage generating circuit 1C can prevent the circuit operation from becoming unstable or abnormal operation such as an oscillating operation from occurring. That is, according to the reference voltage generating circuit 1C, the stability of the circuit operation can be improved.

In the reference voltage generating circuit 1C, the phase compensating circuit 71 and the phase compensating circuit 72 can increase the margin of the phase and improve the stability of the sudden change of the node in the reference voltage generating circuit 1C with respect to the power supply voltage VDD.

Since the phase compensation circuit 73 functions similarly to the case where a capacitor equal to or larger than the actual capacitance of the capacitor C3 is connected, the margin of the phase can be further increased. In other words, the capacitor C3 can be selected to have a capacitance value smaller than the capacitance value required for operation. In this case, the occupied area and volume of the circuit can be reduced.

Further, since the reference voltage generating circuit 1C includes the resistor 77, the difference between the first ac impedance and the second ac impedance can be reduced. In addition, when the resistor 77 has a resistance value equal to that of the resistor 22, the reference voltage generating circuit 1C can make the first ac impedance and the second ac impedance substantially equal to each other.

The phase compensation circuit 71, the phase compensation circuit 72, and the phase compensation circuit 73 illustrated in fig. 3 are configured to include only the capacitor C1, the capacitor C2, and the capacitor C3, respectively, but are not limited to this example. The phase compensation circuit 71, the phase compensation circuit 72, and the phase compensation circuit 73 may be configured to include a capacitor C1, a capacitor C2, and a capacitor C3, respectively. That is, the phase compensation circuits 71 to 73 may include a series circuit of a capacitor and a resistor.

The

phase compensation circuits

74 and 75 are also similar to the phase compensation circuits 71 to 73. That is, the phase compensation circuit 74 may include a resistor 741 connected in series to the capacitor 742, as illustrated in fig. 4 (a). The phase compensation circuit 75 may include a resistor 751 connected in series to the capacitor 752 as illustrated in fig. 4 (B). In the phase compensation circuit 74 in which the capacitor 742 and the resistor 741 are connected in series, the positional relationship between the resistor 741 and the capacitor 742 is not limited to the positional relationship illustrated in fig. 4 (a). The positional relationship may be reversed as illustrated in fig. 4 (a). The positional relationship between the resistor 751 and the capacitor 752 is similar to the positional relationship between the resistor 741 and the capacitor 742.

[ third embodiment ]

Fig. 5 is a circuit diagram showing a configuration of a reference voltage generating circuit 1D as an example of a reference voltage generating circuit according to a third embodiment.

The reference voltage generating circuit 1D differs from the reference voltage generating circuit 1A in that a current dividing circuit 80 is provided in place of the current dividing circuit 10, and a resistance circuit 55 is provided in place of the resistance voltage dividing circuit 50, but is otherwise the same. The resistor circuit 55 is a component provided in the reference voltage generating circuit 1B, as described in the first embodiment. Therefore, in the present embodiment, the description is mainly given of the current dividing circuit 80, and the description overlapping with the reference voltage generating circuit 1A and the reference voltage generating circuit 1B is omitted.

The current shunt circuit 80 has an input terminal 81 connected to the output terminal 43, power input terminals 82a to 82c connected to the power supply terminal 3, output terminals 83a to 83c, and NMOS transistors 85 to 87.

The output terminal 83a is connected to one terminal of the resistor-diode circuit 20, more specifically, to the node N1. The output terminal 83b is connected to one terminal of the resistor-diode circuit 30, and more specifically, to the node N2. The output terminal 83c is connected to one terminal of the resistor circuit 55, that is, one terminal of the resistor 51.

The NMOS transistor 85 includes a gate connected to the input terminal 81, a drain connected to the power input terminal 82a, and a source connected to the output terminal 83 a. The NMOS transistor 86 includes a gate connected to the input terminal 81, a drain connected to the power input terminal 82b, and a source connected to the output terminal 83 b. The NMOS transistor 87 includes a gate connected to the input terminal 81, a drain connected to the power supply input terminal 82c, and a source connected to the output terminal 83 c.

The value of the gate width/gate length of the NMOS transistor 86 is p (p is an arbitrary positive number) times as large as the value of the gate width/gate length of the NMOS transistor 85. The gate width/gate length of the NMOS transistor 87 is q (q is an arbitrary positive number) times the gate width/gate length of the NMOS transistor 86. That is, the ratio of the gate width/gate length of each of the NMOS transistor 85, the NMOS transistor 86, and the NMOS transistor 87 is 1: p: p.q.

The reference voltage generation circuit 1D configured as described above differs from the reference voltage generation circuit 1A in which bias voltages are input to the gates of the

PMOS transistors

16, 17, and 18, respectively, in that no bias voltage is input to the gates of the

NMOS transistors

85, 86, and 87, respectively. That is, the configuration of the reference voltage generating circuit 1D is simpler than that of the reference voltage generating circuit 1A.

On the other hand, due to the difference, in the reference voltage generating circuit 1D, in order to satisfy the expression (9), the magnitudes of the source current Is1, the source current Is2, and the source current Is3 must be constantly maintained at 1: p: p.q. That is, the voltage VN1 and the voltage VN2 must be constant and substantially the same value.

In the reference voltage generating circuit 1D, the current shunt circuit 80 generates the source current Is1, the source current Is2, and the source current Is3 based on the output of the differential amplifier circuit 41. The source current Is1, the source current Is2, and the source current Is3 are output from the output terminal 83a, the output terminal 83b, and the output terminal 83c, respectively.

The source current Is1 Is divided into current I1 and current I2 at node N1. Current I1 flows to GND via resistor 23. The current I2 flows to GND through the resistor 22 and the diode D1.

The source current Is2 Is divided into current I3 and current I4 at node N2. The current I3 flows to GND via the diode D2. Current I4 flows to GND via resistor 32.

The source current Is3 Is equal to the current I5 flowing through the resistor 51, and flows to GND through the resistor 51.

The NMOS transistors 85 to 87 have drains connected to the power supply terminal 3, and gates, back gates, and sources not connected to the power supply terminal 3. The internal resistances between the drain and the source of the NMOS transistors 85 to 87 are, for example, several M Ω. Therefore, even if the power supply voltage VDD fluctuates rapidly, the current shunt circuit 80 can generate the source current Is1, the source current Is2, and the source current Is3 in which the fluctuations are suppressed.

According to the reference voltage generating circuit 1D, even if the power supply voltage VDD suddenly changes, it Is possible to suppress sudden changes in the source currents Is1, Is2, and Is 3.

The present invention is not limited to the above-described embodiments, and may be implemented in various forms other than the examples described above at the stage of implementation, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention.

For example, the reference voltage generating circuit may be configured by replacing the polarities of the transistors and the power supply terminal 3 with GND with respect to the reference voltage generating circuit 1A to the reference voltage generating circuit 1D.

Fig. 6 and 7 are circuit diagrams showing configuration examples of the reference voltage generating circuit 1E of the first modification and the reference voltage generating circuit 1F of the second modification, respectively.

The reference voltage generating circuit 1E includes a current shunt circuit 90, a capacitor C1, a capacitor C2, a capacitor C3, a diode D1, a resistor 22, a resistor 23, a diode D2, a resistor 32, a differential amplifier circuit 41, a resistor 51, a resistor 52, and a resistor 77, which are included in the phase compensation circuit 71, the phase compensation circuit 72, and the phase compensation circuit 73, respectively.

In other words, the reference voltage generating circuit 1E is a circuit in which the polarities of the transistors and the power supply terminals 3 and GND are switched in the reference voltage generating circuit 1C in which the phase compensating circuit 74 and the phase compensating circuit 75 are omitted. Therefore, the current shunt circuit 90 is a circuit in which the polarities of the transistors and the power supply terminals 3 and GND are switched with respect to the current shunt circuit 10, and includes a PMOS transistor 95 and three NMOS transistors 96 to 98.

The PMOS transistor 95 as the first field effect transistor is switched from n-type to p-type in polarity with respect to the NMOS transistor 15. That is, the PMOS transistor 95 has one of n-type and p-type polarities, i.e., p-type polarity as the first polarity.

The NMOS transistor 96 as the second field effect transistor is switched from a p-type to an n-type in polarity with respect to the PMOS transistor 16. That is, the NMOS transistor 96 has the other of the n-type and p-type polarities, i.e., the n-type polarity as the second polarity.

The NMOS transistor 97 as the third field effect transistor switches the polarity of the transistor from p-type to n-type with respect to the PMOS transistor 17, and has n-type polarity as the second polarity. The NMOS transistor 98 as the fourth field effect transistor switches the polarity of the transistor from p-type to n-type with respect to the PMOS transistor 18, and has n-type polarity as the second polarity.

The reference voltage generating circuit 1E can obtain the same effect as the reference voltage generating circuit 1C. In the reference voltage generating circuit 1E, as in the reference voltage generating circuit 1C, part or all of the capacitor C1, the capacitor C2, and the capacitor C3 may be omitted, or the resistor 77 may be omitted. In addition, at least one of the phase compensation circuit 74 and the phase compensation circuit 75 may be additionally provided in the reference voltage generation circuit 1E.

Further, in the reference voltage generating circuit 1B, the polarity of the transistor and the power supply terminal 3 may be switched with GND to constitute a reference voltage generating circuit 1F. The reference voltage generating circuit 1F can obtain the same effects as the reference voltage generating circuit 1B.

In addition, at least one of the phase compensation circuits 71 to 75 and the resistor 77 may be additionally provided to the reference voltage generating circuit 1F. In addition, the voltage source 57 may be omitted from the reference voltage generating circuit 1F.

In the self-feedback circuits such as the reference voltage generating circuit 1A to the reference voltage generating circuit 1F, there is a possibility that the operation does not start even when the power is turned on, depending on the power supply voltage or its transient operation, the constant values of the constituent elements, the manufacturing accuracy, the ambient temperature, and other conditions. To avoid this, a start-up circuit may be added to the reference voltage generating circuit 1A to the reference voltage generating circuit 1F.

In the reference voltage generating circuit 1A to the reference voltage generating circuit 1F, if the characteristics of the reference voltage generating circuit 1A to the reference voltage generating circuit 1F are ideal, the resistance voltage dividing circuit 50 and the resistance circuit 55 may be simple open circuits. If the characteristics of the reference voltage generating circuits 1A to 1F are ideal, the above-mentioned expression (10) is also satisfied when the resistor 51 (or the resistor 52 in addition to the resistor 51 in the case of the resistor voltage dividing circuit 50) is opened and removed to obtain the current Id3 as the entire output current IOUT. In addition, in the resistance voltage divider circuit 50, if the

resistors

51 and 52 are opened and removed, the divided voltage cannot be derived as the bias voltage. In this case, as described above, the output voltage VOUT or the voltage supplied from the external circuit may be used as the bias voltage.

In the above embodiment, the area of the junction of the diode D1 is n times the area of the junction of the diode D2, but the area ratio of the junctions of the diode D1 and the diode D2 is not limited to the above ratio. For example, even if diodes having the same area (or length and width) as the bonding portions are used, a configuration equivalent to the configuration using the diodes D1 and D2 can be realized. When diodes having the same area as the junction are used, the number of diodes connected in parallel constituting the diode D1 may be n times the number of diodes connected in parallel constituting the diode D2.

Further, in the above embodiment, a case was described in which the ratio of the gate width/gate length of each of the PMOS transistor 16, the PMOS transistor 17, and the PMOS transistor 18, and the ratio of the gate width/gate length of each of the NMOS transistor 85, the NMOS transistor 86, and the NMOS transistor 87 were 1: p: p.q. However, the ratios of the gate widths/gate lengths of the

PMOS transistors

16, 17, 18 and the ratios of the gate widths/gate lengths of the

NMOS transistors

85, 86, 87 are not limited to the ratios. Even if PMOS transistors (hereinafter referred to as "reference transistors") having the same gate width/gate length value are used, the ratio of the gate width/gate length of each of the

PMOS transistors

16, 17, 18 can be made 1: p: the ratio of the gate width/gate length of each of the NMOS transistor 85, the NMOS transistor 86, and the NMOS transistor 87, or the p · q current-dividing circuit 10 is 1: p: a p.q current shunt circuit 80.

For example, there are the following cases: the

PMOS transistors

16, 17, and 18 are formed using a reference transistor group including at least one reference transistor and having one reference transistor or a plurality of reference transistors connected in parallel. In this case, the number of reference transistors is 1: p: p · q of the current shunting circuit 10 of the PMOS transistor 16, the PMOS transistor 17, the PMOS transistor 18 to the transistor having a ratio of gate width/gate length of 1: p: the current shunt circuit 10 of the PMOS transistor 16, the PMOS transistor 17, and the PMOS transistor 18 of p · q has a substantially equivalent configuration. In addition, the number of reference transistors is 1: p: p · q NMOS transistor 85, NMOS transistor 86, current-shunting circuit 80 of NMOS transistor 87, and a current-shunting element having a ratio of gate width/gate length of 1: p: the current shunt circuit 80 of the NMOS transistor 85, the NMOS transistor 86, and the NMOS transistor 87 of p · q has a substantially equivalent configuration.

The above-described embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Claims

1. A reference voltage generating circuit, comprising:

a current shunt circuit having:

a first input terminal and a second input terminal,

A power input terminal,

A first output terminal to a third output terminal,

A first field effect transistor including a gate connected to the first input terminal, a drain connected to the power input terminal, and a source, and electrically connected to a first power source via the power input terminal,

a second field effect transistor comprising a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the first output terminal,

a third field effect transistor having a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the second output terminal, an

A fourth field effect transistor having a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the third output terminal;

a first resistor-diode circuit having a resistor and a diode, one end of which is connected to the first output terminal of the current shunt circuit, and the other end of which is connected to a second power supply;

a second resistor-diode circuit having a resistor and a diode, one end of which is connected to the second output terminal of the current shunt circuit, and the other end of which is connected to the second power supply;

a feedback control circuit including a first input terminal connected to the one end of the first resistance diode circuit, a second input terminal connected to the one end of the second resistance diode circuit, and an output terminal connected to the first input terminal of the current shunt circuit;

a resistance circuit having a resistance, one end of which is connected to the third output terminal of the current dividing circuit, and the other end of which is connected to the second power supply; and

an output terminal connected to the third output terminal of the current shunt circuit and the one end of the resistance circuit,

the first field effect transistor has a first polarity that is one of n-type and p-type,

the second to fourth field effect transistors have a second polarity as the other of the n-type and p-type.

2. The reference voltage generating circuit according to claim 1, wherein

The resistance circuit includes a first resistance and a second resistance connected in series, and is a resistance voltage dividing circuit in which a connection point of the first resistance and the second resistance is connected to the second input terminal of the current dividing circuit.

3. The reference voltage generating circuit according to claim 1, wherein

The second input terminal of the current splitting circuit is electrically connected to the second power supply.

4. The reference voltage generating circuit according to any one of claims 1 to 3, comprising:

at least one phase compensation circuit selected from the first phase compensation circuit, the second phase compensation circuit, and the third phase compensation circuit,

the first phase compensation circuit includes a capacitor and is connected between the output terminal of the feedback control circuit and the second power supply,

the second phase compensation circuit includes a capacitor and is connected between the output terminal and the second power source,

the third phase compensation circuit includes a capacitor and is connected between the second input terminal and the third output terminal of the current splitting circuit.

5. The reference voltage generating circuit according to any one of claims 1 to 3, comprising:

at least one phase compensation circuit selected from the fourth phase compensation circuit and the fifth phase compensation circuit,

the fourth phase compensation circuit includes a capacitor and is connected between the first output terminal of the current splitting circuit and the first resistance diode circuit and between the second power supply,

the fifth phase compensation circuit includes a capacitor and is connected between the second output terminal of the current dividing circuit and the second resistance diode circuit and between the second power supply.

6. The reference voltage generating circuit according to any one of claims 1 to 3, comprising:

a resistor connected between the second input of the feedback control circuit and the one end of the second resistive diode circuit.

7. The reference voltage generating circuit according to any one of claims 1 to 3, wherein

The feedback control circuit includes a differential amplifier circuit that outputs a voltage obtained by amplifying a difference between a first input voltage input to the first input terminal of the differential amplifier circuit and a second input voltage input to the second input terminal of the differential amplifier circuit from the output terminal of the differential amplifier circuit.