JP7292117B2 - Reference voltage generator - Google Patents

Description

The present invention relates to a reference voltage generation circuit .

A reference voltage generation circuit is known which outputs a voltage stable at a predetermined voltage value as a reference voltage, which is not easily affected by power supply voltage and temperature. An example of the reference voltage generation circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-45125 (see Patent Document 1).

FIG. 8 is a circuit diagram showing a configuration example of a conventional reference voltage generation circuit 100. In the reference voltage generation circuit shown in FIG. 1 is a circuit diagram of a circuit substantially equivalent to the case of FIG.

The reference voltage generating circuit 100 illustrated in FIG. 8 includes field effect transistors (hereinafter referred to as “PMOS transistors”) 105 to 107 having p-type polarity, diodes 111 and resistors 112 and 113, diodes 115 and It has a resistor 116 , a differential amplifier circuit 118 , an output voltage circuit 120 and an output terminal 130 .

Each source of the PMOS transistors 105 to 107 is connected to a power supply terminal 103 that supplies a power supply voltage VDD. Each gate of the PMOS transistors 105 to 107 is connected to the output terminal of the differential amplifier circuit 118, respectively. The drain of the PMOS transistor 105 is connected to three points through the node N11. Specifically, the drain of the PMOS transistor 105 is connected (grounded) to GND via a series circuit of a resistor 112 and a diode 111 as a first point. The drain of the PMOS transistor 105 is connected (grounded) to GND via a resistor 113 as a second point. The drain of the PMOS transistor 105 is connected to the non-inverting input terminal (+) of the differential amplifier circuit 118 as the third point.

The drain of the PMOS transistor 106 is connected to three points through the node N12. Specifically, the drain of PMOS transistor 106 is connected to the anode of diode 115 as a first point. The cathode of the diode 115 is further connected (grounded) to GND. The drain of the PMOS transistor 106 is connected (grounded) to GND via a resistor 116 as a second point. The drain of the PMOS transistor 106 is connected to the inverting input terminal (-) of the differential amplifier circuit 118 as the third point.

The drain of the PMOS transistor 107 is connected to two points through the node N13. Specifically, the drain of the PMOS transistor 107 is connected (grounded) to GND via an output voltage circuit 120 including a resistor 123 as a first point. The drain of PMOS transistor 107 is connected to output terminal 130 as a second point.

In the reference voltage generating circuit 100, PMOS transistors 105, 106, and 107 output drain currents of a preset ratio. In the reference voltage generation circuit 100 thus configured, the rest of the circuit except for the PMOS transistor 107 and the resistor 123 constitutes a feedback control circuit. As a result, the reference voltage generation circuit 100 operates as a bandgap reference circuit.

The drain current of the PMOS transistor 105 branches at the node N11 and flows through the series circuit of the resistor 112 and the diode 111 and the resistor 113, respectively. The drain current of PMOS transistor 106 branches at node N12 and flows through diode 115 and resistor 116, respectively. The drain current of PMOS transistor 107 flows through resistor 123 . Therefore, in the reference voltage generation circuit 100, a voltage equal to the voltage drop across the resistor 123 is obtained as the output voltage VOUT.

JP-A-11-45125

However, the reference voltage generation circuit 100 illustrated in FIG. 8 has a problem that when the power supply voltage VDD suddenly rises or falls, a transient but large-amplitude voltage is superimposed on the output voltage VOUT. For example, when the power supply voltage VDD changes from 1.5 V to 6.0 V or from 6.0 V to 1.5 V for several μs, an amplitude variation of several tens of mV to several hundreds of mV is superimposed on the output voltage VOUT. .

The output of the reference voltage generating circuit is often used as a reference voltage when other circuits operate. For example, it serves as the reference for the output voltage of power supply voltage output circuits such as LDOs and DC/DC converters, and the reference for the bias voltage and amplitude voltage of signal processing circuits such as amplifier circuits and filters. The output voltages of these circuits, which operate based on the output voltage of the reference voltage generation circuit, are influenced by the fluctuations in the output voltage of the reference voltage generation circuit, and fluctuate by equal or proportional amounts. In this way, fluctuations in the output voltage of the reference voltage generation circuit cause deviations and errors in the operation of other circuits, so the smaller the fluctuation, the better.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a reference voltage generating circuit capable of reducing amplitude fluctuations of an output voltage caused by sudden fluctuations in power supply voltage.

In order to solve the above-described problems, a reference voltage generation circuit according to the present invention includes a first input terminal, a second input terminal, a power supply input terminal, first to third output terminals, and the first input terminal. a first field effect transistor including a gate connected to an input terminal, a drain connected to the power supply input terminal, and a source, and electrically connected to a first power supply via the power supply input terminal; , a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the first output terminal. a third electric field including a transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input, and a drain connected to the second output. an effect transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the third output terminal. a current shunt circuit having a field effect transistor; a resistor and a diode; one end of which is connected to the first output end of the current shunt circuit; a resistor diode circuit, a second resistor diode circuit having a resistor and a diode, one end of which is connected to the second output end of the current shunt circuit and the other end of which is connected to the second power supply; a first input terminal connected to the one end of the first resistor diode circuit; a second input terminal connected to the one end of the second resistor diode circuit; and the first input terminal of the current shunting circuit. an output end connected to an input end; and a resistor, one end of which is connected to the third output end of the current shunt circuit and the other end of which is connected to the second power supply. and an output terminal connected to the third output terminal of the current shunt circuit and the one end of the resistance circuit, wherein the second input terminal of the current shunt circuit is directly connected to the first 2, or electrically connected to the third output terminal, the first field effect transistor having a first polarity that is one of n-type and p-type; and the second to fourth field effect transistors have a second polarity which is the other of the n-type and p-type.
In order to solve the above-described problems, a reference voltage generation circuit according to the present invention includes a first input terminal, a second input terminal, a power supply input terminal, first to third output terminals, and the first input terminal. a first field effect transistor including a gate connected to an input terminal, a drain connected to the power supply input terminal, and a source, and electrically connected to a first power supply via the power supply input terminal; , a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the first output terminal. a third electric field including a transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input, and a drain connected to the second output. an effect transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input terminal, and a drain connected to the third output terminal. a current shunt circuit having a field effect transistor; a resistor and a diode; one end of which is connected to the first output end of the current shunt circuit; a resistor diode circuit, a second resistor diode circuit having a resistor and a diode, one end of which is connected to the second output end of the current shunt circuit and the other end of which is connected to the second power supply; a first input terminal connected to the one end of the first resistor diode circuit; a second input terminal connected to the one end of the second resistor diode circuit; and the first input terminal of the current shunting circuit. an output end connected to an input end; and a resistor, one end of which is connected to the third output end of the current shunt circuit and the other end of which is connected to the second power supply. and an output terminal connected to the third output terminal of the current shunt circuit and the one end of the resistance circuit, wherein the first field effect transistor is one of n-type and p-type and the second to fourth field effect transistors have a second polarity that is the other of the n-type and p-type, and the resistor circuit is connected in series A resistor voltage dividing circuit including a first resistor and a second resistor, wherein a connection point between the first resistor and the second resistor is connected to the second input terminal of the current dividing circuit. characterized by

According to the present invention, even when the power supply voltage fluctuates abruptly, it is possible to reduce the amplitude fluctuation of the output voltage caused by the fluctuation.

1 is a circuit diagram showing a first configuration example of a current shunt circuit according to a first embodiment and a reference voltage generation circuit having the current shunt circuit; FIG . FIG. 4 is a circuit diagram showing a second configuration example of the current shunt circuit according to the first embodiment and the reference voltage generation circuit having the current shunt circuit ; FIG. 5 is a circuit diagram showing a configuration example of a current shunt circuit according to a second embodiment and a reference voltage generation circuit having the current shunt circuit; 4A and 4B are circuit diagrams each showing a configuration example of a phase compensation circuit connected between a current shunt circuit and a resistor diode circuit; FIG. FIG. 11 is a circuit diagram showing a configuration example of a current shunt circuit according to a third embodiment and a reference voltage generation circuit having the current shunt circuit; FIG. 10 is a circuit diagram showing a configuration example of a current shunt circuit according to a first modification and a reference voltage generation circuit having the current shunt circuit ; FIG. 11 is a circuit diagram showing a configuration example of a current shunt circuit according to a second modification and a reference voltage generation circuit having the current shunt circuit ; FIG. 4 is a circuit diagram showing a configuration example of a conventional current shunt circuit and a reference voltage generation circuit having the current shunt circuit;

A current shunt circuit and a reference voltage generation circuit having the current shunt circuit according to embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
FIG. 1 is a circuit diagram showing configurations of a current dividing circuit 10 and a reference voltage generating circuit 1A, which are examples of a current dividing circuit and a reference voltage generating circuit having the current dividing circuit according to the first embodiment.

The reference voltage generating circuit 1A includes a current dividing circuit 10, a resistor diode circuit 20, a resistor diode circuit 30, a feedback control circuit 40, a resistor voltage dividing circuit 50, and an output terminal 60. Further, the reference voltage generation circuit 1A is provided with a power supply terminal 3 electrically connected to the first power supply and a ground terminal electrically connected (grounded) to GND as the second power supply. there is

The current dividing circuit 10 includes an input terminal 11a as a first input terminal, an input terminal 11b as a second input terminal, a power supply input terminal 12, an output terminal 13a as a first output terminal, and a second and an output end 13c as a third output end.

A resistance diode circuit 20 as a first resistance diode circuit has one end connected to the node N1 and the other end grounded. A resistance diode circuit 30 as a second resistance diode circuit has one end connected to the node N2 and the other end grounded.

The feedback control circuit 40 has an inverting input terminal (-) as a first input terminal connected to the output terminal 13a and a non-inverting input terminal (+) as a second input terminal connected to the output terminal 13b. , and an output terminal 43 connected to the output terminal of the differential amplifier circuit 41 .

A resistive voltage dividing circuit 50 as a resistive circuit has a resistor 51 and a resistor 52 connected in series. grounded at the end.

The output terminal 13a is connected to the node N1, and is connected to one end of the resistor diode circuit 20 and the inverting input terminal of the differential amplifier circuit 41 via the node N1. The output terminal 13b is connected to the node N2, and is connected to one end of the resistor diode circuit 30 and the non-inverting input terminal of the differential amplifier circuit 41 via the node N2. Also, the output end 43 and the input end 11a are connected. Therefore, a feedback loop is formed by the current shunt circuit 10 and the feedback control circuit 40 .

Further, the current dividing circuit 10 is connected to the resistance diode circuit 20 through the node N1, and is connected to the resistance diode circuit 30 through the node N2.

The input terminal 11b is connected to a node N3, which is a connection point between the resistors 51 and 52. FIG. Also, the output terminal 13 c is connected to one end of the resistance voltage dividing circuit 50 . Therefore, the current dividing circuit 10 is connected so as to be capable of inputting voltage from the resistive voltage dividing circuit 50 and outputting voltage to the resistive voltage dividing circuit 50 . An output terminal 60 is connected to a connection point between the output terminal 13 c and one end of the resistance voltage dividing circuit 50 . Further, the power supply input terminal 12 is connected to the power supply terminal 3 that supplies the power supply voltage VDD.

Next, each circuit of the current dividing circuit 10, the resistor diode circuits 20 and 30, the feedback control circuit 40, and the resistor voltage dividing circuit 50 will be described.

In addition to the input terminals 11a and 11b, the power input terminal 12 and the output terminals 13a to 13c, the current dividing circuit 10 includes a field effect transistor (hereinafter referred to as "NMOS transistor") 15 having n-type polarity and a p-type and field effect transistors (PMOS transistors) 16 to 18 having polarities.

The NMOS transistor 15 as the first field effect transistor has n-type polarity as the first polarity, which is one of n-type and p-type polarities. The NMOS transistor 15 includes a gate connected to the input terminal 11a, a drain connected to the power input terminal 12, and a source.

The PMOS transistor 16 as the second field effect transistor has p-type polarity as the second polarity, which is the other polarity of n-type and p-type. The PMOS transistor 16 includes a gate, a source connected to the source of the NMOS transistor 15, a backgate connected (short-circuited) to this source, and a drain connected to the output terminal 13a.

A PMOS transistor 17 as a third field effect transistor has a p-type polarity as a second polarity, and has a gate, a source connected to the source of the NMOS transistor 15, and a back gate connected to this source. and a drain connected to the output terminal 13b.

A PMOS transistor 18 as a fourth field effect transistor has a p-type polarity as a second polarity, and has a gate, a source connected to the source of the NMOS transistor 15, and a back gate connected to this source. and a drain connected to the output terminal 13c.

The value of the gate width with respect to the gate length of the PMOS transistor 17 (hereinafter referred to as "gate width/gate length") is p (p is any positive number) with respect to the value of the gate width/gate length of the PMOS transistor 16. Double. The value of gate width/gate length of the PMOS transistor 18 is q (where q is an arbitrary positive number) times the value of gate width/gate length of the PMOS transistor 17 . That is, the gate width/gate length ratio of the PMOS transistors 16, 17 and 18 is 1:p:p·q.

The PMOS transistor 16 is connected to the gates of the PMOS transistors 17 and 18 and the input terminal 11b, respectively. The PMOS transistor 17 is connected to the gates of the PMOS transistors 16 and 18 and the input terminal 11b, respectively. The PMOS transistor 18 is connected to the gates of the PMOS transistors 16 and 17 and the input terminal 11b, respectively.

The resistive diode circuit 20 has a diode D1 and a resistor 22 forming a first current path (hereinafter simply referred to as "path") and a resistor 23 forming a second path. The first path is connected in parallel with the second path in resistive diode circuit 20 .

A first path is a path connecting node N1 and GND via resistor 22 and diode D1. In the first path, the node N1 and one end of the resistor 22 are connected, the other end of the resistor 22 is connected to the anode of the diode D1, and the cathode of the diode D1. The cathode of diode D1 is grounded.

A second path is a path that connects node N1 and GND via resistor 23 . Node N1 is connected to one end of resistor 23 on the second path. The other end of resistor 23 is grounded.

Resistive diode circuit 30 has diode D2 and resistor 32 connected in parallel between node N2 and GND. Diode D2 has an anode connected to node N2 and a cathode grounded. The area of the junction of the diode D2 is 1/n (n is an arbitrary positive number) times the area of the junction of the diode D1. In other words, the junction area of the diode D1 is n times the area of the junction of the diode D2. The resistor 32 has one end connected to the node N2 and the other end grounded.

In the feedback control circuit 40 , the first input terminal of the feedback control circuit 40 is connected to the inverting input terminal of the differential amplifier circuit 41 . A second input terminal of the feedback control circuit 40 is connected to a non-inverting input terminal of the differential amplifier circuit 41 .

The resistor voltage dividing circuit 50 is a voltage dividing circuit that obtains a divided voltage of the output voltage VOUT output to the output terminal 60 by resistors 51 and 52 connected in series. A divided voltage of the output voltage VOUT is the voltage of the node N3.

Next, functions and effects of the reference voltage generation circuit 1A will be described.
In the reference voltage generating circuit 1A, the current dividing circuit 10 generates currents Id1, Generate current Id2 and current Id3.

More specifically, the NMOS transistor 15 generates the current Id based on the voltage input from the input terminal 11 a and the power supply voltage VDD input from the power supply input terminal 12 . The generated current Id separately flows into each source of the PMOS transistors 16, 17 and 18. FIG. A voltage input from the input terminal 11b is applied to each gate of the PMOS transistors 16, 17, 18 as a bias voltage.

The PMOS transistor 16 causes a current Id1 to flow from the drain based on the current input to the source and the bias voltage applied to the gate. The PMOS transistor 17 causes a current Id2 to flow from the drain based on the current input to the source and the bias voltage applied to the gate. The PMOS transistor 18 causes a current Id3 to flow from the drain based on the current input to the source and the bias voltage applied to the gate. The current ratio of the currents Id1, Id2 and Id3 is equal to the gate width/gate length ratio of the PMOS transistors 16, 17 and 18, which is 1:p:p·q.

A current Id 1 , which is a drain current, is output from the output terminal 13 a and flows into the resistance diode circuit 20 . The current Id1 that has flowed into the resistor diode circuit 20 is divided into a current I1 flowing through the resistor 23 and a current I2 flowing through the resistor 22 and the diode D1 via the node N1 and flows to GND.

A current Id2, which is a drain current, is output from the output terminal 13b and flows into the resistance diode circuit 30. FIG. The current Id2 that has flowed into the resistance diode circuit 30 is divided into a current I3 flowing through the diode D2 and a current I4 flowing through the resistor 32 via the node N2 and flows to GND.

A current Id3, which is a drain current, is output from the output terminal 13c and flows into the resistance voltage dividing circuit 50. FIG. Current Id3 is equal to current I5 flowing through resistive voltage dividing circuit 50 and flows through resistors 51 and 52 to GND. A divided voltage according to the resistance ratio of the resistors 51 and 52 is generated at the node N3, which is the connection point of the resistors 51 and 52, due to the current flowing through the resistors 51 and 52. FIG. This divided voltage is supplied to the input terminal 11b as a bias voltage.

Further, the voltage VN1 of the node N1 and the voltage VN2 of the node N2 are input to the feedback control circuit 40 . More specifically, the voltage VN1 as the first input voltage is input to the inverting input terminal of the differential amplifier circuit 41, and the voltage VN2 as the second input voltage is input to the non-inverting input terminal of the differential amplifier circuit 41. be done. The differential amplifier circuit 41 supplies an output terminal 43 with a voltage proportional to the difference between the two voltages respectively input to the inverting input terminal and the non-inverting input terminal. The voltage supplied to the output terminal 43 is applied to the gate of the NMOS transistor 15 through the input terminal 11a of the current dividing circuit 10 as the output voltage of the feedback control circuit 40 .

An output voltage VOUT is output from the output terminal 60 . The output voltage VOUT is obtained by formulating a circuit equation and solving for the output voltage VOUT. In formulating the circuit equations, the resistance values of resistors 23, 22, 32, 51 and 52 are assumed to be R1, R2, R3, R4 and R5, respectively. Let the voltages across the diodes D1 and D2 be VD1 and VD2, respectively. Thermal voltage VT is kB·T/qe (kB is Boltzmann's constant, T is absolute temperature, and qe is elementary charge). Let Is be the reverse saturation current of the diodes D1 and D2. Assume that the offset voltage of the differential amplifier circuit 41 is Voffset. According to the above conditions, the following equations (1) to (7) are obtained.

Since the equation of the above equation (8) includes the voltage VN1 of the node N1 and the voltage VN2 of the node N2, it cannot be said that the above equation (8) is explicitly solved. Therefore, circuit conditions are further added in consideration of the practical use of the reference voltage generating circuit 1A. In the differential amplifier circuit 41, two voltages respectively input to the inverting input terminal and the non-inverting input terminal are generally substantially equal. Therefore, the voltage VN1 input to the inverting input terminal and the voltage VN2 input to the non-inverting input terminal are assumed to be substantially equal, and the terms on the right side of the above equation (8) are further arranged. Further arranging the terms on the right side of the above equation (8), the output voltage VOUT is expressed by the following equation (9).

According to the above equation (9), it can be seen that the output voltage VOUT can be freely set by means of circuit constants. Therefore, the reference voltage generating circuit 1A has a large degree of freedom in circuit design. Here, it is assumed that the characteristics of reference voltage generating circuit 1A are ideal, that is, the impedance of the load connected to output terminal 60 is infinite. If the characteristics of the reference voltage generating circuit 1A are ideal, all of the current Id3 flows through the resistive voltage dividing circuit 50, so the current Id3 is equal to the current I5 flowing through the resistors 51 and 52 connected in series. Therefore, the output voltage VOUT is the resistance value between one end and the other end of the resistance voltage dividing circuit 50, that is, the resistance value of the resistor (=R4·R5/(R4+R5)) in which the resistors 51 and 52 are connected in series. It is obtained by multiplying it with the current I5 (=current Id3).

On the other hand, the resistors 22, 23, 32, 51, and 52 used in actual electronic circuits do not always have ideal characteristics, and their operation depends on environmental temperature, potential difference between the resistor element and the power supply voltage VDD or ground potential. The resistance value may vary depending on the situation. The resistance values R1 to R5 of the resistors 22, 23, 32, 51, 52 appear as ratios of each other in the right-hand term of the above equation (9). Therefore, the output voltage VOUT can be determined by the relative values of the resistance values of the mutual resistors rather than the absolute values of the resistance values of the mutual resistors.

The relative precision of the resistance value is often obtained with a precision difference as high as about 1/1000 when configured on an integrated circuit (IC). Therefore, the characteristics of the output voltage VOUT can be obtained with high accuracy without being affected by the variation characteristics of the resistance.
Further, from the above equation (9), the current IOUT flowing to the output terminal 60 is given by the following equation (10)
is represented by

According to the above equation (10), the output current IOUT is directly affected by the absolute accuracy of the resistance value R1 of the resistor 23. If the resistance value R1 of the resistor 23 can be obtained with high accuracy without being affected by the operating conditions such as the environmental temperature, the potential difference between the power supply voltage VDD and the ground potential, it is possible to obtain the output current IOUT with high accuracy. . That is, in this case, the reference voltage generation circuit 1A can function as a reference current generation circuit.

Thus, in the reference voltage generation circuit 1A, the NMOS transistor 15 generates the current Id based on the output of the feedback control circuit 40. FIG. Based on this current Id, respective currents Id1, Id2 and Id3 to be supplied to the resistor diode circuit 20, the resistor diode circuit 30 and the resistor voltage dividing circuit 50 are generated.
The NMOS transistor 15 has a drain connected to the power supply terminal 3 , but the remaining gate, back gate and source are not connected to the power supply terminal 3 . In general, a MOSFET has a large internal resistance of, for example, several MΩ between the drain and the source, so the influence of fluctuations in the power supply voltage VDD on the current Id is limited.
Therefore, in the reference voltage generation circuit 1A, even if the power supply voltage VDD, which is the drain voltage of the NMOS transistor 15, suddenly changes, it is possible to reduce the ratio of the voltage resulting from the fluctuation of the power supply voltage VDD being superimposed on the current Id.

Further, in the reference voltage generation circuit 1A, the voltage VN1 and the voltage VN2 are input to the differential amplifier circuit 41, so that the common-mode component of the input signal can be canceled. Therefore, even if the fluctuation caused by the sudden change in the power supply voltage VDD is superimposed on each of the voltages VN1 and VN2, the fluctuation can be removed. Further, in the reference voltage generation circuit 1A, the stabilized divided voltage of the output voltage VOUT is input to each gate of the PMOS transistors 16, 17, 18 through the input terminal 11b. This allows the PMOS transistors 16, 17 and 18 to operate stably.

Therefore, according to the reference voltage generation circuit 1A, even when the power supply voltage VDD fluctuates abruptly, the amplitude fluctuation of the output voltage VOUT caused by the fluctuation can be reduced. Further, according to the reference voltage generating circuit 1A, by appropriately selecting the PMOS transistors 16, 17 and 18, the ratio (dividing ratio) of the currents Id1, Id2 and Id3 can be arbitrarily selected.

In the reference voltage generating circuit 1A described above, the bias voltage input from the input terminal 11b to the current dividing circuit 10 is the divided voltage of the output voltage VOUT extracted from the resistance voltage dividing circuit 50, but is not limited to this. . As will be described later with reference to FIG. 2, the input bias voltage does not necessarily have to be a divided voltage of the output voltage VOUT.

FIG. 2 is a circuit diagram showing the configuration of a reference voltage generation circuit 1B, which is another example of the reference voltage generation circuit according to the first embodiment.

The reference voltage generation circuit according to the present embodiment may have a configuration in which a voltage generated by a voltage source that supplies a predetermined voltage is input to the input terminal 11b, for example, like the reference voltage generation circuit 1B. Note that the reference voltage generating circuit 1B has a resistor circuit 55 instead of the resistor voltage dividing circuit 50, and the source of the bias voltage is not the resistor voltage dividing circuit 50 but an external source. The difference is that it is the voltage source 57, but the other points are the same.

The resistor circuit 55 has a configuration in which the resistor 52 is omitted from the resistor voltage dividing circuit 50 , that is, has a resistor 51 . Voltage source 57 includes a negative terminal connected to GND and a positive terminal connected to input 11b as the second input. According to the reference voltage generation circuit 1B configured in this way, even when the divided voltage of the output voltage VOUT is not applied from the input terminal 11b, the same effect as that of the reference voltage generation circuit 1A can be obtained.

Although the reference voltage generating circuit 1B described above has the input terminal 11b and the voltage source 57 connected, the input terminal 11b and the voltage source 57 do not necessarily need to be connected. The reference voltage generation circuit 1B has, for example, a configuration in which the output voltage VOUT is input to the input terminal 11b. short-circuited with the end 13c). Also, if the design conditions permit, the input terminal 11b may be electrically connected to GND.

In this way, the reference voltage generation circuit 1B in which the output terminal 13c and the input terminal 11b are connected (short-circuited), the reference voltage generation circuit 1B electrically connected to the voltage source 57, and the reference voltage generator electrically connected to GND. In the voltage generation circuit 1B, the circuit configuration can be simplified while reducing the influence of sudden changes in the power supply voltage VDD.

[Second embodiment]
FIG. 3 is a circuit diagram showing the configuration of a reference voltage generation circuit 1C, which is an example of the reference voltage generation circuit according to the second embodiment.

Reference voltage generation circuit 1C differs from reference voltage generation circuit 1A in that phase compensation circuits 71 to 75 and resistor 77 are further provided, but other points are the same. Therefore, in this embodiment, the phase compensation circuits 71 to 75 and the resistor 77 will be mainly described, and the description overlapping with the reference voltage generation circuit 1A will be omitted. In FIG. 3, from the viewpoint of ensuring the clarity of the drawing, some components such as the input terminals 11a and 11b overlapping with the reference voltage generating circuit 1A are omitted.

A phase compensation circuit 71 as a first phase compensation circuit includes a capacitor C1 and is connected between the output terminal (not shown in FIG. 3) of the feedback control circuit 40 and GND. A phase compensation circuit 72 as a second phase compensation circuit includes a capacitor C2 and is connected between the output terminal 60 and GND. A phase compensation circuit 73 as a third phase compensation circuit includes a capacitor C3 and connects a node N4 corresponding to the input terminal 11b (not shown in FIG. 3) and an output terminal 13c (not shown in FIG. 3). It is connected between corresponding node N5.

A phase compensation circuit 74 as a fourth phase compensation circuit is connected to the connection point P1. The connection point P1 is provided between the drain of the PMOS transistor 16 and one end of the resistor diode circuit 20, more specifically, the node N1. A phase compensation circuit 75 as a fifth phase compensation circuit is connected to the connection point P2. The connection point P2 is connected between the drain of the PMOS transistor 17 and one end of the resistor diode circuit 30, more specifically, the node N2. The phase compensation circuits 74 and 75 are configured including at least capacitors 742 and 752 as shown in FIGS. 4(A) and 4(B).
The resistor 77 is connected between the non-inverting input terminal of the differential amplifier circuit 41 and one end of the resistor diode circuit 30, more specifically, the node N2.

In the reference voltage generation circuit 1C thus configured, the phase compensation circuits 71 to 75 increase the phase margin. In the phase compensation circuits 71 and 72, one ends of the capacitors C1 and C2 are connected (grounded) to GND, which is also a ground point in terms of AC. Therefore, the phase compensation circuits 71 and 72 increase the phase margin and improve the stability of the nodes in the reference voltage generating circuit 1C against sudden changes in the power supply voltage VDD.

In the phase compensation circuit 73, the drain of the PMOS transistor 18 is connected to its own gate and further to the resistance voltage dividing circuit 50, so that the capacitor C3 can obtain a mirror effect. Due to this Miller effect, the phase compensation circuit 73 operates in the same manner as when a capacitor larger than the actual capacity of the capacitor C3 is connected.

The resistor 77 reduces the difference between the AC impedances of the two input terminals of the differential amplifier circuit 41 to the outside.
A first AC impedance looking out from the inverting input terminal of the differential amplifier circuit 41 is approximately equal to the resistance value of the resistor 22 when the diode D1 is regarded as an ideal diode. A second AC impedance looking out from the non-inverting input end of the differential amplifier circuit 41 becomes substantially zero if the resistor 77 does not exist and the diode D2 is regarded as an ideal diode. Therefore, if a resistor 77 having a resistance value equal to the resistance value of the resistor 22 is connected between the non-inverting input terminal of the differential amplifier circuit 41 and GND, the first AC impedance and the second AC impedance are approximately can be matched.

According to the reference voltage generation circuit 1C, since the phase compensation circuits 71 to 75 are provided, it is possible to prevent the phase from greatly fluctuating within the frequency band in the feedback control circuit 40 of the negative feedback and to substantially shift to the positive feedback. can be prevented. Therefore, the reference voltage generation circuit 1C can prevent an abnormal operation such as unstable circuit operation or oscillation. That is, according to the reference voltage generating circuit 1C, the stability of circuit operation can be enhanced.

Further, in reference voltage generation circuit 1C, phase compensation circuits 71 and 72 can increase the phase margin and improve the stability of nodes in reference voltage generation circuit 1C against sudden changes in power supply voltage VDD.

Since the phase compensation circuit 73 operates in the same manner as when a capacitor having a capacity larger than the actual capacity of the capacitor C3 is connected, the phase margin can be further increased. In other words, for the capacitor C3, a capacitor with a smaller capacitance value than that required for operation can be selected. In this case, the occupied area and volume of the circuit can be reduced.

Furthermore, since the reference voltage generation circuit 1C includes the resistor 77, the difference between the first AC impedance and the second AC impedance can be reduced. Further, when resistor 77 has a resistance value equal to that of resistor 22, reference voltage generation circuit 1C can substantially match the first AC impedance and the second AC impedance.

Note that the phase compensation circuits 71, 72, 73 illustrated in FIG. 3 are configured only with capacitors C1, C2, C3, respectively, but are not limited to this example. The phase compensation circuits 71, 72 and 73 may be configured to include capacitors C1, C2 and C3, respectively. That is, the phase compensation circuits 71 to 73 may be composed of series circuits of capacitors and resistors.

Further, the phase compensation circuits 74 and 75 are similar to the phase compensation circuits 71-73. That is, the phase compensation circuit 74 may include a resistor 741 connected in series with a capacitor 742 as illustrated in FIG. 4(A). The phase compensation circuit 75 may include a resistor 751 connected in series with a capacitor 752 as illustrated in FIG. 4B. In the phase compensation circuit 74 in which the capacitor 742 and the resistor 741 are connected in series, the positional relationship between the resistor 741 and the capacitor 742 is not limited to the positional relationship illustrated in FIG. The positional relationship illustrated in FIG. 4A may be reversed. Also, the positional relationship between the resistor 751 and the capacitor 752 is the same as the positional relationship between the resistor 741 and the capacitor 742 .

[Third embodiment]
FIG. 5 is a circuit diagram showing configurations of a current dividing circuit 80 and a reference voltage generating circuit 1D, which are examples of a current dividing circuit and a reference voltage generating circuit having the current dividing circuit according to the third embodiment.

The reference voltage generation circuit 1D differs from the reference voltage generation circuit 1A in that it includes a current shunt circuit 80 instead of the current shunt circuit 10 and a resistance circuit 55 instead of the resistance voltage divider circuit 50. , and other points are the same. Note that the resistor circuit 55 is a component provided in the reference voltage generation circuit 1B, and is as described in the first embodiment. Therefore, in the present embodiment, the current shunt circuit 80 will be mainly described, and descriptions overlapping those of the reference voltage generation circuits 1A and 1B will be omitted.

The current dividing circuit 80 has an input terminal 81 connected to the output terminal 43, power supply input terminals 82a to 82c respectively connected to the power supply terminal 3, output terminals 83a to 83c, and NMOS transistors 85 to 87. are doing.

The output terminal 83a is connected to one end of the resistor diode circuit 20, more specifically, the node N1. The output end 83b is connected between one end of the resistor diode circuit 30, more specifically, the node N2. The output terminal 83c is connected to one end of the resistor circuit 55, that is, one end of the resistor 51. FIG.

The NMOS transistor 85 includes a gate connected to the input terminal 81, a drain connected to the power supply input terminal 82a, and a source connected to the output terminal 83a. The NMOS transistor 86 includes a gate connected to the input terminal 81, a drain connected to the power supply input terminal 82b, and a source connected to the output terminal 83b. The NMOS transistor 87 includes a gate connected to the input terminal 81, a drain connected to the power supply input terminal 82c, and a source connected to the output terminal 83c.

The value of the gate width/gate length of the NMOS transistor 86 is p (p is any positive number) times the value of the gate width/gate length of the NMOS transistor 85 . The value of gate width/gate length of the NMOS transistor 87 is q (q is any positive number) times the value of gate width/gate length of the NMOS transistor 86 . That is, the gate width/gate length ratio of the NMOS transistors 85, 86 and 87 is 1:p:p·q.

In the reference voltage generation circuit 1D configured in this manner, a bias voltage is input to each of the gates of the PMOS transistors 16, 17 and 18 in that no bias voltage is input to each of the gates of the NMOS transistors 85, 86 and 87. It is different from the reference voltage generating circuit 1A that is used. That is, the configuration of reference voltage generation circuit 1D is simpler than that of reference voltage generation circuit 1A.

On the other hand, due to the above difference, in the reference voltage generation circuit 1D, the magnitudes of the source currents Is1, Is2, and Is3 are constantly maintained at 1:p:p·q in order to satisfy the above equation (9). There is a need. That is, the voltage VN1 and the voltage VN2 must constantly have substantially the same value.

In the reference voltage generating circuit 1D, a current dividing circuit 80 generates source currents Is1, Is2 and Is3 based on the output of the differential amplifier circuit 41. FIG. Source currents Is1, Is2 and Is3 are output from output terminals 83a, 83b and 83c, respectively.

Source current Is1 splits into current I1 and current I2 at node N1. Current I1 flows through resistor 23 to GND. Current I2 flows through resistor 22 and diode D1 to GND.
Source current Is2 splits into current I3 and current I4 at node N2. Current I3 flows to GND via diode D2. Current I4 flows through resistor 32 to GND.
Source current Is3 is equal to current I5 flowing through resistor 51 and flows through resistor 51 to GND.

The drains of the NMOS transistors 85 to 87 are connected to the power supply terminal 3, while the gates, back gates and sources are not connected to the power supply terminal 3, respectively. The internal resistance between the drain and source of the NMOS transistors 85 to 87 is as large as several MΩ, for example. Therefore, in the current dividing circuit 80, even if the power supply voltage VDD fluctuates abruptly, the source currents Is1, Is2, and Is3 are generated in which the fluctuation is suppressed.

According to the reference voltage generation circuit 1D, even if the power supply voltage VDD suddenly changes, the sudden changes in the source currents Is1, Is2, and Is3 can be suppressed.

In addition, the present invention is not limited to the above-described embodiment as it is, and in the implementation stage, it is possible to implement it in various forms other than the above-described example, without departing from the gist of the invention. Various omissions, substitutions and alterations may be made.

For example, the polarities of the transistors and the power supply terminal 3 and GND may be exchanged with respect to the reference voltage generation circuits 1A to 1D described above to configure the reference voltage generation circuit.

FIG. 6 is a circuit diagram showing a configuration example of a current shunt circuit 90 and a reference voltage generation circuit 1E, which are examples of a current shunt circuit and a reference voltage generation circuit having the current shunt circuit according to the first modification. FIG. 7 is a circuit diagram showing a configuration example of a current shunt circuit 90 and a reference voltage generation circuit 1F, which are examples of a current shunt circuit according to a second modification and a reference voltage generation circuit having the current shunt circuit .

Reference voltage generating circuit 1E includes current dividing circuit 90, capacitors C1, C2 and C3 included in phase compensation circuits 71, 72 and 73, diode D1, resistors 22 and 23, diode D2 and resistor 32. , a differential amplifier circuit 41 , resistors 51 and 52 , and a resistor 77 .

In other words, the reference voltage generation circuit 1E is a circuit in which the polarities of the transistors and the power supply terminal 3 and GND are exchanged in the reference voltage generation circuit 1C in which the phase compensation circuits 74 and 75 are omitted. Therefore, the current shunt circuit 90 is a circuit in which the polarities of the transistors and the power supply terminal 3 and GND are exchanged with respect to the current shunt circuit 10, and includes a PMOS transistor 95 and three NMOS transistors 96 to 98. ing.

The PMOS transistor 95 as the first field effect transistor has the polarity of the NMOS transistor 15 switched from n-type to p-type. That is, the PMOS transistor 95 has a p-type polarity as a first polarity that is one of n-type and p-type.

The NMOS transistor 96 as the second field effect transistor has the polarity of the PMOS transistor 16 switched from p-type to n-type. That is, the NMOS transistor 96 has n-type polarity as the second polarity, which is the other polarity of n-type and p-type.

The NMOS transistor 97 as the third field effect transistor has the polarity of the transistor changed from the p-type to the n-type with respect to the PMOS transistor 17, and has the n-type as the second polarity. The NMOS transistor 98 as the fourth field effect transistor has the polarity of the transistor changed from the p-type to the n-type with respect to the PMOS transistor 18, and has the n-type as the second polarity.

The reference voltage generation circuit 1E described above can obtain the same effect as the reference voltage generation circuit 1C. Further, in the reference voltage generation circuit 1E, like the reference voltage generation circuit 1C, some or all of the capacitors C1, C2 and C3 may be omitted, or the resistor 77 may be omitted. At least one of the phase compensation circuits 74 and 75 may be added to the reference voltage generation circuit 1E.

Further, in the reference voltage generation circuit 1B, the reference voltage generation circuit 1F may be configured by exchanging the polarities of the transistors and the power supply terminal 3 and GND. The reference voltage generation circuit 1F can obtain the same effect as the reference voltage generation circuit 1B.

At least one of the phase compensation circuits 71 to 75 and the resistor 77 may be added to the reference voltage generation circuit 1F. Also, the voltage source 57 may be omitted from the reference voltage generation circuit 1F.

It should be noted that self-feedback circuits such as the reference voltage generating circuits 1A to 1F described above may operate even when the power is turned on, depending on conditions such as the power supply voltage, its transient operation, constant values of constituent elements, manufacturing accuracy, and ambient temperature. may not start. To avoid this, a starting circuit may be added to the reference voltage generating circuits 1A-1F.

Further, in the reference voltage generation circuits 1A to 1F described above, if the characteristics of the reference voltage generation circuits 1A to 1F are ideal, the resistance voltage dividing circuit 50 and the resistance circuit 55 may be simply open circuits. Equation (10) above shows that if the characteristics of the reference voltage generating circuits 1A to 1F are ideal, the resistor 51 (in the case of the resistor voltage dividing circuit 50, the resistor 52 in addition to the resistor 51) is removed and the current This holds true even when Id3 is all obtained as the output current IOUT. In the resistance voltage dividing circuit 50, if the resistances 51 and 52 are opened and removed, the divided voltage cannot be taken out as the bias voltage. In this case, as described above, the output voltage VOUT or the voltage supplied from the external circuit may be used as the bias voltage.

In the above-described embodiment, the diode D1 has a junction area n times as large as the junction area of the diode D2. The area ratio is not limited to the above ratio. For example, even if diodes having the same junction area (or length and width) are used, a configuration equivalent to the configuration using the diodes D1 and D2 described above can be realized. When diodes having the same junction area are used, the number of diodes in parallel forming the diode D1 should be n times the number of diodes in parallel forming the diode D2.

Furthermore, in the above-described embodiments, the gate width/gate length ratio of the PMOS transistors 16, 17 and 18 and the gate width/gate length ratio of the NMOS transistors 85, 86 and 87 are 1:p:p·q. I explained a case. However, the gate width/gate length ratios of the PMOS transistors 16, 17 and 18 and the gate width/gate length ratios of the NMOS transistors 85, 86 and 87 are not limited to the above ratios. Even if PMOS transistors having the same gate width/gate length values (hereinafter referred to as “reference transistors”) are used, the gate width/gate length ratio of each of the PMOS transistors 16, 17, and 18 is 1:p:p·q. and the current shunt circuit 80 in which the gate width/gate length ratio of the NMOS transistors 85, 86, and 87 is 1:p:p·q.

For example, PMOS transistors 16, 17, 18 may have at least one reference transistor and may be configured using a reference transistor or a group of reference transistors connected in parallel. In this case, the current shunt circuit 10 having PMOS transistors 16, 17, 18 with a reference transistor number of 1:p:pq has a gate width/gate length ratio of 1:p:pq. The configuration is substantially equivalent to the current shunt circuit 10 having PMOS transistors 16, 17 and 18. FIG. In addition, the current dividing circuit 80 having the NMOS transistors 85, 86, 87 whose number of reference transistors is 1:p:p·q is equivalent to the NMOS transistors whose gate width/gate length ratio is 1:p:p·q. The configuration is substantially equivalent to the current dividing circuit 80 having 85, 86 and 87. FIG.
The embodiments and modifications thereof described above are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

1A to 1F reference voltage generation circuit 3 power supply terminals 10, 80, 90 current shunt circuits 11a, 11b, 81, 91a, 91b input terminal 12 power supply input terminals 13a to 13c, 83a to 83c, 93a to 93c output terminals 15, 85- 87, 96 to 98 NMOS transistors 16 to 18, 95 PMOS transistors 20, 30 resistor diode circuits 22, 23, 32 resistor 40 feedback control circuit 41 differential amplifier circuit 43 output terminal 50 resistor voltage dividing circuit (resistor circuit)
51, 52 resistor 55 resistor circuit 57 voltage source 60 output terminals 71 to 75 phase compensation circuits 741, 751 resistors 742, 752 capacitor 77 resistors C1 to C3 capacitors D1, D2 diode

Claims (5)

a first input terminal and a second input terminal, a power input terminal, first to third output terminals, a gate connected to the first input terminal, and a drain connected to the power input terminal and a source, the first field effect transistor electrically connected to a first power supply via the power input terminal, the source connected to the source of the first field effect transistor; a second field effect transistor including a gate connected to the second input terminal and a drain connected to the first output terminal; and a source connected to the source of the first field effect transistor. and a third field effect transistor including a gate connected to the second input terminal, a drain connected to the second output terminal, and the source of the first field effect transistor. a current shunt circuit having a source, a gate connected to the second input, and a fourth field effect transistor including a drain connected to the third output;
a first resistive diode circuit having a resistor and a diode, one end of which is connected to the first output end of the current shunt circuit and the other end of which is connected to a second power supply;
a second resistive diode circuit having a resistor and a diode, one end of which is connected to the second output end of the current shunt circuit and the other end of which is connected to the second power supply;
a first input terminal connected to the one end of the first resistance diode circuit; a second input terminal connected to the one end of the second resistance diode circuit; and the first input terminal of the current shunting circuit. a feedback control circuit including an output terminal connected to the input terminal of
a resistor circuit having a resistor, one end of which is connected to the third output end of the current shunt circuit and the other end of which is connected to the second power supply;
an output terminal connected to the third output terminal of the current shunt circuit and the one terminal of the resistance circuit;
the second input end of the current shunting circuit is electrically connected to the second power supply;
said first field effect transistor having a first polarity being one of n-type and p-type;
A reference voltage generating circuit, wherein said second to fourth field effect transistors have a second polarity which is the other of said n-type and p-type. a first input terminal and a second input terminal, a power input terminal, first to third output terminals, a gate connected to the first input terminal, and a drain connected to the power input terminal and a source, the first field effect transistor electrically connected to a first power supply via the power input terminal, the source connected to the source of the first field effect transistor; a second field effect transistor including a gate connected to the second input terminal and a drain connected to the first output terminal; and a source connected to the source of the first field effect transistor. and a third field effect transistor including a gate connected to the second input terminal, a drain connected to the second output terminal, and the source of the first field effect transistor. a current shunt circuit having a source, a gate connected to the second input, and a fourth field effect transistor including a drain connected to the third output;
a first resistive diode circuit having a resistor and a diode, one end of which is connected to the first output end of the current shunt circuit and the other end of which is connected to a second power supply;
a second resistive diode circuit having a resistor and a diode, one end of which is connected to the second output end of the current shunt circuit and the other end of which is connected to the second power supply;
a first input terminal connected to the one end of the first resistance diode circuit; a second input terminal connected to the one end of the second resistance diode circuit; and the first input terminal of the current shunting circuit. a feedback control circuit including an output terminal connected to the input terminal of
a resistor circuit having a resistor, one end of which is connected to the third output end of the current shunt circuit and the other end of which is connected to the second power supply;
an output terminal connected to the third output terminal of the current shunt circuit and the one terminal of the resistance circuit;
said first field effect transistor having a first polarity being one of n-type and p-type;
the second to fourth field effect transistors have a second polarity that is the other of the n-type and p-type;
The resistor circuit includes a first resistor and a second resistor connected in series, and a connection point between the first resistor and the second resistor is the second input terminal of the current shunt circuit. A reference voltage generation circuit , characterized in that it is a connected resistance voltage dividing circuit. 2. The reference voltage generation circuit according to claim 1 , further comprising a voltage source connected between said second input terminal of said current shunt circuit and said second power supply. a first input terminal and a second input terminal, a power input terminal, first to third output terminals, a gate connected to the first input terminal, and a drain connected to the power input terminal and a source, the first field effect transistor electrically connected to a first power supply via the power input terminal, the source connected to the source of the first field effect transistor; a second field effect transistor including a gate connected to the second input terminal and a drain connected to the first output terminal; and a source connected to the source of the first field effect transistor. and a third field effect transistor including a gate connected to the second input terminal, a drain connected to the second output terminal, and the source of the first field effect transistor. a current shunt circuit having a source, a gate connected to the second input, and a fourth field effect transistor including a drain connected to the third output;
a first resistive diode circuit having a resistor and a diode, one end of which is connected to the first output end of the current shunt circuit and the other end of which is connected to a second power supply;
a second resistive diode circuit having a resistor and a diode, one end of which is connected to the second output end of the current shunt circuit and the other end of which is connected to the second power supply;
a first input terminal connected to the one end of the first resistance diode circuit; a second input terminal connected to the one end of the second resistance diode circuit; and the first input terminal of the current shunting circuit. a feedback control circuit including an output terminal connected to the input terminal of
a resistor circuit having a resistor, one end of which is connected to the third output end of the current shunt circuit and the other end of which is connected to the second power supply;
an output terminal connected to the third output terminal of the current shunt circuit and the one terminal of the resistance circuit;
The reference voltage generating circuit, wherein the second input terminal of the current shunt circuit is electrically connected to the third output terminal of the current shunt circuit. a first phase compensation circuit including a capacitor connected between the output terminal of the feedback control circuit and the second power supply; a capacitor including a first phase compensation circuit connected between the output terminal and the second power supply; a second phase compensation circuit, including a capacitor, connected between the second input terminal and the third output terminal of the current shunting circuit; a third phase compensation circuit, including a capacitor; a fourth phase compensation circuit connected between the first output terminal of the current shunt circuit and the first resistor diode circuit and between the second power supply and a capacitor, the current shunt circuit At least one of the five phase compensation circuits of the fifth phase compensation circuit connected between the second output terminal of and the second resistor diode circuit and between the second power supply 5. The reference voltage generation circuit according to claim 1, comprising two phase compensation circuits .

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