JP2020201754A5 - A current shunt circuit and a reference voltage generation circuit having the current shunt circuit - Google Patents
A current shunt circuit and a reference voltage generation circuit having the current shunt circuit Download PDFInfo
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Description
本発明は、電流分流回路及び当該電流分流回路を有する基準電圧発生回路に関する。 The present invention relates to a current shunt circuit and a reference voltage generation circuit having the current shunt circuit .
本発明は、上記課題を解決するため、電源電圧が急激に変動した場合においても、当該変動に起因する出力電圧の振幅の変動を低減可能な電流分流回路及び当該電流分流回路を有する基準電圧発生回路を提供することを目的とする。 In order to solve the above problems, the present invention has a current shunt circuit capable of reducing fluctuations in the output voltage amplitude caused by the fluctuations even when the power supply voltage suddenly fluctuates, and a reference voltage generation having the current shunt circuit. The purpose is to provide a circuit.
本発明に係る基準電圧発生回路は、上述した課題を解決するため、第１の入力端及び第２の入力端と、電源入力端と、第１から第３の出力端と、前記第１の入力端と接続されるゲートと、前記電源入力端と接続されるドレインと、ソースとを含み、前記電源入力端を介して第１の電源と電気的に接続される第１の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第１の出力端と接続されるドレインとを含む第２の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第２の出力端と接続されるドレインを含む第３の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第３の出力端と接続されるドレインを含む第４の電界効果トランジスタと、を有する電流分流回路と、抵抗及びダイオードを有し、一端が前記電流分流回路の前記第１の出力端と接続され、他端が第２の電源に接続される第１の抵抗ダイオード回路と、抵抗及びダイオードを有し、一端が前記電流分流回路の前記第２の出力端と接続され、他端が前記第２の電源に接続される第２の抵抗ダイオード回路と、前記第１の抵抗ダイオード回路の前記一端と接続される第１の入力端と、前記第２の抵抗ダイオード回路の前記一端と接続される第２の入力端と、前記電流分流回路の前記第１の入力端と接続される出力端と、を含む帰還制御回路と、抵抗を有し、一端が前記電流分流回路の前記第３の出力端と接続され、他端が前記第２の電源に接続される抵抗回路と、前記電流分流回路の前記第３の出力端及び前記抵抗回路の前記一端と接続される出力端子と、を備え、前記第１の電界効果トランジスタは、ｎ型及びｐ型の一方である第１の極性を有し、前記第２から第４の電界効果トランジスタは、前記ｎ型及びｐ型の他方である第２の極性を有することを特徴とする。
本発明に係る電流分流回路は、上述した課題を解決するため、第１の入力端及び第２の入力端と、電源入力端と、第１から第３の出力端と、前記第１の入力端と接続されるゲートと、前記電源入力端と接続されるドレインと、ソースとを含み、前記電源入力端を介して第１の電源と電気的に接続される第１の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第１の出力端と接続されるドレインとを含む第２の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第２の出力端と接続されるドレインを含む第３の電界効果トランジスタと、前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第３の出力端と接続されるドレインを含む第４の電界効果トランジスタと、を有し、前記第１の電界効果トランジスタは、ｎ型及びｐ型の一方である第１の極性を有し、前記第２から第４の電界効果トランジスタは、前記ｎ型及びｐ型の他方である第２の極性を有することを特徴とする。
In the reference voltage generation circuit according to the present invention, in order to solve the above-mentioned problems, the first input end, the second input end, the power supply input end, the first to third output ends, and the first A first field effect transistor that includes a gate connected to the input end, a drain connected to the power input end, and a source, and is electrically connected to the first power source via the power input end. A second field effect including a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the first output end. A third electric field including a transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the second output end. A fourth including an effect transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the third output end. A first that has a current diversion circuit with a field effect transistor, a resistor and a diode, one end connected to the first output end of the current diversion circuit and the other end connected to a second power source. A second resistance transistor circuit having a resistance transistor circuit and a resistor and a transistor, one end of which is connected to the second output end of the current diversion circuit and the other end of which is connected to the second power supply, and the above. A first input end connected to the one end of the first resistance transistor circuit, a second input end connected to the one end of the second resistance transistor circuit, and the first of the current diversion circuit. It has a feedback control circuit including an output end connected to an input end and a resistor, one end connected to the third output end of the current diversion circuit and the other end connected to the second power supply. The first field effect transistor is one of n-type and p-type. The second to fourth field effect transistors have a first polarity, which is the other of the n-type and the p-type.
In order to solve the above-mentioned problems, the current divergence circuit according to the present invention has a first input end, a second input end, a power supply input end, first to third output ends, and the first input. A first field effect transistor that includes a gate connected to the end, a drain connected to the power input end, and a source, and is electrically connected to the first power supply via the power input end. A second field effect transistor including a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the first output end. And a third field effect including a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the second output end. A fourth field including a transistor, a source connected to the source of the first field effect transistor, a gate connected to the second input end, and a drain connected to the third output end. The first field-effect transistor has an effect transistor, the first field-effect transistor has a first polarity that is one of the n-type and the p-type, and the second to fourth field-effect transistors have the n-type and the p-type. It is characterized by having a second polarity, which is the other of the p-type.
以下、本発明の実施形態に係る電流分流回路及び当該電流分流回路を有する基準電圧発生回路を、図面を参照して説明する。
［第１の実施形態］
図１は、第１の実施形態に係る電流分流回路及び当該電流分流回路を有する基準電圧発生回路の一例である電流分流回路１０及び基準電圧発生回路１Ａの構成を示す回路図である。
Hereinafter, the current shunt circuit according to the embodiment of the present invention and the reference voltage generation circuit having the current shunt circuit will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit diagram showing the configurations of the current shunt circuit 10 and the reference voltage generation circuit 1A, which are examples of the current shunt circuit according to the first embodiment and the reference voltage generation circuit having the current shunt circuit.
［第３の実施形態］
図５は、第３の実施形態に係る電流分流回路及び当該電流分流回路を有する基準電圧発生回路の一例である電流分流回路８０及び基準電圧発生回路１Ｄの構成を示す回路図である。
[Third Embodiment]
FIG. 5 is a circuit diagram showing the configurations of the current shunt circuit 80 and the reference voltage generation circuit 1D, which are examples of the current shunt circuit according to the third embodiment and the reference voltage generation circuit having the current shunt circuit.
図６は、第１の変形例に係る電流分流回路及び当該電流分流回路を有する基準電圧発生回路の一例である電流分流回路９０及び基準電圧発生回路１Ｅの構成例を示す回路図である。図７は、第２の変形例に係る電流分流回路及び当該電流分流回路を有する基準電圧発生回路の一例である電流分流回路９０及び基準電圧発生回路１Ｆの構成例を示す回路図である。 FIG. 6 is a circuit diagram showing a configuration example of the current shunt circuit 90 and the reference voltage generation circuit 1E, which are examples of the current shunt circuit according to the first modification and the reference voltage generation circuit having the current shunt circuit . FIG. 7 is a circuit diagram showing a configuration example of the current shunt circuit 90 and the reference voltage generation circuit 1F, which are examples of the current shunt circuit according to the second modification and the reference voltage generation circuit having the current shunt circuit .
Claims (7)
抵抗及びダイオードを有し、一端が前記電流分流回路の前記第１の出力端と接続され、他端が第２の電源に接続される第１の抵抗ダイオード回路と、
抵抗及びダイオードを有し、一端が前記電流分流回路の前記第２の出力端と接続され、他端が前記第２の電源に接続される第２の抵抗ダイオード回路と、
前記第１の抵抗ダイオード回路の前記一端と接続される第１の入力端と、前記第２の抵抗ダイオード回路の前記一端と接続される第２の入力端と、前記電流分流回路の前記第１の入力端と接続される出力端と、を含む帰還制御回路と、
抵抗を有し、一端が前記電流分流回路の前記第３の出力端と接続され、他端が前記第２の電源に接続される抵抗回路と、
前記電流分流回路の前記第３の出力端及び前記抵抗回路の前記一端と接続される出力端子と、を備え、
前記第１の電界効果トランジスタは、ｎ型及びｐ型の一方である第１の極性を有し、
前記第２から第４の電界効果トランジスタは、前記ｎ型及びｐ型の他方である第２の極性を有する
ことを特徴とする基準電圧発生回路。 A first input end, a second input end, a power input end, a first to third output ends, a gate connected to the first input end, and a drain connected to the power input end. A first field effect transistor including a source and electrically connected to the first power source via the power input end, and a source connected to the source of the first field effect transistor. A second field-effect transistor including a gate connected to the second input end and a drain connected to the first output end, and a source connected to the source of the first field-effect transistor. , A third field-effect transistor including a gate connected to the second input end, a drain connected to the second output end, and the source of the first field-effect transistor. A current diversion circuit having a source, a gate connected to the second input end, and a fourth field effect transistor including a drain connected to the third output end.
A first resistance diode circuit having a resistor and a diode, one end connected to the first output end of the current shunt circuit and the other end connected to a second power source.
A second resistance diode circuit having a resistor and a diode, one end connected to the second output end of the current shunt circuit and the other end connected to the second power source.
A first input end connected to the end of the first resistance diode circuit, a second input end connected to the end of the second resistance diode circuit, and the first of the current shunt circuit. The feedback control circuit, including the input end and the output end connected to,
A resistance circuit having a resistance, one end connected to the third output end of the current shunt circuit and the other end connected to the second power supply.
The third output end of the current shunt circuit and the output terminal connected to the one end of the resistance circuit are provided.
The first field effect transistor has a first polarity that is one of n-type and p-type.
The second to fourth field effect transistors are reference voltage generation circuits having a second polarity, which is the other of the n-type and the p-type.
電源入力端と、Power input end and
第１から第３の出力端と、With the first to third output ends,
前記第１の入力端と接続されるゲートと、前記電源入力端と接続されるドレインと、ソースとを含み、前記電源入力端を介して第１の電源と電気的に接続される第１の電界効果トランジスタと、A first that includes a gate connected to the first input end, a drain connected to the power input end, and a source, and is electrically connected to the first power source via the power input end. Field effect transistor and
前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第１の出力端と接続されるドレインとを含む第２の電界効果トランジスタと、A second field-effect transistor including a source connected to the source of the first field-effect transistor, a gate connected to the second input end, and a drain connected to the first output end. When,
前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第２の出力端と接続されるドレインを含む第３の電界効果トランジスタと、A source connected to the source of the first field effect transistor, a gate connected to the second input end, and a third field effect transistor including a drain connected to the second output end. ,
前記第１の電界効果トランジスタの前記ソースと接続されるソースと、前記第２の入力端と接続されるゲートと、前記第３の出力端と接続されるドレインを含む第４の電界効果トランジスタと、を有し、A source connected to the source of the first field effect transistor, a gate connected to the second input end, and a fourth field effect transistor including a drain connected to the third output end. Have,
前記第１の電界効果トランジスタは、ｎ型及びｐ型の一方である第１の極性を有し、The first field effect transistor has a first polarity that is one of n-type and p-type.
前記第２から第４の電界効果トランジスタは、前記ｎ型及びｐ型の他方である第２の極性を有することを特徴とする電流分流回路。The second to fourth field effect transistors are current shunting circuits characterized by having a second polarity, which is the other of the n-type and the p-type.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019108772A JP7292117B2 (en) | 2019-06-11 | 2019-06-11 | Reference voltage generator |
| CN202010446240.XA CN112068625A (en) | 2019-06-11 | 2020-05-25 | Reference voltage generating circuit |
| TW109117545A TW202046045A (en) | 2019-06-11 | 2020-05-26 | Reference voltage generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019108772A JP7292117B2 (en) | 2019-06-11 | 2019-06-11 | Reference voltage generator |
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| JP2020201754A JP2020201754A (en) | 2020-12-17 |
| JP2020201754A5 true JP2020201754A5 (en) | 2022-03-08 |
| JP7292117B2 JP7292117B2 (en) | 2023-06-16 |
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| JP2019108772A Active JP7292117B2 (en) | 2019-06-11 | 2019-06-11 | Reference voltage generator |
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| JP (1) | JP7292117B2 (en) |
| CN (1) | CN112068625A (en) |
| TW (1) | TW202046045A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3586073B2 (en) * | 1997-07-29 | 2004-11-10 | 株式会社東芝 | Reference voltage generation circuit |
| JP2003173212A (en) * | 2001-12-06 | 2003-06-20 | Seiko Epson Corp | Cmos reference voltage generating circuit and power supply monitoring circuit |
| JP2005038482A (en) * | 2003-07-17 | 2005-02-10 | Toshiba Microelectronics Corp | Semiconductor device |
| US7199646B1 (en) * | 2003-09-23 | 2007-04-03 | Cypress Semiconductor Corp. | High PSRR, high accuracy, low power supply bandgap circuit |
| JP5078502B2 (en) * | 2007-08-16 | 2012-11-21 | セイコーインスツル株式会社 | Reference voltage circuit |
| JP4759015B2 (en) * | 2008-04-25 | 2011-08-31 | 株式会社リコー | Constant voltage circuit |
| JP6638340B2 (en) * | 2015-11-12 | 2020-01-29 | セイコーエプソン株式会社 | Circuit device, oscillator, electronic equipment and moving object |
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