JP3059263B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type analog-to-digital converter. In the successive approximation type analog-digital converter, a resistor for zero offset adjustment is connected in series to a number of ladder resistors for generating a reference voltage, and the analog input is adjusted by adjusting the resistance value of the zero offset adjustment resistor. When the voltage becomes “0”, the digital output signal can be adjusted so as to become “0”. Then, it is required to simplify the adjustment operation.

[0002]

2. Description of the Related Art An example of a conventional two-branch successive approximation type analog-to-digital converter will be described with reference to FIG. 3. A ladder resistor 1 is formed by connecting a number of resistors R having the same resistance value in series. One end of the resistor 1 has a reference power supply voltage A
VR is supplied, and the other end is connected to a low-potential-side power supply Vss via a zero-offset adjusting resistor R / 2 having a resistance half of the resistor R.

A large number of reference voltages obtained by dividing the reference power supply voltage AVR by the respective resistors R are output to a sampling and holding switching circuit 3 via transistors Trs as switches. That is, half of the high potential side of all the transistors Trs is a P-channel MOS.
A low-potential half is formed by an N-channel MOS transistor, and based on the operation of the successive approximation control unit 2, one of the transistors Trs is turned on and one of the reference voltages is switched to a sampling and holding switching circuit. 3 is output.

An analog input signal Ain is also input to the sampling and holding switching circuit 3, and the sampling and holding switching circuit 3 supplies either the reference voltage or the analog input signal Ain to a sampling and holding capacitor C1.
Is output to the chopper type comparator 4 through. The chopper type comparator 4 includes an inverter circuit 5 and an N-channel MOS transistor Trc connected in parallel to the inverter circuit 5, and performs sampling by the sampling and holding switching circuit 3 based on the operation of the successive approximation control unit 2. During the sampling operation in which the analog input signal Ain is input to the hold capacitor C1, the transistor Trc is turned on, the input / output terminal voltage of the inverter circuit 5 is maintained at the threshold voltage Vth of the inverter circuit 5, and the sampling hold switching circuit 3, the transistor Trc is turned off during the conversion operation in which the reference voltage is input to the sampling and holding capacitor C1.

[0005] The conversion operation of the analog-to-digital converter configured as described above will be described.
When rc is turned on and the input / output terminal voltage of the inverter circuit 5 is maintained at the threshold voltage Vth of the inverter circuit 5, the analog input signal Ain is input to the capacitor C1 via the sampling hold switching circuit 3. The electric charge is accumulated in the capacitor C1 based on the voltage level of the analog input signal Ain at that time, the electrode of the capacitor C1 on the inverter circuit 5 side becomes the threshold value Vth of the inverter circuit 5, and the sampling hold switching circuit 3 side Are set to the voltage level of the analog input signal Ain, and sampling and holding are performed.

In this state, the transistor Trc is turned off, the sampling and holding switching circuit 3 is switched, and the transistor Trs, which is located in the middle of the many transistors Trs, is turned on to set the reference voltage at half the reference power supply voltage AVR. The voltage is input to the capacitor C1. Then
When the reference voltage is higher than the voltage level of the analog input signal Ain stored in the capacitor C1, the input voltage level of the inverter circuit 5 becomes higher than the threshold value Vth and the output signal of the inverter circuit 5 becomes L level. On the contrary, when the reference voltage is lower than the voltage level of the analog input signal Ain stored in the capacitor C1, the input voltage level of the inverter circuit 5 becomes equal to the threshold voltage Vin.
th, the output signal of the inverter circuit 5 becomes H level.

In this manner, the successive approximation control unit 2 selects the transistor Trs to be turned on next depending on whether the output signal of the inverter circuit 5 is at the H level or the L level, and the two-branch successive approximation is sequentially performed. When the sampled and held analog input signal Ain is converted into a digital signal having a predetermined number of bits, a new analog input signal Ain is input to the capacitor C1, and a similar successive comparison operation is performed.

[0008]

In the above-mentioned digital-analog converter, the charge amount of the capacitor C1 is actually inputted during the sampling and holding operation due to the capacity of the transistor Trc of the chopper type comparator 4 and other causes. it may be shifted for the analog amount that has been. Therefore, the ladder resistor 1 has a resistor R for zero offset adjustment.
/ 2 is formed, and the deviation of the voltage level of the sampled analog input signal Ain is corrected by adjusting the resistance value of the resistor R / 2 to an optimum value by trial production.

However, a resistor R for zero offset adjustment is used.
/ 2 is formed by the diffusion resistance of the same process as the other ladder resistances. Therefore, in order to change the resistance value of the resistance R / 2, it is necessary to change a mask for forming the diffusion resistance. The work is complicated and the cost increases. When the resistance value of the resistor R / 2 is changed, the value of the current flowing through the ladder resistor 1 changes.
The reference voltage output from the device may change. Therefore, there arises a problem that conversion accuracy of the analog input signal Ain into a digital signal is reduced.

An object of the present invention is to make it possible to easily adjust a zero offset without changing the resistance value of a ladder resistor.

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, a ladder resistor 1 is formed by connecting a large number of resistors R having the same resistance value and a zero offset resistor R / 2 having a resistance value １ ／ of the resistance value in series to form the ladder resistor 1 . The reference power supply voltage AVR is connected to the end of the resistor R side.
And the zero offset resistor R / 2 side
Is supplied with the low potential side power supply Vss to the end of the ladder resistor 1.
A successive approximation type analog-to-digital converter which inputs one of the reference voltages, which are voltages between the terminals, and an analog input voltage to a chopper type comparator 4 via a first capacitor C1 and compares them. The switch 4 is provided with a switch circuit 6 via a second capacitor C2. When the reference voltage is inputted to the chopper type comparator 4, the switch circuit 6 is provided between the zero offset resistor R / 2. The second unit is configured to output the low-potential-side power supply Vss to the second capacitor C2 when an analog input voltage is input.

[0012]

According to the present invention, the offset voltage can be set to an arbitrary value.
Can be set.
It is necessary to adjust the resistance value of low offset resistor R / 2
And the zero offset is easily adjusted. Therefore,
Even if the offset amount is changed , the current value flowing through the ladder resistor 1 does not change . In addition, the chopper type comparator 4
Depending on various factors such as the parasitic capacitance of the transistor
It is possible to adjust the offset deviation.

[0013]

FIG. 2 shows an embodiment of the present invention.
It will be described according to. The same components as those in the conventional example will be described with the same reference numerals.

The ladder resistor 1, the successive approximation control unit 2, the sampling and holding switching circuit 3, the chopper type comparator 4 and the capacitor C1 of this embodiment have the same configuration as the conventional example, and their operations are also the same.

An input terminal of an inverter circuit 5 constituting the chopper type comparator 4 is connected to a switch circuit 6 via a second capacitor C2. The switch circuit 6 replaces the capacitor C2 with a zero offset adjusting resistor R / 2. And a low-potential-side power supply Vss via a transistor Tro. The switch circuit 6 and the transistor Tro are controlled by the successive approximation control unit 2 to operate in synchronization with the sampling and holding switching circuit 3 and the transistor Trc, and a sampling and holding operation in which the analog input signal Ain is input to the capacitor C1. Sometimes, the switch circuit 6 is connected to the transistor Tro side, and the transistor Tro is turned on. At the time of conversion operation in which the reference voltage is inputted to the capacitor C1, the switch circuit 6 is connected to the zero offset adjusting resistor R / 2 side. .

Next, the operation of the analog-to-digital converter configured as described above will be described. By the way, at the time of the sampling hold operation, the electric charge Q1 stored in the capacitors C1 and C2 is:

[0017]

Q1 = C1 · (Vth−Vin) + C2 · Vth = (C1 + C2) · Vth−C1 · Vin where C1 and C2 are the capacitances of the capacitors C1 and C2, and Vth
Is a threshold value of the inverter circuit, and Vin is a voltage value of the analog input signal.

On the other hand, the charge Q2 stored in the capacitors C1 and C2 during the conversion operation for converting the sampled and held analog input signal into a digital value is

[0019]

Q2 = C1 · (Vx−Vref) + C2 · (Vx−Voff) = (C1 + C2) · Vx−C1 · Vref−C2 · Voff where Vx is the input voltage of the inverter circuit 5 during the conversion operation and Vref Is the reference voltage input from the ladder resistor 1, V
off is a voltage value input from the zero offset adjustment resistor R / 2.

Since Q1 and Q2 are equal,

[0021]

(C1 + C2) １Vth-C1 ・ Vin = (C1 + C2) ・ Vx-C1 ・ Vref-C2 ・ Voff

That is,

[0023]

Vx = Vth−C1 / (C1 + C2) · Vin + C1 / (C1 + C2) · Vref + C2 / (C1 + C2) · Voff Here, if C1 / (C1 + C2) is α,

[0024]

Vx = Vth−α [(Vin−Vref) −Voff · C2 / C1] Therefore, Vx is reduced by a voltage corresponding to Voff · C2 / C1, and Vx caused by the parasitic capacitance of the transistor Trc is obtained.
Act to offset the rise in x. Then, the offset amount is changed by changing the capacitance value of the capacitor C2 without adjusting the resistance value of the zero offset adjustment resistor R / 2 by changing the mask or by changing the voltage Voff applied to the capacitor C2. , The capacitance value of the capacitor C2 or the voltage Vof
The amount of zero offset can be easily adjusted based on the method of applying f, and there is no need to change the mask for forming the ladder resistor 1. Furthermore, since the zero offset amount can be changed without adjusting the resistance value of the zero offset adjusting resistor R / 2 by changing the mask, the current value flowing through the ladder resistor 1 changes even if the zero offset amount is changed. As a result, it is possible to prevent a decrease in conversion accuracy into a digital signal.

[0025]

[0026]

As described above in detail, the present invention has an excellent effect that the zero offset can be easily adjusted without changing the resistance value of the ladder resistor.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ladder resistance 4 Chopper type comparator 7 Voltage supply circuit R resistance R / 2 Zero offset resistance AVR Reference power supply voltage Vss Low potential side power supply C1 First capacitance C2 Second capacitance

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] A plurality of resistors having the same resistance value and one of said resistors;
/ 2 and for zero offset resistance of the resistance value connected in series to form a ladder resistor, wherein a number of said ladder resistor resistance
The zero supplies a reference power supply voltage to the end of the anti-side
A low-potential-side power supply is supplied to the end of the offset resistor , and one of the reference voltages, which is the voltage between the terminals of the ladder resistor, and the analog input voltage are input to the chopper comparator via the first capacitor. A successive approximation type analog-digital converter, wherein a switch circuit is provided via a second capacitor in the chopper type comparator, and a reference voltage is input to the switch circuit in the chopper type comparator. When the analog input voltage is input, the intermediate portion of the zero offset resistor is output to the second capacitor, and when the analog input voltage is input, the low potential side power supply is output to the second capacitor. Analog-to-digital converter.