JP3471256B2 - A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an A / D converter, and more particularly to an A / D converter using a comparator.

[0002]

Description of the Related Art Conventionally, a general A / D converter has been composed of a D / A converter, a comparator, a controller circuit, and the like. In the conventional A / D converter, the input voltage and the voltage output from the D / A converter are compared using a comparator, and the signal input to the D / A converter when the difference disappears. Was used as the digital signal value. Generally MOSFET as a comparator
The one using the differential amplifier is used.

[0003]

[Problems to be Solved by the Invention] However, the conventional A /
In the D converter, if a voltage lower than the threshold voltage of the MOSFET used for the comparator is input, the operation of the comparator is affected and there is a risk that an error may occur in the digital signal value.

[0004]

In order to solve the above problems, an analog / digital conversion circuit having a typical configuration of the present invention is provided with an input voltage, and a sample hold circuit for holding the input voltage, Comparing the digital / analog converter that outputs a voltage value based on the digital signal given from the controller circuit with the input voltage value held in the sample hold circuit and the voltage value output from the digital / analog converter, A first comparator that outputs a comparison result signal, and a second comparison that outputs the comparison result signal by comparing the input voltage value held in the sample hold circuit with the voltage value output from the digital / analog converter And the comparison result signal of the first comparator or the second comparison signal based on the select signal output from the controller circuit.
And a controller circuit that selectively outputs the comparison result signal of the comparator and a controller circuit that determines the output signal according to the comparison result signal supplied from the selector.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit diagram showing an A / D converter according to a first embodiment of the present invention. An embodiment of the present invention will be described below with reference to FIG.

The A / D converter in the present invention comprises a controller circuit 101, a D / A converter 102, a sample hold circuit 103, comparators 104 and 105, and a selector 106.

From the controller circuit 101, a digital signal S
1 is output. The digital signal S1 is input to the D / A converter 102, and the voltage V1 based on the value of the digital signal S1 is output. The input voltage VIN is input to the sample hold circuit 103 and holds this voltage.

The voltage VIN from the sample hold circuit 103 is input to the non-inverting input terminal of the comparator 104, and the voltage V1 from the D / A converter 102 is input to the inverting input terminal. The comparator 104 outputs an H level comparison result signal when the voltage V1 input to the inverting input terminal is lower than the voltage VIN input to the non-inverting input terminal, and when the voltage V1 is higher than the voltage VIN. Outputs an L level comparison result signal.

The voltage VIN from the sample hold circuit 103 is input to the non-inverting input terminal of the comparator 105, and the voltage V1 from the D / A converter 102 is input to the inverting input terminal. The comparator 105 outputs an H level comparison result signal when the voltage V1 input to the inverting input terminal is lower than the voltage VIN input to the non-inverting input terminal, and when the voltage V1 is higher than the voltage VIN. Outputs an L level comparison result signal.

The selector 106 is based on the select signal SEL from the controller circuit 101, and is output to the comparator 104 or the comparator 10.
Either one of the 5 output signals is selected and output to the controller circuit 101. In this embodiment, the select signal S
The most significant bit of the digital signal input to the D / A converter 102 is given as EL.

FIG. 2 is a circuit diagram showing the comparator 104 in the present embodiment. The inverting input terminal of the comparator 104 is the gate electrode of the NMOS transistor 201, and the non-inverting input terminal is the gate electrode of the NMOS transistor 202. NMOS transistor 2
The voltage V1 from the D / A converter 102 is input to the gate electrode of 01. The drain of the NMOS transistor 201 serves as a resistor P
It is connected to the power supply potential Vdd via the MOS transistor 203. The source of the NMOS transistor 201 serves as a constant current source N
It is connected to the ground potential Vss via the MOS transistor 205.

The voltage VIN from the sample hold circuit 103 is input to the gate electrode of the NMOS transistor 202. The drain of the NMOS transistor 202 serves as a resistance PMOS
It is connected to the power supply potential Vdd through the transistor 204. The source of the NMOS transistor 202 is an NMO that serves as a constant current source.
It is connected to the ground potential Vss via the S transistor 205.

The gate electrode of the PMOS transistor 206 is NMOS
Node between transistor 202 and PMOS transistor 204
It is connected to N1. The source of the PMOS transistor 206 is connected to the power supply potential Vdd, and the drain is the NMOS transistor 2
It is connected to the ground potential Vss via 07. An output terminal OUT that outputs the comparison result between the voltage V1 and the voltage VIN is connected between the PMOS transistor 206 and the NMOS transistor 207.

FIG. 3 is a circuit diagram showing the comparator 105 in the present embodiment. In the comparator 105, the voltage V1 from the D / A converter 102 is input to the gate electrode of the PMOS transistor 301. The drain of the PMOS transistor 301 serves as a resistance NMOS
It is connected to the ground potential Vss via the transistor 303. The source of the PMOS transistor 301 is a PMO that serves as a constant current source.
It is connected to the power supply potential Vdd through the S transistor 305.

The voltage VIN from the sample hold circuit 103 is input to the gate electrode of the PMOS transistor 302. The drain of the PMOS transistor 302 is an NMOS that serves as a resistor.
It is connected to the ground potential Vss via the transistor 304. The source of the PMOS transistor 302 is a PMO that serves as a constant current source.
It is connected to the power supply potential Vdd through the S transistor 305.

The gate electrode of the NMOS transistor 306 is a PMOS
It is connected between the transistor 302 and the NMOS transistor 304. The source of the NMOS transistor 306 is the ground potential Vss
The drain is connected to the power supply potential Vdd through the PMOS transistor 307. The output terminal OUT that outputs the comparison result of the voltage V1 and the voltage VIN is the NMOS transistor 306.
It is connected to the PMOS transistor 307.

The operation of the A / D converter of the present invention will be described below with reference to FIGS. 1, 2 and 3.

It is assumed that a value close to the power supply potential Vdd, such as 4.5 V, is input as the input voltage. If the input voltage is more than half of the power supply potential Vdd, the control circuit 101
The most significant bit of the digital signal output to the converter 102 is H level. Therefore, an H level signal is given to the selector as the selection signal SEL. When the selection signal SEL is at H level, the selector 106 outputs the output signal of the comparator 104 to the control circuit 101.

The operation of the comparator 104 will be described below.

The voltage VIN input to the non-inverting input terminal is
If it is higher than the voltage V1 input to the inverting input terminal, the NMOS
More current flows through the transistor 202. Therefore PMO
The voltage drop due to the S transistor 204 increases. Node N1 between NMOS transistor 202 and PMOS transistor 204
Becomes low, and the PMOS transistor 206 is turned on. By this operation, the comparison result outputs a signal of H level.

The voltage VIN input to the non-inverting input terminal is
When the voltage is lower than the voltage V1 input to the inverting input terminal, the operation is the reverse of the above. The current flowing through the NMOS transistor 202 is reduced, and the PMOS transistor 206 is also turned off. Therefore, an L level signal is output as the comparison result. The above is the operation of the comparator 104.

The controller circuit 101 determines the digital signal value based on the comparison result input from the comparator 104 through the selector 106. The digital signal value is determined by the voltage output from the D / A converter 102 and the input voltage VIN.
Is the point when they almost coincide.

The determined digital signal value is output as the output signal VOUT.

It is assumed that a value close to the ground potential Vss, such as 0.5 V, is input as the input voltage. If the input voltage is less than half of the power supply potential Vdd, the control circuit 101
The most significant bit of the digital signal output to the converter 102 is L level. Therefore, an L level signal is given to the selector as the selection signal SEL. When the selection signal SEL is at L level, the selector 106 outputs the output signal of the comparator 105 to the controller circuit 101.

The operation of the comparator 105 will be described below.

The voltage VIN input to the non-inverting input terminal is
If the voltage is higher than the voltage V1 input to the inverting input terminal, the PMOS
More current flows through the transistor 303, and less current flows through the PMOS transistor 302. Therefore, the voltage drop due to the NMOS transistor 304 is reduced. The voltage of the node between the PMOS transistor 302 and the NMOS transistor 304 becomes close to the ground potential Vss, and the NMOS transistor 306 is turned off. By this operation, the comparison result outputs a signal of H level.

The voltage VIN input to the non-inverting input terminal is
When the voltage is lower than the voltage V1 input to the inverting input terminal, the operation is the reverse of the above. The current flowing through the PMOS transistor 302 increases, and the NMOS transistor 306 is also turned off. Therefore, an L level signal is output as the comparison result. The above is the operation of the comparator 105.

The controller circuit 101 determines the digital signal value based on the comparison result input from the comparator 105 through the selector 106. The digital signal value is determined by the voltage output from the D / A converter 102 and the input voltage VIN.
Is the point when they almost coincide.

The determined digital signal value is output as the output signal VOUT.

As described above, according to the present embodiment, the input voltage
The comparator 104 is used in the range where VIN is close to the power supply potential Vdd, and the comparator 105 is used in the range where the input voltage VIN is close to the ground potential Vss.

By using two comparators, an accurate comparison result can be obtained without depending on the threshold value of the MOS transistor.

Further, in this embodiment, since the most significant bit output from the controller circuit is used for switching between the two comparators, it is not necessary to make a large change on the controller circuit side.

(Second Embodiment) FIG. 4 is a circuit diagram showing an A / D converter according to a second embodiment of the present invention. The second embodiment of the present invention will be described below with reference to FIG.

The A / D converter according to the second embodiment is a controller circuit 401, a D / A converter 402, a sample hold circuit 403, comparators 404 and 405, a selector 406, an operational amplifier 40.
7 and resistors 408 and 409.

The comparison result signal output from the comparator 405 and the select signal SEL output from the comparator 404 are input to the controller circuit 401. A digital signal S1 is output from the controller circuit 401.

The digital signal S1 is input to the D / A converter 402, and the voltage V1 based on the value of the digital signal S1 is output.
The input voltage VIN is input to the sample hold circuit 403,
Holds this voltage.

The voltage VIN from the sample hold circuit 403 is input to the non-inverting input terminal of the comparator 404, and the reference voltage Vref is input to the inverting input terminal. Comparator 4
04 outputs an H-level signal when the voltage Vref input to the inverting input terminal is lower than the voltage VIN input to the non-inverting input terminal, and outputs L when the voltage Vref is higher than the voltage VIN.
Output level signal. This signal is the select signal SEL
Is.

The reference voltage Vref is input to the non-inverting input terminal of the operational amplifier 407. Input voltage to the inverting input terminal
VIN is connected through resistor 408
Output voltage VIN 'of is connected via a resistor 409. In this case, the operational amplifier 407 operates as an inverting amplifier using the reference voltage Vref as a virtual ground voltage. That is, the output voltage VIN '
Is a value obtained by level-converting the input voltage VIN using the reference voltage Vref, and the operational amplifier 407 can be said to be a level conversion circuit.

The selector 406 selects either the output signal of VIN or VIN 'based on the select signal SEL from the comparator 404, and supplies it to the comparator 405.

The selector 4 is connected to the non-inverting input terminal of the comparator 405.
The voltage VIN or VIN ′ from 06 is input, and the voltage V1 from the D / A converter 402 is input to the inverting input terminal.

The comparator 405 outputs a signal of H level when the voltage VIN input to the non-inverting input terminal or the voltage V1 input to the inverting input terminal is lower than the voltage VIN ′ input to the non-inverting input terminal. The voltage V which is greater than the voltage VIN or VIN '
When 1 is high, the L level signal is output.

Comparator 404 in the second embodiment and
409 is the same as the comparator 104 (the comparator shown in FIG. 2) of the first embodiment.

The operation of this embodiment will be described in detail below with reference to FIG.

In the present embodiment, Vdd = 5V, reference voltage Vr
It is assumed that ef is 2.5V.

It is assumed that a value close to the power supply potential Vdd, such as 4.5 V, is input as the input voltage.

In the comparator 404, since the input voltage VIN is higher than the reference voltage Vref, the H level select signal SEL is output.

The selector 406 is an H level select signal SEL.
The output voltage VIN from the sample hold circuit is selected based on

The comparator 409 outputs the output voltage V1 from the D / A converter.
And the output voltage VIN from the selector are compared, and the comparison result is output to the controller circuit 401.

The control circuit 401 determines the digital signal value based on the comparison result input from the comparator 409. The digital signal value is determined when the voltage output from the D / A converter 402 and the input voltage VIN substantially match.

When an H level signal is given as the select signal SEL, the confirmed digital signal is output signal.
Output as VOUT.

It is assumed that a value close to the power supply potential Vss, such as 0.5 V, is input as the input voltage.

In the comparator 404, since the input voltage VIN is lower than the reference voltage Vref, the L-level select signal SEL is output.

The selector 406 is an L level select signal SEL.
The output voltage VIN ′ from the operational amplifier 405 is selected based on

The voltage VIN 'output from the operational amplifier 407 can be calculated by the following equation if the resistors 408 and 409 have the same value.

VIN '= Vref- (VIN-Vref) = 2Vref-VIN Therefore, in this case, VIN '= 4.5V.

The comparator 405 outputs the output voltage V1 from the D / A converter.
And the output voltage VIN ′ from the selector are compared, and the comparison result is output to the controller circuit 401.

The control circuit 401 determines the digital signal value based on the comparison result input from the comparator 409. The digital signal value is determined when the voltage output from the D / A converter 402 and the voltage VIN 'substantially match. However, the digital signal determined here is a value corresponding to VIN '.

Therefore, when the L level signal is given as the select signal SEL, the output digital signal VO
UT is a value obtained by logically inverting the determined signal value.

As a specific example, the power supply voltage Vdd is 5 V, and the A / D of 4 BIT
Consider the conversion. In the case of the above VIN = 0.5V, the digital signal value corresponding to VIN ′ is “1110”. If this is logically inverted to "0001", the output signal VOUT corresponding to VIN can be obtained.

As described above, according to the A / D converter of the second embodiment, the comparator 405 that outputs the comparison result to the controller circuit 401 is always supplied with a voltage equal to or higher than Vref. Therefore, it is possible to reduce the error generated in the digital signal value.

Further, the comparator 405 only has to compare the voltage values equal to or higher than Vref, and the range to be compared becomes small, so that the A / D conversion becomes faster.

(Third Embodiment) FIG. 5 is a circuit diagram showing an A / D converter according to a third embodiment of the present invention. The third embodiment of the present invention will be described below with reference to FIG.

The A / D converter in the third embodiment comprises a controller circuit 501, a D / A converter 502, a sample hold circuit 503, comparators 504 and 505, a selector 506, and a subtractor 507.

The comparison result signal output from the comparator 505 and the select signal SEL output from the comparator 504 are input to the controller circuit 501. A digital signal S1 is output from the controller circuit 501.

The digital signal S1 is input to the D / A converter 502, and the voltage V1 based on the value of the digital signal S1 is output.
The input voltage VIN is input to the sample hold circuit 503,
Holds this voltage.

The voltage VIN from the sample hold circuit 503 is input to the non-inverting input terminal of the comparator 504, and the reference voltage Vref is input to the inverting input terminal. Comparator 50
4 outputs an H level signal when the voltage Vref input to the inverting input terminal is lower than the voltage VIN input to the non-inverting input terminal, and outputs an L level signal when the voltage Vref is higher than the voltage VIN. Output a signal. This signal is the select signal SEL.

The reference voltage V is applied to one input terminal of the subtractor 507.
ref is input and VIN is input to the other input terminal. The subtractor 507 outputs a voltage VIN '= VIN-Vref obtained by subtracting the reference voltage from the input voltage. It can be said that the subtractor 507 is a level conversion circuit as in the second embodiment.

The selector 506 selects either the output signal of VIN or VIN 'based on the select signal SEL from the comparator 504, and supplies it to the comparator 505.

The selector 5 is connected to the non-inverting input terminal of the comparator 505.
The voltage VIN or VIN ′ from 06 is input, and the voltage V1 from the D / A converter 502 is input to the inverting input terminal.

The comparator 507 outputs an H-level signal when the voltage VIN or VIN ′ input to the non-inverting input terminal is lower than the voltage VIN or VIN ′ input to the non-inverting input terminal. The voltage V which is greater than the voltage VIN or VIN '
When 1 is high, the L level signal is output.

The comparator 504 in the third embodiment and
505 is the same as the comparator 105 (the comparator shown in FIG. 3) of the first embodiment. That is, it is assumed that the gate of the PMOS transistor receives the input signal.

The operation of this embodiment will be described in detail below with reference to FIG.

In the present embodiment, Vdd = 5V, reference voltage
It is assumed that Vref is 2.5V.

It is assumed that a value close to the power supply potential Vss, such as 0.5 V, is input as the input voltage.

In the comparator 504, since the input voltage VIN is higher than the reference voltage Vref, the H-level select signal SEL is output.

The selector 506 is an H level select signal SEL.
The output voltage VIN from the sample hold circuit is selected based on

The comparator 505 compares the output voltage V1 from the D / A converter 502 with the output voltage VIN from the selector, and outputs the comparison result to the controller circuit 501.

The control circuit 501 determines the digital signal value based on the comparison result input from the comparator 505. The digital signal value is determined when the voltage output from the D / A converter 502 and the input voltage VIN substantially match.

When an H level signal is given as the select signal SEL, the determined digital signal is output signal.
Output as VOUT.

It is assumed that a value close to the power supply potential Vdd, such as 4.5 V, is input as the input voltage.

In the comparator 504, since the input voltage VIN is lower than the reference voltage Vref, the L level select signal SEL is output.

The selector 506 is an L level select signal SEL.
The output voltage VIN ′ from the subtractor 505 is selected based on

Therefore, in this case, VIN ′ = 2.0V.

The comparator 505 outputs the output voltage V1 from the D / A converter.
And the output voltage VIN ′ from the selector are compared, and the comparison result is output to the controller circuit 501.

The control circuit 501 determines the digital signal value based on the comparison result input from the comparator 505. The digital signal value is determined when the voltage output from the D / A converter 502 and the voltage VIN 'substantially match. The digital signal determined here is a value corresponding to VIN '.

Therefore, when an L level signal is given as the select signal SEL, the digital signal VO to be output is output.
UT is a value obtained by logically inverting a part of the determined signal value.

As a concrete example, the power supply voltage Vdd is 5 V, and the A / D of 4 BIT is used.
Consider the conversion. In the case of VIN = 4.5V, the digital signal value corresponding to VIN '= 2.0V is "0110". If the most significant bit is logically inverted to be "1110", the output signal VOUT corresponding to VIN can be obtained. Similarly, select signal SEL
When a signal of L level is given as, the most significant bit is logically inverted to always obtain a correct digital signal value.

As described above, according to the A / D converter of the third embodiment, the comparator 505 that outputs the comparison result to the controller circuit 501 is always supplied with a voltage equal to or lower than Vref as an input voltage. Therefore, it is possible to reduce the error generated in the digital signal value.

Further, since the subtractor can be composed of a capacitor or the like, the circuit area can be further reduced.

(Fourth Embodiment) FIG. 6 is a circuit diagram showing an A / D converter according to a fourth embodiment of the present invention. The fourth embodiment of the present invention will be described below with reference to FIG.

The A / D converter in the fourth embodiment is the controller circuit 601, the D / A converter 602, the sample hold circuit 603, the capacitors C0 to C4, the switches SW1 to SW5, and the comparator 6.
It is composed of 04.

The comparison result signal output from the comparator 604 is input to the controller circuit 601. Controller circuit
The digital signal S1 is output from 601.

The digital signal S1 is input to the D / A converter 602, and the voltage V1 based on the value of the digital signal S1 is output.

The sample hold circuit 603 has an input voltage VIN
Is input and holds this voltage. This sample-hold circuit has a capacitor C that holds the input voltage VIN.
0 is present.

The input voltage VIN is applied to one input terminal of the comparator.
Are connected via switch SW1. The voltage V1 is connected to the other input terminal via switches SW2 and SW3.

Capacitors C1 to C3 are capacitors having the same capacitance value as C0, and are respectively a node between SW1 and the input terminal of the comparator and GND, a node between switches SW2 and SW3 and a G node.
It is connected between ND and the node between switch SW3 and the input terminal of the comparator and GND. The switches SW4 and SW5 are connected between the input terminal of the comparator and GND, respectively. The comparator 604 used here is the same as the comparator 105 (shown in FIG. 3) in the first embodiment.

The operation of the fourth embodiment of the present invention will be described below with reference to FIG.

The input voltage VIN is applied to the sample hold circuit 603.
Is input and the capacitor C0 holds this voltage.

From the controller circuit 601, the digital signal S
1 is output.

The digital signal S1 is input to the D / A converter 602, and the output voltage V1 of the D / A converter 602 based on the value of the digital signal S1 is output. At this time, the switch SW2 is turned on and the voltage V1 is held in the capacitor C2.

After that, after a new charge is not supplied to the capacitor C0, that is, after the switch (not shown) connected to the capacitor C0 in the sample hold circuit is opened, the switch SW1 is turned on. . Then, the input voltage VIN is divided and the capacitor C
The voltage between electrodes 1 is VIN / 2.

At about the same time as this, the switch SW2 is opened and the switch SW3 is turned on, whereby the D / A converter 60
The output voltage V1 of 2 is divided, and the voltage between the electrodes of the capacitor C3 becomes V1 / 2.

VIN / is applied to each input terminal of the comparator 604.
2. The voltage of V1 / 2 is input, and the final digital signal value is determined by comparing this value.

With the comparison result confirmed, the switches SW4, S
W5 turns on and releases the held voltage. After that, the sample and hold circuit reads the next analog signal value, and the same operation is repeated thereafter.

As described above, according to the A / D converter of the fourth embodiment, the input voltage of the comparator 606 that outputs the comparison result to the controller circuit 601 is always converted into a half value.

That is, in the fourth embodiment, the capacitor C0
By using C3, both the input voltage VIN and the output voltage of the D / A converter are level-converted.

Therefore, if the comparator as shown in FIG. 3 is used, the comparator always operates stably and the error generated in the digital signal value can be reduced.

While the switch SW2 is off, D / A
It is possible to reduce power consumption by setting the converter 602 so that it does not operate.

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120]

[0121]

Since the comparator is supplied with the input voltage subjected to the similar conversion, the conversion error is reduced.

[Brief description of drawings]

FIG. 1 shows a circuit diagram of a first embodiment of the present invention.

FIG. 2 shows a circuit diagram of a comparator in the present invention.

FIG. 3 shows a circuit diagram of a comparator in the present invention.

FIG. 4 shows a circuit diagram of a second embodiment of the present invention.

FIG. 5 shows a circuit diagram of a third embodiment of the present invention.

FIG. 6 shows a circuit diagram of a fourth embodiment of the present invention.

[Explanation of symbols]

101, 401, 501, 601 ... Controller circuit 102, 402, 502, 602 ... D / A converter 103, 403, 503, 603 ... Sample and hold circuit 104, 105 ... Comparator 106. ··selector

Claims (5)

(57) [Claims] 1. A sample-hold circuit which receives an input voltage and holds the input voltage, a digital / analog converter which outputs a voltage based on a supplied digital signal, and an input which is held by the sample-hold circuit. A first comparator that compares the voltage with a reference voltage and outputs a select signal; and a level conversion circuit that outputs a voltage obtained by level-converting the input voltage held by the sample hold circuit using the reference voltage. A selector for selectively outputting the input voltage held in the sample-hold circuit or the output voltage of the level conversion circuit based on a select signal output from the first comparator; a power supply voltage and a ground voltage; the ratio and the logic circuit and a voltage outputted to the voltage applied from said selector from said digital / analog converter And, there is the power supply voltage as the comparison result
Or a second comparator that outputs a comparison result signal having a voltage based on the ground voltage; and a comparator that is supplied to the digital / analog converter in response to the comparison result signal supplied from the second comparator. A controller that outputs a digital signal, and configures the second comparator as the reference voltage.
Voltage exceeding the threshold voltage of the MOS transistor
The voltage selectively output by the selector is
Fixed voltage on the side that exceeds the reference voltage and the threshold voltage
Voltage in the range between the power supply voltage and the ground voltage.
The analog / digital conversion circuit is characterized in that it is logically inverted with respect to the digital signal according to the voltage level of the select signal. 2. The level conversion circuit, wherein the input voltage
From an operational amplifier that converts the voltage to a voltage higher than the input voltage
The logical inversion of all of the digital signals.
The operation according to claim 1, wherein the operation is performed for each bit.
Analog / digital conversion circuit. 3. The input voltage of the level conversion circuit
Is composed of a subtractor for converting the voltage into a voltage lower than the input voltage
And the logical inversion is the most significant bit of the digital signal.
An analog according to claim 1, characterized in that
Digital / digital conversion circuit. 4. A first hold circuit which receives an input voltage and holds the input voltage, a digital / analog converter which outputs an analog signal based on the supplied digital signal, and a first switch. Is electrically connected to the first hold circuit and makes the first switch conductive, thereby dividing the input voltage held by the first hold circuit to generate the first divided voltage. A second hold circuit that receives the analog signal through a first level conversion circuit that generates the second switch and a voltage that the analog signal has, and a second hold circuit that holds the voltage of the analog signal through the second switch. Is electrically connected to the second hold circuit and makes the third switch conductive to divide the voltage held by the second hold circuit to generate a second divided voltage. Les Compares the Le converter circuit, said first divided voltage and a second divided voltage,
A comparator that outputs a comparison result signal as a comparison result, according to the comparison result signal given from the comparator,
The digital / and a controller for outputting the digital signal supplied to the analog converter, have a, the first divided voltage and the second divided voltage is its
Each of the MOS transistors constituting the comparator is
An analog / digital conversion circuit characterized by a voltage exceeding a threshold voltage . 5. The first level conversion circuit includes the first level conversion circuit.
Has a first capacitor for holding the divided voltage
And the first capacitor held by the first capacitor
A fourth switch for releasing the divided voltage of
The level conversion circuit holds the second divided voltage.
Has a second capacitor for
The fifth that releases the second divided voltage held by Pashita
The analog according to claim 4, further comprising a switch.
Log / digital conversion circuit.