JP2000201076A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately control the current consumption of a comparator circuit and the current consumption of a reference voltage generating circuit corresponding to the converting speed of an A/D converter for allowing the A/D converter to operate accurately corresponding to the converting speed with the absolute minimum current consumption. SOLUTION: A current consumption controller 28A is provided with the current control circuits of the chopper comparators of a comparator circuit 21 for upper 4 bits and comparator circuits 22 and 23 for lower 4 bits and the current control circuit of a reference voltage generating circuit 24A. Thus, the chopper comparators and the reference voltage generating circuit 24A can be driven in either a normal operation state or a low current consumption operating state respectively according to the combination of control signals Vc1 and STB and the combination of control signals Vc2 and STB. Thus, the highly precise A/D converting operation can be accurately and efficiently attained in the operating state without any useless power consumption according to the converting speed by selecting the operation mode corresponding to the converting speed of the A/D converter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an AD converter for converting an analog signal into a digital signal and outputting the digital signal.

[0002]

2. Description of the Related Art Under a system-on-silicon flow due to miniaturization of semiconductor process units, high-speed AD
Converters tend to be built into LSIs (Large Scale Integrated Circuits). In this case, as a high-speed AD converter,
In many cases, the conversion frequency ranges from several MHz to several tens of MHz, and the conversion frequency differs depending on the purpose of use. Examples of such a high-speed AD converter include a flash AD converter that converts an input analog signal into an n-bit digital signal in parallel, and a two-step AD converter that converts an analog signal into two stages of upper bits and lower bits. A flash type AD converter and the like are known.

In a conventional AD converter, a reference signal output from a reference voltage generating circuit having a resistance ladder circuit and an analog input signal are input to a chopper comparator circuit, and a digital output signal is output from the chopper comparator circuit. You. In this case, the ratio W / L of the gate width W to the gate length L of the transistor constituting the CMOS inverter of the chopper comparator circuit is determined according to the conversion speed required for the chopper comparator circuit, and the chopper is determined by W / L. Since the current consumption of the comparator is also determined, a high-speed chopper comparator circuit capable of covering several MHz to several tens of MHz has been used at the expense of power consumption.

[0004] In order to solve this problem, the applicant of the present application has proposed an A / D converter as the basis of the present invention, which can obtain a required conversion speed without sacrificing power consumption. The AD converter according to this proposal is shown in FIG.
And a current consumption controller 28 for controlling the current consumption of the chopper comparator circuit of the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23. According to 28, the current consumption of the chopper comparator circuits of the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23 is appropriately selected according to the conversion speed. For this,
Upper 4-bit comparator circuit 2 according to conversion speed
By reducing the current consumption of the chopper comparator circuits of the 1 and lower 4 bit comparator circuits 22 and 23, an AD change operation without unnecessary current consumption is performed.

[0005]

The overall structure of the proposed AD converter is as shown in FIG. 9. The reference voltage generating circuit 24 is provided with a resistor ladder circuit. As shown in FIG. 11, in the case of an 8-bit AD converter, the resistance ladder circuit has 256 unit resistors R between input terminals RT and RB of a reference input voltage.
1 are connected in series with each other, and 16 unit resistors R
The short-circuit resistor R2 is connected in parallel for each series connection circuit. A necessary reference signal is extracted from the connection terminal of the resistor ladder circuit having such a configuration and supplied to the upper four-bit comparator circuit 21 and the chopper comparator circuits of the lower four-bit comparator circuits 22 and 23.

In this case, the short-circuit resistor R2 is originally required only when the high-order 4-bit comparator circuit 21 and the low-order 4-bit comparator circuits 22 and 23 operate at high speed. Value is small,
When an analog switch is provided and turned on and off, the linearity of the reference signal cannot be ensured, and therefore, it is actually always connected. In such a state, according to the AD converter shown in FIG. 9, as shown in FIG.
The clock CLK shown in (a) corresponds to the reference signal VIN shown in (b) and the output terminal 8 shown in (c) corresponds to the reference signal VIN shown in (b).
A bit-converted digital signal is output. As described above, in the proposed AD converter, useless current is constantly consumed in the reference voltage generation circuit 24.

[0007] The present invention relates to an AD according to the above proposal.
It was made in view of the current state of operation of the converter,
The purpose is to accurately control the current consumption of the reference voltage generation circuit as well as the current consumption of the comparator circuit in accordance with the conversion speed of the A / D converter. To provide an AD converter that operates in response to the above.

[0008]

According to a first aspect of the present invention, a reference signal output from a reference voltage generating circuit having a resistor ladder circuit and an analog input signal are converted into chopper comparators. An AD converter which is input to a circuit and converts and outputs a digital output signal from the chopper comparator circuit in accordance with an operation condition of the chopper comparator circuit; and a first current consumption control supplied to the chopper comparator circuit. A current consumption controller for outputting a signal and a second current consumption control signal supplied to the reference voltage generation circuit; and controlling the current consumption of the chopper comparator circuit based on the first current consumption control signal. First current control means, and the reference voltage generation circuit based on the second current consumption control signal. It is characterized in that a second current control means for controlling the current consumption.

Similarly, in order to achieve the above object, a second aspect of the present invention is characterized in that, in the first aspect of the present invention, the AD converter is a flash type AD converter.

[0010] Similarly, in order to achieve the above object, the invention according to claim 3 is characterized in that, in the invention according to claim 1, the AD converter is a two-step fish type AD converter. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a block diagram showing the overall configuration of the present embodiment, FIG. 2 is a circuit diagram showing the configuration of a chopper comparator of the comparator circuit of FIG. 1, and FIG. 3 is a configuration of a current consumption control circuit for the chopper comparator of the present embodiment. FIG. 4 is a characteristic diagram illustrating current control of the chopper comparator according to the present embodiment, FIG. 5 is an explanatory diagram illustrating a schematic configuration of a reference voltage generating circuit according to the present embodiment, and FIG. 6 is an operational amplifier illustrated in FIG. FIG. 7 is a circuit diagram showing a configuration of a current consumption control circuit for the reference voltage generation circuit of the present embodiment, and FIG. 8 is a characteristic showing current consumption control of the reference voltage generation circuit of the present embodiment. FIG.

In the present embodiment, as shown in FIG. 1, a reference voltage generating circuit 24A includes a comparator circuit 21 for upper 4 bits and a comparator circuit 22 for lower 4 bits.
23 is connected to the comparator circuit 21 for the upper 4 bits.
Are connected to a latch circuit 25 for upper 4 bits, and comparator circuits 22 and 23 for lower 4 bits are connected to a latch circuit 26 for lower 4 bits. Further, in the present embodiment, a current consumption controller 28A is provided, and the current consumption controller 28A is provided with the upper 4-bit comparator circuit 21, the lower 4-bit comparator circuit 22,
3 and the reference voltage generating circuit 24, and the clock signal generator 27
5, the lower 4-bit latch circuit 26, the upper 4-bit comparator circuit 21, the current consumption controller 28A, the lower 4-bit comparator circuits 22 and 23, and the reference voltage generation circuit 24A.

An analog input voltage Vin is input from the outside to the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23, and a reference voltage Vreft and a reference voltage Vrefb is applied and the reference voltage Vreft
Corresponds to the voltage of the most significant pit of the quantization level, and the reference voltage Vrefb corresponds to the voltage of the least significant bit of the quantization level.

In the reference voltage generating circuit 24A, as shown in FIG. 5, an input terminal RT to which a reference voltage Vreft is input is provided.
And 16 input terminals RB to which the reference voltage Vrefb is input, 16 resistors R3 are connected in series with each other, and 256 unit resistors R1 are connected between the input terminal RT and the input terminal RB.
Are connected in series with each other, and in this series connection circuit,
Between a connection point of a series connection circuit of 16 unit resistors R1 and a connection point of each of the 16 resistors R3 connected in series with each other, an operational amplifier C connected by a voltage follower connects a non-inverting input terminal to each resistor. Connect 16 output terminals to the connection point of R3.
The unit resistors R1 are inserted and provided so as to be connected to respective connection points of the series connection circuit. The operational amplifier C is
The operational amplifier C has a configuration as shown in FIG.
A current consumption control circuit having a configuration as shown in FIG.
8A.

Further, in this embodiment, the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23 are provided with a chopper comparator having a configuration as shown in FIG. A current control circuit having a configuration as shown in FIG. 3 for controlling current consumption is provided in the current consumption controller 28A.

The chopper converter according to the present embodiment
As shown in FIG. 2, the input terminal 1 of the analog input signal Vin is provided at the input terminal of the switch SW1, the input terminal of the reference signal Vref is provided at the input terminal of the switch SW2, and the output terminals of the switches SW1 and SW2 are provided at the capacitors. Through C1, p-MOS (p-channel MOS-FE)
T) Q1 and the source are connected to the input terminal of a CMOS inverter 3 consisting of an n-MOS (n-channel MOS-FET) Q2 grounded, and a switch SW3 is connected between the input terminal and the output terminal of the CMOS inverter 3. ing. Similarly, the output terminal of the CMOS inverter 3 is connected via a capacitor C2 to a CMOS inverter 4 comprising a p-MOS Q3 and an n-MOS Q4 whose source is grounded.
The switch SW4 is connected between the input terminal and the output terminal of the CMOS inverter 4.

The output terminal of the CMOS inverter 4 is a p-MOS Q5 and an n-MO
SQ6 is connected to the input terminal of the CMOS inverter 5, the output terminal of the CMOS inverter 5 is used as the output terminal 6 of the chopper comparator, and the output terminal 6 is n-M
The n-MOS Q18 is connected to the drain of the OSQ18, the source is grounded, and the control signal STB is input to the gate.

In this embodiment, p-MOS Q15, p-MOS Q15 are connected to the input terminal 9 to which the control signal Vc1 is input.
16, the gate of p-MOS Q17 is connected and p-MO
The sources of SQ15, Q16 and Q17 have the power supply voltage Vdd
Is applied, and the drains of the p-MOSs Q15, Q16, and Q17 are connected to the sources of the p-MOSs Q1, Q3, and Q5, respectively. In the present embodiment, p-M
The threshold voltages of OSQ15, Q16, and Q17 are set to Vth, and the control signal Vc1 is set to 0 (V) and Vdd- (V
(th + α) (V) and Vdd (V).

When the control signal Vc1 = 0, p-MO
SQ15, Q16 and Q17 are turned ON, and p-MO
The maximum current flows through the CMOS inverters 3, 4, and 5 through SQ15, Q16, and Q17. Control signal Vc1 = V
In the case of dd− (Vth + α), p-MOSQ15,
Although Q16 and Q17 are turned on, the p-MOS Q1
5, CMOS inverter 3 through Q16 and Q17,
The currents flowing through 4 and 5 decrease as compared with the case where the control signal Vc = 0. When the control signal Vc1 = Vdd, p−
MOS Q15, Q16, Q17 are turned off, and p
-No current flows through the CMOS inverters 3, 4, 5 through the MOSs Q15, Q16, Q17.

In this embodiment, the control signal STB
, Two-stage voltages of L level and H level are used. If the control signal STB is at H level, n-MOS
Q18 is turned on, the signal of the output terminal 6 is fixedly held at L level, and if the control signal STB is at L level,
The n-MOS Q18 is turned off, and C is output from the output terminal 6.
The output signal of MOS inverter 5 is output.

In this embodiment, the chopper comparator thus enters the normal operation mode when the control signal Vc1 = 0, and the control signal Vc1 = Vdd- (Vt
h + α), the mode is the low current consumption mode. In the normal operation mode and the low current consumption mode, the control signal STB is set to L level. When the control signal Vc1 = Vdd, the standby mode is set, and the control signal STB is set to the H level.

In the normal operation mode, when the clock signal CK goes high, the switches SW1, SW3, and SW4 are turned on, and the switch SW2 is turned off.
In this period, the analog input signal Vi from the input terminal 1
n is supplied to the capacitor C1 and is sampled.
Self-offset cancellation of the MOS inverters 3 and 4 is performed. The operating currents i1 to i3 at this time correspond to DC currents flowing through the CMOS inverters 3 to 5 when the input terminals and the output terminals of the CMOS inverters 3 to 5 have the same potential. In the normal operation mode, the operation currents i1 to i3 of the CMOS inverters 3 to 5 during the sampling period become maximum.

Next, when the clock signal CK goes low, the switches SW1, SW3, and SW4 are turned off, the switch SW2 is turned on, and the reference signal Vref from the input terminal 2 is supplied to the capacitor C1, and sampling is performed first. The comparison with the analog input signal Vin is performed. In this case, if Vin ≧ Vref, an H-level output signal Vout is output from the output terminal 6 and Vin
<If it is, the logical value of the signal at the output terminal 6 becomes L level.

The operation of the chopper comparator in the low current consumption operation mode is the same as the operation in the normal operation mode described above, except that in this case, the currents i1 to i3 flowing through the CMOS converters 3 to 5 through the p-MOSs Q15 to Q17.
Is reduced as compared with the case of the normal operation mode.

The current control circuit for supplying the control signal Vc1 to the chopper comparator shown in FIG. 2 includes NOR gates 31 and 32 as shown in FIG.
And the control signal STB are input to the input terminal of the NOR gate 32, the control signal STB is input to one input terminal of the NOR gate 31, and the control signal PS is input via the inverter 33 to the other input terminal of the NOR gate 31. Has been entered. The output terminal of the NOR gate 31 is a p-MOS Q41
The power supply voltage Vdd is applied to the source of the p-MOS Q41, and the drain is connected to the p-MOS Q4
5 and an output terminal 37 via a switch SW10 comprising an n-MOS Q46.

Further, a p-MOS Q42 is provided, the power supply voltage Vdd is applied to the source, and the gate is connected to the p-M transistor Q42.
The drain of the OSQ 41 is connected to the drain of the resistor 36.
, The source is connected to the drain of the grounded n-MOS Q44, the control signal STB is connected to the gate of the n-MOS Q44 via the inverter 34, and the drain of the p-MOS Q42 is connected to the output terminal 37. Is also connected.

The output terminal of the NOR gate 32 is connected to the n-MOS Q46 of the switch SW10 via the inverter 35, and the output terminal of the NOR gate 32 is connected to the gate of the n-MOS Q43 whose source is grounded. n-
The drain of the MOS Q43 is connected to the output terminal 37.

The current control circuit shown in FIG. 3 outputs a control signal Vc1 as shown in Table 1 according to the control signal STB and the control signal PS.

[0029]

[Table 1]

When the control signal STB is at the H level, the voltage of the control signal Vc1 becomes Vdd regardless of the control signal PS, and the chopper comparators of the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23 become The standby mode is set, the current consumption of the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23 becomes 0, and the supply of the clock signal from the clock signal generation circuit 27 is also stopped.

When the control signal STB is at L level and the control signal P
When S is at the H level, the voltage of the control signal Vc1 is Vdd-
(Vth + α), and the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23
Operates in a low current consumption operation mode, the current consumption of the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22 and 23 is saved, and the AD converter operates at a low speed.

When control signal STB is at L level and control signal P
When S is at the L level, the voltage of the control signal Vc1 becomes 0, and the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22, 23 operate in the normal operation mode, and the upper 4-bit comparator circuit operates. The current consumption of the circuit 21 and the lower 4-bit comparator circuits 22 and 23 is maximized, the AD converter operates at high speed, and the maximum performance is exhibited.

FIG. 4 shows the current consumption accompanying the operation of the chopper comparator. The current consumption changes as shown in FIG. 4B in response to the clock signal CK in FIG. 4A, and the solid line in FIG. In the operation mode, the chain line indicates the current consumption in the low current consumption operation mode, and the dashed line indicates the current consumption in the standby mode.

In the present embodiment, the current control circuit for controlling the current consumption of the reference voltage generation circuit 24A is, as shown in FIG. 7, an output terminal of the NOR gate 20 to which the control signal PS and the control signal STB are input. Is connected to the gate of the p-MOS Q22 via the inverter 23,
A resistor R22 is connected between the source and the drain of Q22, a drain of the p-MOS Q22 is connected via a resistor R21 to a drain of an n-MOS Q26 whose source is grounded, and a gate of the n-MOS Q26 is The signal STB is input via the inverter 21. Also, a p-MOS Q having a power supply voltage Vdd applied to its source
The drain of the p-MOS Q21 is connected to the output terminal 25 and the source of the p-MOS Q22.
The gate of the MOS Q21 is connected to the output terminal 25; Furthermore, a p-MOS with a power supply voltage applied to the source
The drain of Q25 is connected to output terminal 25 and p-MO
The gate of SQ25 is connected to the output terminal of inverter 21.

In the operational amplifier C of the present embodiment, as shown in FIG. 6, the control signal Vc2 is supplied to the gate of p-
The power supply voltage Vdd is applied to the source of the MOS Q31, and the drain of the p-MOS Q3 having a gate as an input terminal is applied to the drain.
P-MOSQ whose source and gate are output terminals
33 sources are connected. The drain of the p-MOS Q32 is connected to the drain of the n-MOS Q37 whose source is grounded and the output terminal via the capacitor 39, and the drain of the p-MOS Q33 is connected to the drain of the n-MOS Q38 whose source is grounded. And n−M
The gates of the OSQ 37 and the n-MOS Q38 are connected to each other.

The gate and the drain of the n-MOS Q38 are connected to the drain of the n-MOS Q39 whose source is grounded, and the control signal STB is input to the gate of the n-MOS Q39. Further, the p-MOS Q34 and the p-MOS Q3 to which the power supply voltage Vdd is applied to the sources are provided.
5 is provided, and a control signal STB is input to the gate of the p-MOS Q34 via the inverter 38.
The drains of the p-MOSs Q34 and Q35 are connected to each other, and the drains of the p-MOSs Q34 and Q35 are grounded.
0 is connected to the drain.

The drain and the gate of the p-MOS Q35 are connected to each other, the gate of the p-MOS Q35 is connected to the gate of the p-MOS Q36 whose power source voltage Vdd is applied to the source, and the source of the p-MOS Q36 is grounded. Connected to the drain of the n-MOS Q52
The gate of the n-MOS Q52 is connected to the grounded n-MOS Q52.
The control signal STB is input to the drain of the MOS-Q51 and the drain of the p-MOSQ32, and to the gate of the n-MOSQ51.

Operation modes corresponding to the control signals STB and PS of the current control circuit of FIG. 7 are as shown in Table 2. In Table 2, S1 indicates a switch circuit of the p-MOS Q22, S2 indicates a switch circuit of the p-MOS Q25, and S3 indicates a switch circuit of the n-MOS Q26.

[0039]

[Table 2]

First, the standby mode will be described. In the current control circuit shown in FIG.
When it is at the level, the control signal Vc2 goes to the H level, the control signal Vc2 at the H level is supplied to the gate of the p-MOS Q31 of the operational amplifier C in FIG. STB
Is inverted by the inverter 38 and applied to the gate of the p-MOS Q34, the p-MOS Q34 is turned on, and the gates of the p-MOS Q34 and
Level, the p-MOSs Q34 and Q35 are turned off, the DC current of the operational amplifier circuit is cut off, and the standby mode is set to a high impedance state.

Next, the Power Save mode will be described. In the current control circuit of FIG.
When TB is at L level and control signal PS is at H level,
The output terminal of the NOR gate 20 is at L level and the inverter 2
3, the gate of the p-MOS Q22 goes high, the p-MOS Q22 (S1) goes off, the gate of the p-MOS Q25 goes high by the inverter 21, and the p-MOS Q25 (S2) goes off. Becomes Further, the inverter 21 causes the n-MOS Q2
6 becomes H level, and the n-MOS Q26 (S
3) is turned ON, the p-MOS Q21 in which the control signal Vc2 is applied to the gate operates in the saturation region, and the n-MO
The ON resistance of SQ26 is the resistance R1 + R3 described in FIG.
Output terminal 2
The resistance between 5 and ground is approximated by R21 + R22.

The relationship between the current I flowing through the resistors R21 + R22 and the control signal Vc2 is, as shown in FIG.
Vc2 / (R21 + R22). On the other hand, p-M
The current flowing through the OSQ 21 is, as shown in FIG.
When Kp = K (Q21) is a proportional constant and Vth is a threshold voltage, I = Kp (Vdd−Vc2−Vth) (Vdd
−Vc2−Vth). Here, the resistance R21 + R2
2 and the current flowing through the p-MOS Q21 are equal, the current Ib2 flowing in this case is as shown in FIG. 8, and the control signal Vc2 at that time becomes V2.

By the way, if the p-MOS Q31 of FIG. 6 is designed to operate in the saturation region, the current flowing through the p-MOS Q31 will be I (31) = K, where K (Q31) is a proportional constant and Vth is a threshold voltage. (Q31) (Vdd-V2
−Vth) (Vdd−V2−Vth). Further, the current of the p-MOS Q21 of the current control circuit of FIG.
= K (Q21) (Vdd-V2-Vth) (Vdd-V
2-Vth), and from both equations, I (31) / K (Q3
1) = Ib2 / K (Q21) That is, p-MOS
The connection relationship between Q31 and p-MOS Q21 is p-MOS
With reference to the current Ib2 generated by Q21, I
(31) = {K (Q31) / K (Q21)} · Ib2 The current mirror circuit is converted into I (31) at a predetermined ratio by a relational expression.

The DC current of the operational amplifier C shown in FIG.
1) + I (34) + I (36), the connection relationship between the n-MOS Q50 and the n-MOS Q38 is based on the current I (31) / 2 generated by the n-MOS Q38.
(34) = K (Q50) / K (Q38) · I (31) /
According to the two relational expressions, the current mirror circuit is converted to I (34) at a predetermined ratio. At this time, p-MO
SQ32 and p-MOS Q33 and n-MOS Q37 and n
-MOSQ38 is a transistor of the same size,
The gate voltages of -MOS Q32 and p-MOS Q33 need to be equal.

The p-MOS Q35 and p-MOS Q3
6 is based on the current I (34) generated by the p-MOS Q35, and I (36) = K (Q36)
According to the relational expression of / K (Q35) · I (34), the current mirror circuit converts the current to I (36) at a predetermined ratio. Here, I (31) + I (34) + I (36)
= [1 + K (Q50) / {K (Q38) · 2} + K (Q
36) ・ K (Q50) / ｛K (Q35) ・ K (Q38)
2｝] · K (Q31) / K (Q21) · lb2, so that the DC current of the operational amplifier C is determined by Ib2.

Finally, the Normal mode will be described. As shown in Table 2, when the control signal STB to the current control circuit shown in FIG. 7 is at L level and the control signal PS is at L level, an L level signal is supplied to the gate of the p-MOS Q22 via the inverter 23. Is applied to the p-MOS Q22
(S1) is turned on, and n
The H-level signal is applied to the gate of the MOS Q26, the n-MOS Q26 (S3) is turned on, the H-level signal is applied to the gate of the p-MOS Q25 via the inverter 21, and the p-MOS Q25 (S2 ) Is O
The state becomes the FF state. In this case, the p-MOS Q22 and the n-M
Since the ON resistance of the OSQ 26 is set sufficiently smaller than the resistances R21 and R22, the resistance between the output terminal 25 and the ground is approximated to R21, and the relationship between the current I flowing through the resistance R21 and the control signal Vc2. Is I = Vc2 / R21 as shown in FIG. 8 (b).

The p-MOS Q21 operates in the saturation region,
The current flowing through the MOS Q21 is, as shown in FIG. 8A, I = Kp (Vdd-Vc2-Vth) (Vdd-V
c2−Vth), and the current I flowing through the resistor R21 and p
Since the currents flowing through the MOS Q21 are equal, the current becomes Ib2 in FIG. 8, and the control signal Vc2 becomes V1. When the p-MOS Q31 of the operational amplifier C in FIG. 6 is designed to operate in a saturated state, the current flowing through the p-MOS Q31 is I (31) = K (31) (Vdd-V1-Vth)
(Vdd-V1-Vth).

The current of the p-MOS Q21 in FIG.
Ib1 = K (21) (Vdd-V1-Vth) (Vdd
−V1−vTH), and I (31) /
K (31) = Ib1 / K (21). That is, p-M
The connection relationship between OSQ31 and p-MOSQ21 is p-MO
The current mirror circuit converts the current at a predetermined ratio represented by I (31) = {K (31) / K (21)} · Ib1 based on the current Ib1 generated by SQ21. Here, I (31) + I (34) + I (36) =
[1 + K (Q50) / {K (Q38) · 2} + K (Q3
6) ・ K (Q50) / ｛K (Q35) ・ K (Q38) ・
2｝] · K (Q31) / K (Q21) · lb1, so that the DC current of the operational amplifier C is determined by Ib1. As shown in FIG. 8, the bias current Ib1 in the normal state is set to be larger than the bias current Ib2 in the power save mode.
In the rmal mode, the DC current of the operational amplifier C increases.

As described above, according to the present embodiment, the current consumption controller 28A is provided with the upper 4-bit comparator circuit 21 and the lower 4-bit comparator circuits 22, 2
3 is provided with a current control circuit of the chopper comparator and a current control circuit of the reference voltage generation circuit 24A. Is driven in one of the normal operation mode and the low current consumption operation mode. Therefore, the operation mode is selected according to the conversion speed of the AD converter, and the operation state without wasteful power consumption is selected according to the conversion speed. Thus, a highly accurate AD conversion operation can be performed accurately and efficiently.

[0050]

According to the present invention, the reference signal output from the reference voltage generating circuit having the resistance ladder circuit and the analog input signal are input to the chopper comparator circuit, and the operation of the chopper comparator circuit is performed from the chopper comparator circuit. A digital output signal is converted and output according to the conditions. A first current consumption control signal supplied from the current consumption controller to the chopper comparator circuit and a second current consumption supplied to the reference voltage generation circuit are output. And the control signal is output. The first current control means controls the current consumption of the chopper comparator circuit based on the first current consumption control signal. The first current control means controls the current consumption of the reference voltage generation circuit based on the second current consumption control signal. Since the current consumption is controlled, the chopper Current consumption and over-capacitor circuit and the reference voltage generating circuit is set controlled in an efficient operating state without wasteful current consumption, high precision at the required conversion speed AD
The conversion operation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a chopper comparator of the comparator circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration of a current consumption control circuit that controls current consumption of the chopper comparator according to the embodiment.

FIG. 4 is a characteristic diagram showing current control of the chopper comparator of the embodiment.

FIG. 5 is an explanatory diagram illustrating a schematic configuration of a reference voltage generation circuit according to the embodiment;

FIG. 6 is a circuit diagram showing a configuration of the operational amplifier of FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a current consumption control circuit that controls current consumption of the reference voltage generation circuit of the embodiment.

FIG. 8 is a characteristic diagram showing current consumption control of the reference voltage generation circuit of the embodiment.

FIG. 9 is a block diagram showing the overall configuration of a conventional AD converter.

FIG. 10 is a block diagram showing a circuit configuration of a conventional AD converter.

FIG. 11 is an explanatory diagram showing a configuration of a conventional resistance ladder circuit of an AD converter.

FIG. 12 is a characteristic diagram showing an operation of a conventional AD converter.

[Explanation of symbols]

21: Upper 4-bit comparator circuit, 22, 23 ...
Lower 4-bit comparator circuit, 24A: reference voltage generating circuit, 25: upper 4-bit latch circuit, 26: lower 4-bit latch circuit.

Claims (3)

[Claims] A reference signal output from a reference voltage generation circuit having a resistance ladder circuit and an analog input signal are input to a chopper comparator circuit, and the chopper comparator circuit responds to operating conditions of the chopper comparator circuit. A first current consumption control signal supplied to the chopper comparator circuit; and a second current consumption control signal supplied to the reference voltage generation circuit. A current consumption controller that outputs a current consumption control signal based on the first current consumption control signal; a first current control unit that controls current consumption of the chopper comparator circuit based on the first current consumption control signal; Second current control means for controlling current consumption of the reference voltage generation circuit. A / D converter. 2. The AD converter according to claim 1, wherein the AD converter is a flash AD converter. 3. The AD converter according to claim 2, wherein the AD converter is a two-step fish type AD converter.