JP2007243656A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the generation of an offset voltage caused by to the field-through of a calibration switch, and to suppress fluctuation in a differential non-linear error in an A-D converter which uses a plurality of inverter chopper type voltage comparators. <P>SOLUTION: The capacities plurality of voltage comparators have input switches SW1 and SW2, inverters 5, coupling capacities C, and calibration switches SWC, respectively. The input switch successively switch an input analog signal 4 and a reference voltage from a reference resistor string 1 given to the coupling capacity, while the calibration switch is in an on-state when the input analog signal is given to the coupling capacity and is in an off-state when the reference voltage is given. Voltages of an input terminal and an output terminal of the inverter when the calibration switch is in the on-state are not included in a range of the analog input signal voltage and a range of the referential voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an A / D converter (analog / digital converter), and more particularly to a high-speed A / D converter using an inverter chopper voltage comparator.

  A voltage comparator capable of operating at a high speed is used in a high-speed A / D converter. As this type of comparator, there is an inverter chopper voltage comparator composed of a CMOS transistor, which is frequently used for a monolithic A / D converter realized by a VLSI LSI of a CMOS transistor.

  FIG. 9 shows a configuration example of an inverter chopper voltage comparator composed of CMOS transistors. In FIG. 9, 10 is a basic configuration of an inverter chopper voltage comparator. Here, the analog input signal 4 is applied to one terminal of the first switch SW1, and the other terminal is connected to the coupling capacitor C. One terminal of the second switch SW2 is connected to the reference resistor string 1 that divides the reference voltages 2 and 3 to generate a reference voltage, and the other terminal is connected to the first switch SW1 of the coupling capacitor C. Connected to the terminal. The terminal of the coupling capacitor C, to which the first and second switches SW1, SW2 are not connected, is connected to the input of the inverter 5. One terminal of the calibration switch SWC is connected to the input terminal of the inverter 5, and the other terminal is connected to the output terminal of the inverter. The inverter 5 and the calibration switch SWC form an inverting amplifier.

Next, the operation will be described. FIG. 10 shows timing charts and states of the three switches SW1, SW2, and SWC. In the sample hold period, SW1 and SWC are turned on, that is, in a conductive state. At this time, the analog input signal 4 is applied to the coupling capacitor C, and one terminal of the coupling capacitor C becomes the analog voltage Vin. The other terminal of the coupling capacitor C becomes the voltage value of the input terminal of the inverter 5, but when the input / output characteristic of the inverter 5 is the characteristic shown in FIG. 11, the calibration switch SWC is ON, so that the inverter 5 The voltage value of the input terminal and the output terminal is a voltage value Va (hereinafter referred to as a calibration voltage) at an intersection A between the input / output characteristics of the inverter and a straight line where the input voltage and the output voltage are equal. As a result, the voltage difference (Vin−Va) between the analog voltage value Vin and the calibration voltage Va is held in the coupling capacitor C. The charge Q held in the coupling capacitor C is obtained by using the relation Q = CV between the accumulated charge of the parallel plate capacitor and the terminal voltage difference.
Q = C (Vin-Va) (1)
It becomes.

In the next comparison period, when the first switch SW1 and the calibration switch SWC are turned OFF and the second switch SW2 is turned ON, the potential difference between the voltage Vb of the input terminal of the inverter 5 and the reference voltage Vref of the reference resistor string 1 ( Vref−Vb) is applied between both terminals of the coupling capacitor C. Since the input terminal of the inverter 5 is the gate of a MOS transistor, the input impedance is very high and the inflow of current can be ignored. Since the charge at the input terminal of the inverter 5 is held from the sample hold period,
Q = C (Vref−Vb) (2)
Holds. From the formulas (1) and (2), Vb = Vref−Vin + Va (3)
become that way. Therefore, the input terminal of the inverter 5 varies from the calibration voltage Va by (Vref−Vin) as shown in FIG. When the voltage gain of the inverter 5 is G (G> 1), the change amount ΔVo of the output voltage of the inverter 5 is ΔVo = −G (Vref−Vin) (4)
It becomes.

  Based on the principle described above, the inverter chopper voltage comparator 10 compares the analog input signal with the reference voltage.

Next, an A / D converter using the above-described inverter chopper voltage comparator will be described. FIG. 13 shows a configuration example of a 2-bit parallel A / D converter. In FIG. 13, the reference voltages V1, V2, and V3 are divided and generated by the resistor string 1 connected between the first reference voltage 2 and the second reference voltage 3. The generated reference voltages V1, V2, and V3 are applied to one input terminal of each of the three voltage comparators 10 ₁ , 10 ₂ , and 10 ₃ . An analog input signal 4 is applied to the other input terminals of the voltage comparators 10 ₁ , 10 ₂ , 10 ₃ . Further, the outputs of the voltage comparators 10 ₁ , 10 ₂ , 10 ₃ are input to a logic circuit (encoder) 6, and the output from the logic circuit 6 becomes an A / D converter output 7.

Next, the operation will be described. The comparators 10 ₁ , 10 ₂ , and 10 ₃ output “1” when the voltage value Vin of the input analog signal is smaller than the reference voltage, and “0” when the voltage value Vin is larger. FIG. 14 shows a truth table of the comparators 10 ₁ , 10 ₂ , 10 ₃ and the logic circuit 6 for the input analog signal. The sampled voltage value Vin of the analog input signal 4 is compared with the reference voltages V1, V2 and V2 by the respective voltage comparators 10 ₁ , 10 ₂ and 10 ₃ . As an example, it is assumed that the voltage value Vin of the analog input signal 4 is larger than V2 and smaller than V3. In the voltage comparator ₁₀₃ at this time V3 is input as a reference voltage, towards the analog input signal than the reference voltage V ₃ determined to a small outputs "1" level. On the other hand, the voltage comparators 10 ₂ and 10 ₁ to which V2 and V1 are input as reference voltages determine that the analog input signal is larger than the reference voltage, and output “0” level. Accordingly, “100” is output from the voltage comparator arrays 10 ₃ , 10 ₂ , and 10 ₁ . When this output value is input to the logic circuit 6 and converted, an A / D conversion output of “10” is obtained.

  An A / D converter using an inverter chopper voltage comparator is described in Patent Document 1, for example. This Patent Document 1 discloses a configuration example of an A / D converter that particularly improves noise resistance.

Japanese Patent No. 3106657

  The switch in the inverter chopper voltage comparator 10 shown in FIG. 9 is composed of any one of an NMOS switch, a PMOS switch, a CMOS switch, and the like. These switches realize conduction and non-conduction of the transistor by applying a clock signal to the gate of the transistor. When the clock signal, which is a signal for controlling conduction and non-conduction, transitions from ON to OFF, charge is injected into the drain or source through the gate-drain or gate-source capacitance of the MOS transistor. This is called feedthrough. By this feedthrough, the inverter chopper voltage comparator 10 generates an error in the sample hold voltage in principle. The amount of charge injected due to this feedthrough depends on the voltage value of the drain or source of the MOS transistor and the device parameters of the transistor. Further, in such an A / D converter having a plurality of inverter chopper voltage comparators, the next constant of charge / discharge to the coupling capacitance is caused by the mutual conductance variation of the transistor due to the variation of the device parameter of the inverter in each voltage comparator. As a result, an error occurs in the voltage held in the coupling capacitor.

  In FIG. 9, when the calibration switch SWC is turned off, the charge Qc due to feedthrough is injected into the capacitor C. This charge Qc is determined by the magnitude and the sign is determined by the device parameters, and there is no difference between the voltage comparators.

When the input terminal voltage Va of the inverter is larger than the input voltage Vin,
(Va-Vin) + Qc = Vref-Vb (5)
Vb = Vref−Vin + Va + Qc / C (6)
Conversely, when the input voltage Vin of the inverter is larger than the input terminal voltage Va,
(Vin−Va) + Qc = Vb−Vref (7)
Vb = Vref−Vin + Va−Qc / C (8)
From the above, depending on the magnitude relationship between Vin and Va, there is a positive / negative difference in the offset voltage applied to the input terminal voltage Vb of the inverter. That is, the offset of the voltage comparator whose reference voltage is smaller than Va and the offset of the voltage comparator whose reference voltage is larger than Va have the same magnitude and opposite polarities (see FIG. 15). Therefore, it can be seen that the offset voltage generated by the feedthrough is discontinuous near Va. This is shown in the input / output characteristics of the A / D converter of FIG. FIG. 16 shows the input / output characteristics of the 3-bit parallel A / D converter. In FIG. 16, the dotted line shows the ideal input / output characteristics of the A / D converter, and the solid line shows the nonlinear error due to feedthrough. The input / output characteristics of the generated A / D converter are shown. In an A / D converter in which a nonlinear error has occurred due to feedthrough, the input / output characteristics become discontinuous with Va as a boundary. Since the absolute value of the offset voltage due to feedthrough does not change between the voltage comparators, it is offset in a voltage comparator group to which a reference voltage smaller than Va is inputted (or a voltage comparator group to which a reference voltage larger than Va is inputted). The voltage is constant and there is no effect on the differential nonlinearity error. Therefore, the differential nonlinearity error increases only when crossing Va.

  As described above, in an A / D converter using a plurality of inverter chopper type voltage comparator arrays, when Va exists in the dynamic range of the input analog signal, a different offset voltage is added to the voltage comparator across Va, and the principle is obtained. It can be seen that the differential nonlinearity error deteriorates.

  An object of the present invention is to suppress the variation of differential nonlinearity errors in an A / D converter using a plurality of inverter chopper type voltage comparators by suppressing the occurrence of an offset voltage due to field through of a calibration switch. An object is to provide an accurate A / D converter.

  In the present invention, in the A / D converter using a plurality of inverter chopper type voltage comparators, the calibration voltage Va and the input analog are intentionally controlled in order to suppress the offset voltage generated in principle in the voltage comparator. Try to shift the dynamic range of the signal voltage.

  According to another aspect of the present invention, the voltage comparator includes a reference voltage generation unit that generates a plurality of reference voltages, and a plurality of voltage comparators that compare each of the plurality of reference voltages with a voltage of an input analog signal. Each of which has an input switch, an inverter, a coupling capacitor connected between the input switch and the inverter, and a calibration switch connected between an input terminal and an output terminal of the inverter, An input switch sequentially switches the input analog signal and the reference voltage to be applied to the coupling capacitor, the calibration switch is turned on during a period in which the input analog signal is applied to the coupling capacitor, and the reference voltage is In an A / D converter composed of an inverter chopper voltage comparator that is turned off during the period given to the coupling capacitance, The inverter is composed of an N-channel transistor and a P-channel transistor, and when the calibration switch is on, the voltage at the input terminal and the output terminal of the inverter is generated from the range of the analog input signal voltage and the reference voltage generating means. The present invention proposes an A / D converter that is not included in the reference voltage range.

  2. The A / D converter according to claim 1, wherein when the calibration switch is in an ON state, the voltage of the input terminal and the output terminal of the inverter is the range of the analog input signal voltage and the reference voltage generation. As means for preventing the voltage from being included in the range of the reference voltage generated by the means, an inverter in which the channel width of the N channel transistor is larger than the channel width of the PMOS transistor in the N channel transistor and the P channel transistor constituting the inverter is provided. An A / D converter characterized by having at least one is proposed.

  3. The A / D converter according to claim 1, wherein when the calibration switch is in an ON state, the voltage of the input terminal and the output terminal of the inverter is the range of the analog input signal voltage and the reference voltage generation. A DC voltage is applied to the substrate terminal of each of the N-channel transistor and the P-channel transistor constituting the inverter as means for preventing the voltage from being included in the range of the reference voltage generated by the means. A D converter is proposed.

  According to a fourth aspect of the present invention, in the A / D converter according to the third aspect, as means for applying a DC voltage to a substrate terminal of each of the N-channel transistor and the P-channel transistor constituting the inverter in the plurality of voltage comparators. Each of the N-channel transistor and the P-channel transistor constituting the inverter so that the voltage of the input terminal and the output terminal of the inverter is always equal among the plurality of voltage comparators when the calibration switch is on. An A / D converter is proposed in which a DC voltage is applied to each substrate terminal.

  According to a fifth aspect of the present invention, in the A / D converter according to the third aspect, as means for applying a DC voltage to a substrate terminal of each of the N-channel transistor and the P-channel transistor constituting the inverter in the plurality of voltage comparators. The inverter is configured such that a difference between a voltage of the input terminal and the output terminal of the inverter when the calibration switch is in a closed state and a reference voltage input to the voltage comparator is constant among a plurality of voltage comparators. The A / D converter is characterized in that a DC voltage is applied to the substrate terminal of each of the N-channel transistor and the P-channel transistor that constitute the transistor.

  According to the present invention, in an A / D converter using an inverter chopper voltage comparator composed of a CMOS transistor or the like, an offset voltage due to a field-through of a calibration switch interposed between an input terminal and an output terminal of the inverter. It is possible to realize a high-precision high-speed A / D converter that avoids occurrence and suppresses variation in differential nonlinearity errors.

Specific examples of the A / D converter according to the present invention will be described in detail below.
[Example 1]
FIG. 1 is a block diagram of a 3-bit A / D converter according to a first embodiment of the present invention. In FIG. 1, first and second reference voltages 2 and 3 are applied to both ends of a reference resistor string 1. In the reference resistor string 1, reference voltages V1 to V7 are extracted from seven terminals, and the voltage difference between the terminals is equal. Outputs of voltage comparators 10 ₁ to 10 _{7 including seven} inverter chopper voltage comparators are input to a logic circuit (encoder) 6. The output of the logic circuit 6 becomes an A / D conversion output 7. The overall operation of this A / D converter is basically the same as that of FIG. FIG. 2 shows a truth table of the voltage comparators 10 ₁ to 10 ₇ and the logic circuit 6 for the input analog signal.

  In FIG. 1, the configuration of each voltage comparator is as follows. An analog input signal is applied to one of the first switches SW1, and the other terminal is connected to the coupling capacitor C. One terminal of the second switch SW2 is connected to the reference resistor string 1, and the other terminal is connected to a terminal to which the first SW1 of the coupling capacitor C is connected. A terminal of the terminal of the coupling capacitor C to which the first and second switches are not connected is connected to the input terminal of the inverter 5. One terminal of the calibration switch SWC is connected to the input terminal of the inverter 5, and the other terminal is connected to the output terminal of the inverter 5.

  The configuration and electrical characteristics of the inverter of this example are shown in FIG. FIG. 3A shows a configuration example of a CMOS inverter composed of a P-channel MOSFET (PMOS) and an N-channel MOSFET (NMOS). The CMOS inverter connects the PMOS source, the substrate 3 to the power supply voltage Vdd, the NMOS source, and the substrate to Vss. The gate terminals of both MOSFETs (NMOS) are the input and the drain terminal is the output. The PMOS channel width is about three times the NMOS channel width so that the threshold voltage (input voltage at which the output is inverted) of a general CMOS inverter is Vdd * 0.5. This is because the mobility of holes, which are PMOS carriers, is smaller than the mobility of electrons, which are NMOS carriers.

  The electrical characteristic (A) in FIG. 3B is the input / output characteristic of a general CMOS inverter. The input / output characteristics of the CMOS inverter used in this example are shown in (b) of the electrical characteristics in FIG. In order to obtain the input / output characteristics shown in (b), in this embodiment, the channel width of the NMOS is increased to about 2 to 3 times the channel width of the PMOS. As a result, the voltage Va when the calibration switch SWC is closed can be controlled to a desired voltage. Furthermore, by setting the dynamic range of the input analog signal as shown in FIG. 4 in this state, it is possible to avoid the calibration voltage Va being included in the dynamic range of the input analog signal. Since the calibration voltage Va is not included in the dynamic range, the offset due to the injection of the feedthrough charge by the calibration switch SWC does not differ between the voltage comparators, and has a constant and equal sign. As a result, the A / D converter of FIG. 1 using this voltage comparator can suppress variation in differential nonlinearity.

  FIG. 17 shows the simulation result of the differential nonlinearity error of the first example. The vertical axis represents the differential nonlinearity error, and the horizontal axis represents the value obtained by normalizing the input voltage with the center voltage of the dynamic range. In the figure, 1 is the case where the calibration voltage Va is included in the dynamic range of the input analog signal, 2 is the case where the calibration voltage is lowered below the lower limit of the dynamic range of the input analog signal using the first embodiment. It is. It can be confirmed that the differential nonlinearity error is suppressed by using this embodiment.

[Example 2]
FIG. 5 is a block diagram of a 3-bit A / D converter according to the second embodiment. In FIG. 5, first and second reference voltages 2 and 3 are applied to both ends of the reference resistor string 1. In the reference resistor string, reference voltages V1 to V7 are taken from seven terminals, and the voltage difference between the terminals is equal. Outputs of voltage comparators 10 ₁ to 10 _{7 including seven} inverter chopper voltage comparators are input to a logic circuit (encoder) 6. The output of the logic circuit 6 becomes an A / D conversion output 7. The overall operation of this A / D converter is basically the same as in FIG. 12, and the truth tables of the voltage comparators 10 ₁ to 10 ₇ and the logic circuit 6 for the input analog signal 4 are shown in FIG. Two.

In FIG. 5, the configuration of each of the voltage comparators 10 ₁ to 10 ₇ is as follows. The analog input signal 4 is applied to one of the first switches SW1, and the other terminal is connected to the coupling capacitor C. One terminal of the second switch SW2 is connected to the reference resistor string 1, and the other terminal is connected to a terminal to which the first SW1 of the coupling capacitor C is connected. A terminal of the coupling capacitor C to which the first and second switches are not connected is connected to the input terminal of the inverter. One terminal of the calibration switch SWC is connected to the input terminal of the inverter 5, and the other terminal is connected to the output terminal of the inverter 5. In this embodiment, a DC voltage 8 for substrate terminal voltage control for controlling the calibration voltage Va of the inverter is input to the inverter 5.

  The configuration and electrical characteristics of the inverter 5 of this embodiment are shown in FIG. FIG. 6A shows a configuration example of a CMOS inverter composed of a P-channel MOSFET (PMOS) and an N-channel MOSFET (NMOS). In the CMOS inverter, a PMOS source, a substrate are connected to a power supply voltage Vdd, an NMOS source is connected to Vss, and a substrate terminal voltage control DC voltage 8 of Vsub is applied to the substrate. The gate terminals of both MOSFETs (NMOS) are input and the drain terminal is output. The NMOS threshold voltage can be controlled by applying a DC voltage to the substrate. By utilizing this so-called substrate bias effect, a difference is generated in the current driving force between NMOS and PMOS, and a CMOS inverter having electrical characteristics as shown in (b) of FIG.

  The electrical characteristics (A) in FIG. 6B are the input / output characteristics of a general CMOS inverter. The input / output characteristics of the CMOS inverter used in this embodiment are (b) of the electrical characteristics shown in FIG. As a result, the calibration voltage Va when the calibration switch SWC is closed can be controlled to a desired voltage. Further, in this state, the dynamic range of the input analog signal is set as shown in FIG. 4 as in the first embodiment, so that the calibration voltage Va can be avoided from being included in the dynamic range of the input analog signal. Since the calibration voltage Va is not included in the dynamic range, the offset due to the injection of the feedthrough charge of the calibration switch SWC does not differ between the voltage comparators, and has a constant and equal sign. Therefore, the A / D converter of FIG. 5 using this voltage comparator can suppress variation in differential nonlinearity.

[Example 3]
FIG. 7 is a block diagram of a 3-bit A / D converter according to the third embodiment. In FIG. 7, first and second reference voltages 2 and 3 are applied to both ends of the reference resistor string 1. In the reference resistor string 1, reference voltages V1 to V7 are extracted from seven terminals, and the voltage difference between the terminals is equal. Outputs of voltage comparators 10 ₁ to 10 _{7 including seven} inverter chopper voltage comparators are input to a logic circuit (encoder) 6. This logic circuit 6 outputs an A / D conversion output 7. The overall operation of this A / D converter is basically the same as in FIG. 12, and the truth tables of the voltage comparators 10 ₁ to 10 ₇ and the logic circuit 6 for the input analog signal 4 are shown in FIG. Two.

In FIG. 7, the configuration of each of the voltage comparators 10 ₁ to 10 ₇ is as follows. The analog input signal 4 is applied to one of the first switches SW1, and the other terminal is connected to the coupling capacitor C. One terminal of the second switch SW2 is connected to the reference resistor string 1, and the other terminal is connected to a terminal to which the first SW1 of the coupling capacitor C is connected. The terminal of the coupling capacitor that is not connected to the first and second switches SW 1 and SW 2 is connected to the input terminal of the inverter 5. One terminal of the calibration switch SWC is connected to the input terminal of the inverter 5, and the other terminal is connected to the output terminal of the inverter 5. In this embodiment, a voltage control unit 9 is provided for controlling the substrate terminal voltage. The voltage control unit 9 inputs the output of each of the voltage comparators 10 ₁ to 10 _{7 and} the output of the logic circuit 6 so that the inverter in each voltage comparator has a desired electrical characteristic. A DC voltage 8 for substrate terminal voltage control of PMOS and NMOS of each inverter is dynamically output.

  The configuration and electrical characteristics of the inverter 5 of this embodiment are shown in FIG. FIG. 8A shows a configuration example of a CMOS inverter composed of a P-channel MOSFET (PMOS) and an N-channel MOSFET (NMOS). In the CMOS inverter, the source of PMOS is connected to the power supply voltage Vdd, and the source of NCOS is connected to Vss. The gate terminals of both MOSFETs (NMOS) are input and the drain terminal is output. Substrate terminals for controlling the substrate terminal voltage 8 input from the substrate terminal voltage control unit 9 are input to the substrate terminals of the PMOS and NMOS. As a result, a CMOS inverter having the same electrical characteristics as in the second embodiment is realized.

  The electrical characteristics (A) in FIG. 8B are the input / output characteristics of a general CMOS inverter. The input / output characteristics of the CMOS inverter used in this embodiment are (b) of the electrical characteristics shown in FIG. As a result, the calibration voltage Va when the calibration switch SWC is closed can be controlled to a desired voltage. Further, in this state, the dynamic range of the input analog signal is set as shown in FIG. 4 as in the first embodiment, so that the calibration voltage Va can be avoided from being included in the dynamic range of the input analog signal. Since the calibration voltage Va is not included in the dynamic range, the offset due to the injection of the feedthrough charge by the calibration switch SWC does not differ between the voltage comparators, and has a constant and equal sign. Therefore, the A / D converter using this voltage comparator can suppress the variation of the differential nonlinearity error.

It is a 3-bit A / D converter according to the first embodiment of the present invention. 2 is an operation truth table of FIG. It is the structure of the inverter in FIG. 1, and its electrical property. Indicates the input / output characteristics of the inverter and the dynamic range of the input analog signal. 3 is a 3-bit A / D converter according to a second embodiment of the present invention. 6 shows the configuration of the inverter in FIG. 5 and its electrical characteristics. It is a 3 bit A / D converter concerning the 3rd example of the present invention. 8 shows the configuration of the inverter in FIG. 7 and its electrical characteristics. This is a general inverter chopper voltage comparator. FIG. 10 is a timing chart of the switch of FIG. 9 and its state. It is the input / output characteristic of the inverter in FIG. It is the input / output characteristic of the inverter which shows the voltage gain of the inverter in FIG. This is a general 2-bit parallel A / D converter. 14 is an operation truth table of FIG. This is the offset voltage due to the feedthrough of the voltage comparator. It is an input / output characteristic of a conventional A / D converter. It is a simulation result of differential nonlinearity error of the 1st example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference resistance row | line | column 2 1st reference voltage 3 2nd reference voltage 4 Analog input signal 5 Inverter 6 Logic circuit 7 A / D converter output 8 DC voltage for board terminal control 9 Board terminal voltage control part

Claims (5)

Reference voltage generating means for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each of the plurality of reference voltages with the voltage of an input analog signal, each of the plurality of voltage comparators being an input A switch, an inverter, a coupling capacitor connected between the input switch and the inverter, and a calibration switch connected between an input terminal and an output terminal of the inverter, An input analog signal and the reference voltage are sequentially switched to be applied to the coupling capacitor, the calibration switch is turned on during a period in which the input analog signal is applied to the coupling capacitor, and the reference voltage is applied to the coupling capacitor. In an A / D converter composed of an inverter chopper voltage comparator that is turned off in a period,
The inverter is composed of an N-channel transistor and a P-channel transistor, and when the calibration switch is on, the voltage at the input terminal and the output terminal of the inverter is generated from the range of the analog input signal voltage and the reference voltage generating means The A / D converter is not included in the range of the reference voltage to be used.   2. The A / D converter according to claim 1, wherein voltages of the input terminal and the output terminal of the inverter when the calibration switch is on are generated from the range of the analog input signal voltage and the reference voltage generating means. As means for preventing the voltage from being included in the range of the reference voltage, the N-channel transistor and the P-channel transistor constituting the inverter have at least one inverter in which the channel width of the N-channel transistor is larger than that of the P-channel transistor. An A / D converter characterized by the above.   2. The A / D converter according to claim 1, wherein voltages of the input terminal and the output terminal of the inverter when the calibration switch is on are generated from the range of the analog input signal voltage and the reference voltage generating means. An A / D converter characterized in that, as means for preventing it from being included in a reference voltage range, a DC voltage is applied to a substrate terminal of each of an N-channel transistor and a P-channel transistor constituting the inverter.   4. The A / D converter according to claim 3, wherein the inverter is configured such that voltages at the input terminal and the output terminal of the inverter are always equal among a plurality of voltage comparators when the calibration switch is in an ON state. An A / D converter, wherein a DC voltage is applied to the substrate terminal of each of an N-channel transistor and a P-channel transistor.   4. The A / D converter according to claim 3, wherein a difference between a voltage at the input terminal and the output terminal of the inverter when the calibration switch is in an on state and a reference voltage input to the voltage comparator is a plurality of voltages. An A / D converter, wherein a DC voltage is applied to a substrate terminal of each of an N-channel transistor and a P-channel transistor constituting the inverter so as to be constant between comparators.

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