JP2005268895A - Switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching circuit for suppressing a leakage current even if a field effect transistor having a low threshold voltage is used to reduce on-resistance. <P>SOLUTION: Two identical conductivity-type field effect transistors 101, 102 in which a control signal 100 is input to each gate are connected in series between one terminal T1 and the other T2 of the switching circuit, a switch element 105 controlled by the control signal 100 is connected between the source of the transistor 101 and the drain of the transistor 102 and a constant potential point, and the potential of the source of the transistor 101 and the drain of the transistor 102 is fixed to a fixed potential point when the switching circuit is off. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switch circuit using a field effect transistor.

A switch circuit using a field effect transistor is frequently used in, for example, a pipeline type ADC (analog-digital converter), a ΔΣ (delta sigma) ADC, a switched capacitor filter, and the like. For example, Non-Patent Document 1 describes a pipeline type ADC using a CMOS switch circuit as shown in FIG. In addition to CMOS switch circuits, switch circuits using field effect transistors include NMOS switch circuits using only NMOS transistors (hereinafter referred to as NMOS transistors) and PMOS using only P-channel MOS transistors (hereinafter referred to as PMOS transistors). There is also a switch circuit.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999, “A 1.5-V, 10-bit, 14.3-MS / s CMOS Pipeline Analog-to-Digital Converter”, Andrew M .. Abo and Paul R. Gray, Fellow, IEEE

  For the purpose of increasing the speed of a semiconductor integrated circuit and reducing the circuit area, the miniaturization of a semiconductor process has been promoted. For example, according to the International Technology Roadmaps for Semiconductors (ITRS) 2002 Update, what was a 130nm process in 2001 was a 90nm process in 2004, and a 65nm process in 2007. Expected to stand up.

  In general, as the process becomes finer, the dielectric breakdown voltage of the field effect transistor becomes lower. Therefore, in order to maintain the reliability of the integrated circuit, it is necessary to lower the power supply voltage used in the circuit. When the power supply voltage is lowered, if a field effect transistor having a normal threshold voltage is used in the switch circuit, the resistance between the source and drain (ON resistance) of the field effect transistor when the switch is turned on is not sufficiently reduced. There arises a problem that the switch cannot be turned on.

  For example, a CMOS switch circuit can be turned ON / OFF by changing the gate-source voltage Vgs of each of an NMOS transistor and a PMOS transistor and increasing / decreasing the value of the switch resistance. The switch resistance of the CMOS switch circuit is a parallel resistance of the source-drain resistance of each of the NMOS transistor and the PMOS transistor. When the switch is to be turned on, a high voltage is applied to the NMOS transistor and a low voltage is applied to the gate of the PMOS transistor in order to sufficiently reduce the ON resistance to a desired value. Conversely, to turn off the switch, a low voltage is applied to the gate of the NMOS transistor and a high voltage is applied to the gate of the PMOS transistor to sufficiently increase the OFF resistance to a desired value.

  In general, in a switched capacitor circuit using a switch circuit, the DC potential of the signal voltage Vi input to the source of the field effect transistor is set to the power supply voltage Vdd and the ground potential (0 V) because it is desired to increase the signal-to-noise power ratio. )) Around the median value Vdd / 2. Also for the switch circuit, it is important that the ON resistance is sufficiently small and the OFF resistance is sufficiently large in the vicinity of Vi = Vdd / 2.

  As the process becomes finer, the power supply voltage decreases, but the threshold voltage of the field effect transistor does not decrease as much as the rate of decrease of the power supply voltage. For this reason, when the power supply voltage is lowered with the miniaturization of the process, the power supply voltage eventually falls below the threshold voltage (in the case of a CMOS switch circuit, the sum of the absolute values of the threshold voltages of the NMOS transistor and the PMOS transistor). In this case, in the vicinity of Vi = Vdd / 2, the gate-source voltage of the field effect transistor becomes lower than the threshold voltage, and it becomes difficult to sufficiently reduce the ON resistance.

  In order to solve this problem, a special field effect transistor having a threshold voltage smaller than that of a normal field effect transistor may be used for the switch circuit. However, when a field effect transistor having a low threshold voltage is used, there arises a new problem that leakage current at the time of switch OFF increases. For example, in the switched capacitor circuit, if the charge of the capacitor leaks through the switch circuit, the accuracy of the switched capacitor circuit is greatly deteriorated, which is a serious problem.

  Specifically, taking as an example a CMOS switch circuit in which the source of an NMOS transistor and a PMOS transistor is connected to a signal source and the drain is connected to a capacitor, the gate of the NMOS transistor is connected to the ground potential when the switch is OFF, and the PMOS transistor Is connected to the power supply voltage Vdd. The leak current flowing from the capacitor through the NMOS transistor when the switch is OFF is considered to increase as the difference between the gate voltage and the signal voltage Vi increases. Considering the NMOS transistor, since the difference between the gate voltage and the signal voltage Vi is -Vi (0≤Vi≤Vdd), the leakage current becomes maximum when Vi = 0. The leakage current corresponds to the drain current Id (Vgs = 0) when Vgs = 0. Since the value of Id (Vgs = 0) is larger in the field effect transistor having the low threshold voltage, the field effect transistor having the low threshold voltage has a larger leakage current than the normal field effect transistor. The same can be said for the PMOS transistor.

  An object of the present invention is to provide a switch circuit capable of suppressing leakage current even when a field effect transistor having a low threshold voltage is used to reduce ON resistance.

  According to one aspect of the present invention, a switch circuit is connected between a first terminal and a second terminal and performs a switching operation according to a control signal, the gate to which the control signal is input, and the first A first field effect transistor of a first conductivity type having a drain connected to one terminal; a gate to which the control signal is input; a drain connected to a source of the first field effect transistor; A first conductivity type second field effect transistor having a source connected to two terminals, and between the source of the first field effect transistor and the drain of the second field effect transistor and a constant potential point. Provided is a switch circuit including a switch element connected and controlled by the control signal.

  In the switch circuit according to the first aspect, the source of the first field effect transistor and the drain of the second field effect transistor are fixed at the potential of the constant potential point when the switch is OFF. As a result, the leakage current always becomes the minimum value, and the average value of the leakage current can be reduced as compared with the conventional NMOS switch circuit.

  Specifically, for example, when the first and second field effect transistors are N-channel MOS transistors, the control signal is a voltage signal that transitions between the power supply voltage and the ground potential, and the constant potential point is the potential of the power supply voltage. Have In this case, when the switch is turned off, the source of the first field effect transistor and the drain of the second field effect transistor are fixed to the potential of the power supply voltage. The switch element is a P-channel MOS transistor.

  On the other hand, when the first and second field effect transistors are P-channel MOS transistors, the control signal is a voltage signal that transitions between the ground potential and the power supply voltage, and the constant potential point has the ground potential. In this case, when the switch is turned off, the source of the first field effect transistor and the drain of the second field effect transistor are fixed to the ground potential. An N channel MOS transistor is used as the switch element.

  According to another aspect of the present invention, in a switch circuit connected between a first terminal and a second terminal and performing a switching operation in accordance with the first and second control signals, the first control signal is input. A first field effect transistor of a first conductivity type having a gate connected to the first terminal and a drain connected to the first terminal; a gate to which the first control signal is input; and the first field effect transistor A first conductivity type second field effect transistor having a drain connected to the source and a source connected to the second terminal; a source of the first field effect transistor; and a second field effect transistor. A first switch element connected between the drain of the first electrode and a constant potential point and controlled by the first control signal; a gate to which the second control signal is input; and the first terminal A third field effect transistor of the second conductivity type having a drain connected to the gate, a gate to which the second control signal is input, a drain connected to a source of the third field effect transistor, and the first A second conductivity type fourth field effect transistor having a source connected to the second terminal, and between the source of the third field effect transistor and the drain of the fourth field effect transistor and a constant potential point. And a switch circuit connected to the second switch element controlled by the second control signal.

  Since the switch circuit according to the second aspect is a CMOS switch circuit and uses both an NMOS switch circuit and a PMOS switch circuit, the fluctuation of the ON resistance when the switch is turned on is higher than that of the NMOS switch circuit or the PMOS switch circuit. As a result, the signal becomes smaller near the center value of the ground potential and signal distortion can be suppressed. The other points are basically the same as the NMOS switch circuit or the PMOS switch circuit according to the first aspect.

  According to the present invention, in an NMOS switch circuit or a PMOS switch circuit in which two field effect transistors of the same conductivity type having two low threshold voltages are connected in series, a connection point between the two field effect transistors when the switch is turned off using a switch element. Is fixed to the power supply potential in the case of an NMOS switch circuit, and to the ground potential in the case of a PMOS switch circuit, the leakage current when the switch is OFF can be reduced. Further, in the CMOS switch circuit, an effect that the signal distortion is reduced with respect to the signal voltage at the substantially central value of the power supply voltage and the ground voltage is newly obtained.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
The switch circuit according to the first embodiment of the present invention shown in FIG. 1 is an NMOS switch circuit, and includes two NMOS transistors 101 and 102. The drain of the NMOS transistor 101 is connected to the first terminal T1, which is one end of the switch circuit. The terminal T1 is connected to the signal source 103, for example. Assume that the signal source 103 generates a signal voltage Vi of 0 ≦ Vi ≦ Vdd. The source of the NMOS transistor 101 and the drain of the NMOS transistor 102 are connected. The source of the NMOS transistor 102 is connected to the second terminal T2 which is the other end of the switch circuit. The terminal T2 is connected to the capacitive element 104, for example.

  A control signal 100 is input to the gates of the NMOS transistors 101 and 102. A switch element 105 is connected between the drains of the NMOS transistors 101 and 102 and the power supply voltage Vdd. The switch element 105 is turned on / off by the control signal 100. In this example, the control signal 100 is a voltage signal that transitions between the power supply voltage Vdd and the ground potential (0 potential), and the NMOS switch circuit performs an ON / OFF operation by the control signal 100.

Next, the operation of the NMOS switch circuit of FIG. 1 will be described.
When the NMOS switch circuit is turned on, the voltage of the control signal 100, that is, the gate potential of the NMOS transistors 101 and 102 is set to Vdd, and the switch element 105 is turned off. The gate-drain voltage of the NMOS transistor 101 is Vdd-Vi. Here, when an element having a low threshold voltage VtNlow that satisfies Vdd−Vi ≧ VtNlow, for example, Vdd / 2 ≧ VtNlow is used for the NMOS transistors 101 and 102, the NMOS transistor 101 is turned on, and the NMOS transistor 102 is also turned on. It becomes a state. At this time, the ON resistances of the NMOS transistors 101 and 102 are sufficiently small. Accordingly, the NMOS switch circuit is turned on, and a signal current flows between the signal source 103 and the capacitor 104.

  Next, when the NMOS switch circuit is turned off, the voltage of the control signal 100, that is, the gate potential of the NMOS transistors 101 and 102 is set to 0, and the switch element 105 is turned on. Here, paying attention to the NMOS transistor 102, the drain potential of the NMOS transistor 102 becomes equal to the power supply voltage Vdd, so that the gate-drain voltage becomes −Vdd.

  This state is equivalent to the case where the signal voltage Vi is Vdd in a conventional NMOS switch circuit using a single NMOS transistor. In the conventional NMOS switch circuit, the leakage current is maximized when the signal voltage Vi (0 ≦ Vi ≦ Vdd) is Vi = 0, and the leakage current is minimized when Vi = Vdd. The average value of the leakage current corresponds to the leakage current when Vi = Vdd / 2.

  FIG. 2 shows the relationship between the gate-source voltage Vgs and the drain current Id for an NMOS transistor having a normal threshold voltage (StdVth) and a low threshold voltage (LowVth). The relationship between Vgs and Id corresponds to the relationship between the potential difference between the gate potential and the signal voltage and the leakage current. As shown in FIG. 2, the drain current when the gate-source voltage Vgs = 0 is small (0 in the example shown) in the NMOS transistor having the normal threshold voltage as shown by the point A, whereas the drain current is low. The voltage NMOS transistor is large as shown by point B. Therefore, when an NMOS transistor having a low threshold voltage is used, the leakage current increases.

  On the other hand, the leakage current of the NMOS transistor 102 in FIG. 1, that is, the current flowing through the NMOS transistor 102 when the NMOS switch circuit is OFF corresponds to the case where Vi = Vdd is fixed in the conventional NMOS switch circuit, Always minimal.

  As described above, in the NMOS switch circuit according to the present embodiment, the switch element 105 is turned on in the OFF state of the switch circuit, and the drain potential of the NMOS transistor 102 is fixed to Vdd. Therefore, even when an NMOS transistor having a low threshold voltage is used to reduce the ON resistance, the leakage current can be reduced as compared with the conventional NMOS switch circuit.

  FIG. 3 shows an example in which the NMOS switch circuit of FIG. 1 is embodied. In the NMOS switch circuit of FIG. 3, the switch element 105 shown in FIG. The source of the PMOS transistor 106 is connected to the power supply Vdd, and the drain is connected to the source of the NMOS transistor 101 and the drain of the NMOS transistor 102. A control signal 100 is input to the gate of the PMOS transistor 106.

  Next, it will be described that the PMOS transistor 106 functions as the switch element 105 shown in FIG. When the voltage of the control signal 100 is set to the power supply voltage Vdd and the gate potential of the PMOS transistor 106 is set to Vdd in order to turn on the NMOS switch circuit of FIG. 3, the gate-source voltage of the PMOS transistor 106 becomes zero. Since this is sufficiently larger than the resistance between the source and drain of the NMOS transistors 101 and 102, the PMOS transistor 106 is turned off.

  On the other hand, when the NMOS switch circuit is turned off, the voltage of the control signal 100 is set to zero. Here, if the switch element 105 is an NMOS transistor, if the source potential of the NMOS transistor 102 is close to Vdd, a sufficiently small ON resistance cannot be obtained even if the gate potential is Vdd, and the leakage current does not decrease. There is. On the other hand, when the PMOS transistor 106 is used as the switch element 105, the gate-source voltage of the PMOS transistor 106 becomes −Vdd regardless of the source potential of the NMOS transistor 102. Since this is smaller than the threshold voltage (−VtP) of the PMOS transistor 106, it is always in the ON state with a sufficiently small ON resistance.

(Second Embodiment)
Next, a PMOS switch circuit according to a second embodiment of the present invention will be described with reference to FIG. The PMOS switch circuit of FIG. 4 has two PMOS transistors 201 and 202. The drain of the PMOS transistor 201 is connected to the first terminal T1, which is one end of the switch circuit. The terminal T1 is connected to the signal source 203, for example. Assume that the signal source 203 generates a signal voltage Vi of 0 ≦ Vi ≦ Vdd. The source of the PMOS transistor 201 and the drain of the PMOS transistor 202 are connected. The source of the PMOS transistor 202 is connected to the second terminal T2 which is the other end of the switch circuit. The terminal T2 is connected to the capacitive element 204, for example.

  A control signal 200 is input to the gates of the PMOS transistors 201 and 202. A switch element 205 is connected between the drains of the PMOS transistors 201 and 202 and the ground potential (0 potential). The switch element 205 is turned on / off by the control signal 200. In this example, the control signal 200 is a voltage signal that transitions between the ground potential and the power supply voltage Vdd, and the PMOS switch circuit performs an ON / OFF operation by the control signal 200.

Next, the operation of the PMOS switch circuit of FIG. 4 will be described.
When the PMOS switch circuit is turned on, the voltage of the control signal 200, that is, the gate potential of the PMOS transistors 201 and 202 is set to 0 potential, and the switch element 205 is turned off. The gate-drain voltage of the PMOS transistor 201 is Vdd-Vi. Here, when an element having a low threshold voltage −VtPlow that satisfies | Vi | ≧ VtPlow is used for the PMOS transistors 201 and 202, the PMOS transistor 201 is turned on, and the PMOS transistor 202 is also turned on. At this time, the ON resistances of the PMOS transistors 201 and 202 are sufficiently small. Accordingly, the PMOS switch circuit is turned on, and a signal current flows between the signal source 203 and the capacitor 204.

  Next, when the PMOS switch circuit is turned off, the voltage of the control signal 200, that is, the gate potential of the PMOS transistors 201 and 202 is set to Vdd, and the switch element 205 is turned on. Here, paying attention to the PMOS transistor 202, the drain potential of the PMOS transistor 202 becomes 0, and therefore the gate-drain voltage becomes Vdd.

  This state is equivalent to the case where the signal voltage Vi is 0 in a conventional PMOS switch circuit using a single PMOS transistor. In the conventional PMOS switch circuit, the leak current is maximum when the signal voltage Vi (0 ≦ Vi ≦ Vdd) is Vi = Vdd, and the leak current is minimum when Vi = 0. The average value of the leakage current corresponds to the leakage current when Vi = Vdd / 2. Similar to the low threshold voltage NMOS transistor, the use of a low threshold voltage PMOS transistor increases the leakage current.

  On the other hand, the leakage current of the PMOS transistor 202 in FIG. 4, that is, the current flowing through the PMOS transistor 202 when the PMOS switch circuit is OFF corresponds to the case where Vi = 0 is fixed in the conventional PMOS switch circuit, Always minimal.

  As described above, in the PMOS switch circuit according to the present embodiment, the switch element 205 is turned ON when the switch circuit is OFF, and the drain potential of the PMOS transistor 202 is fixed to 0. Accordingly, even when a low threshold voltage PMOS transistor is used to reduce the ON resistance, the leakage current can be reduced as compared with the conventional PMOS switch circuit.

  FIG. 5 shows an example in which the PMOS switch circuit of FIG. 4 is embodied. In the PMOS switch circuit of FIG. 5, the switch element 205 shown in FIG. The source of the NMOS transistor 206 is connected to the ground potential, and the drain is connected to the source of the PMOS transistor 201 and the drain of the PMOS transistor 202. A control signal 200 is input to the gate of the NMOS transistor 206.

  Next, it will be described that the NMOS transistor 206 functions as the switch element 205 shown in FIG. When the voltage of the control signal 200 is set to 0 and the gate potential of the NMOS transistor 206 is set to 0 in order to turn on the PMOS switch circuit of FIG. 5, the gate-source voltage of the NMOS transistor 206 becomes 0. Since this is sufficiently larger than the resistance between the source and drain of the PMOS transistors 201 and 202, the NMOS transistor 206 is turned off.

  On the other hand, when the PMOS switch circuit of FIG. 5 is turned off, the voltage of the control signal 200 is set to the power supply voltage Vdd. Here, if the switching element 205 is a PMOS transistor, if the source potential of the PMOS transistor 202 is close to 0, a sufficiently small ON resistance cannot be obtained even if the gate potential is 0, and the leakage current does not decrease. There is. On the other hand, when the NMOS transistor 206 is used as the switch element 205, the gate-source voltage of the NMOS transistor 206 becomes Vdd regardless of the source potential of the PMOS transistor 202. Since this is larger than the threshold voltage (VtN) of the PMOS transistor 206, it is always ON with a sufficiently small ON resistance.

(Third embodiment)
FIG. 6 shows an NMOS switch circuit according to the third embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 will be described. In the NMOS switch circuit of FIG. 6, the NMOS transistor 107 is sandwiched between the source of the NMOS transistor 101 and the drain of the NMOS transistor 102. The drain of the NMOS transistor 107 is connected to the source of the NMOS transistor 101, and the source of the NMOS transistor 107 is connected to the drain of the NMOS transistor 102.

  Accordingly, two switch elements 105A and 105B corresponding to the switch element 105 shown in FIG. 1 are provided. One end of the switch element 105A is connected to the drain of the NMOS transistor 107 and the source of the NMOS transistor 101, and one end of the switch element 105B is connected to the source of the NMOS transistor 107 and the drain of the NMOS transistor 102. The other ends of the switch elements 105A and 105B are connected to the power supply Vdd. As the switch elements 105A and 105B, for example, PMOS transistors can be used as in FIG.

  Hereinafter, it will be described that the NMOS switch circuit correctly performs ON / OFF operation even when the NMOS transistor 107 is added. When the NMOS switch circuit is turned on, the gate potentials of the NMOS transistors 101, 102 and 107 are set to Vdd. As a result, the NMOS transistor 107 has a sufficiently low resistance between the source and the drain, like the NMOS transistors 101 and 102, so that the NMOS switch circuit is turned on.

  When the NMOS switch circuit is turned off, the gate potentials of the NMOS transistors 101, 102 and 107 are set to zero potential. At this time, since the switch elements 105A and 105B are in the ON state, the gate-source voltage and the gate-drain voltage of the NMOS transistor 107 are both -Vdd. Therefore, since the NMOS transistor 107 has a sufficiently large resistance between the source and the drain, the NMOS switch circuit is turned off.

(Fourth embodiment)
FIG. 7 shows an NMOS switch circuit according to the fourth embodiment of the present invention. In the NMOS switch circuit of FIG. 7, an impedance element 108 is inserted instead of the NMOS transistor 107 in the NMOS switch circuit of FIG. The impedance element 108 is a resistance element having an impedance equivalent to or lower than the ON resistance of the NMOS transistors 101 and 102, for example.

  Hereinafter, it will be described that the NMOS switch circuit operates correctly even when the impedance element 108 is inserted. First, when the NMOS switch circuit is turned on, the impedance of the impedance element 108 is equal to or less than the ON resistance of the NMOS transistors 101 and 102 as described above, so that the ON resistance is still kept sufficiently small, as shown in FIG. The NMOS switch circuit shows an ON state.

  When the NMOS switch circuit is turned off, since the switch elements 105A and 105B are in the ON state, the potentials at both ends of the impedance element 108 are both Vdd. Since this is the same as the state of the NMOS switch circuit shown in FIG. 1 when the switch is OFF, the NMOS switch circuit of FIG. 7 clearly shows the OFF state.

(Fifth embodiment)
FIG. 8 shows a PMOS switch circuit according to a fourth embodiment of the present invention. The difference from the second embodiment shown in FIG. 4 will be described. In the PMOS switch circuit of FIG. 8, the PMOS transistor 207 is sandwiched between the source of the PMOS transistor 201 and the drain of the PMOS transistor 202. The drain of the PMOS transistor 207 is connected to the source of the PMOS transistor 201, and the source of the PMOS transistor 207 is connected to the drain of the PMOS transistor 202.

  Accordingly, two switch elements 205A and 205B corresponding to the switch element 205 shown in FIG. 4 are provided. One end of the switch element 205A is connected to the drain of the PMOS transistor 207 and the source of the PMOS transistor 201, and one end of the switch element 205B is connected to the source of the PMOS transistor 207 and the drain of the PMOS transistor 202. The other ends of the switch elements 205A and 205B are connected to the ground potential. As the switch elements 205A and 205B, for example, NMOS transistors can be used as in FIG.

  Hereinafter, it will be described that the PMOS switch circuit operates correctly even when the PMOS transistor 207 is added. When the PMOS switch circuit is turned on, the gate potentials of the PMOS transistors 201, 202, and 207 are set to zero. As a result, the NMOS transistor 207 has a sufficiently low resistance between the source and the drain as in the PMOS transistors 201 and 202, so that the PMOS switch circuit is turned on.

  When the PMOS switch circuit is turned off, the gate potentials of the PMOS transistors 201, 202 and 207 are set to Vdd. At this time, since the switch elements 205A and 205B are in the ON state, the gate-source voltage and the gate-drain voltage of the PMOS transistor 207 are both Vdd. Accordingly, the PMOS transistor 207 has a sufficiently large resistance between the source and the drain, so that the PMOS switch circuit is turned off.

(Sixth embodiment)
FIG. 9 shows a PMOS switch circuit according to a sixth embodiment of the present invention. In the NMOS switch circuit of FIG. 9, an impedance element 208 is inserted in place of the PMOS transistor 207 in the PMOS switch circuit of FIG. The impedance element 208 is a resistance element having an impedance equivalent to or lower than the ON resistance of the PMOS transistors 201 and 202, for example.

  Hereinafter, it will be described that the PMOS switch circuit operates correctly even when the impedance element 208 is inserted. First, when the PMOS switch circuit is turned on, the impedance of the impedance element 208 is equal to or less than the ON resistance of the PMOS transistors 201 and 202 as described above, so that the ON resistance is still kept sufficiently small. The PMOS switch circuit is in the ON state.

  When the PMOS switch circuit is turned off, since the switch elements 205A and 205B are in the ON state, the potentials at both ends of the impedance element 208 are both zero. Since this is the same as the state of the PMOS switch circuit shown in FIG. 4 when the switch is OFF, the PMOS switch circuit of FIG. 9 clearly shows the OFF state.

(Seventh embodiment)
Next, a CMOS switch circuit according to a seventh embodiment of the present invention will be described with reference to FIG. In the CMOS switch circuit of FIG. 10, the same NMOS switch circuit as in FIG. 1 and the same PMOS switch circuit as in FIG. 4 are connected in parallel. The first terminal T1 of the CMOS switch circuit is commonly connected to the signal source 303, and the second terminal T2 is commonly connected to the capacitor 304.

  The control signal 100 input to the NMOS switch circuit and the control signal 200 input to the PMOS switch circuit make a complementary transition between the power supply voltage Vdd and the ground potential (0 potential). That is, when the control signal 100 is the power supply voltage Vdd, the control signal 200 becomes 0 potential, both the NMOS switch circuit and the PMOS switch circuit are turned on, and therefore the CMOS switch circuit is turned on. On the other hand, when the control signal 100 is 0 potential, the control signal 200 becomes Vdd, and both the NMOS switch circuit and the PMOS switch circuit are in the OFF state, and thus the CMOS switch circuit is in the OFF state. Since the operations of the NMOS switch circuit and the PMOS switch circuit are independent, the CMOS switch circuit can obviously perform ON / OFF operations.

  Regarding the leakage current when the switch is OFF, the individual leakage currents of the NMOS switch circuit and the PMOS switch circuit included in the CMOS switch circuit of FIG. 10 are smaller than those of the conventional CMOS switch circuit. The average value of the leakage current from the capacitor 304 is smaller in the switch circuit.

  Further, the CMOS switch circuit has an advantage that the signal distortion when the DC potential of the signal is in the vicinity of Vi = Vdd / 2 is smaller than that of the NMOS switch circuit or the PMOS switch circuit alone. FIG. 11 shows the conductance (hereinafter referred to as ON conductance) when the switch is ON, which is the reciprocal of the ON resistance of each of the NMOS switch circuit, PMOS switch circuit, and CMOS switch circuit when the signal voltage Vi varies from 0 to Vdd. It represents the change of.

  As shown in FIG. 11, the ON conductance of the NMOS switch circuit and the PMOS switch circuit has a large slope in the vicinity of Vi = Vdd / 2. Therefore, in the NMOS switch circuit alone or the PMOS switch circuit alone, the time constant due to the ON resistance of the switch and the capacitance value of the capacitive element greatly increases / decreases due to slight fluctuations in the DC potential Vi of the signal until the voltage of the capacitive element reaches Vi. Variation occurs in the time. This is because, for example, in a circuit such as a switched capacitor circuit in which switching ON / OFF is repeated with a clock having a constant frequency, the voltage of the capacitive element 304 does not reach the value of Vi until the switch is turned OFF. As a result, the voltage of the capacitor 304 is greatly distorted with respect to the signal voltage of the signal source 303.

  On the other hand, the ON conductance of the CMOS switch circuit is the sum of the ON conductance of the NMOS switch circuit and the ON conductance of the PMOS switch circuit. Further, the sign of the slope of the ON conductance near Vi = Vdd / 2 is opposite between the NMOS switch circuit and the PMOS switch circuit. From these facts, as shown in FIG. 11, the ON conductance of the CMOS switch circuit has a smaller slope near Vi = Vdd / 2 than that of the NMOS switch circuit and the PMOS switch circuit, so that the NMOS switch circuit alone or the PMOS switch circuit alone The signal distortion is smaller than in the above case.

  FIG. 12 is a specific example of the CMOS switch circuit of FIG. 10, and uses the NMOS switch circuit shown in FIG. 3 and the PMOS switch circuit shown in FIG. That is, in the CMOS switch circuit of FIG. 12, the switch element 105 of the NMOS switch circuit is realized by the PMOS transistor 106, and the switch element 205 of the PMOS switch circuit is realized by the NMOS transistor 206. Since the operation and effect of the CMOS switch circuit of FIG. 12 are apparent from the description of FIGS. 3, 5, and 10, the description thereof is omitted.

(Eighth embodiment)
FIG. 13 shows a CMOS switch circuit according to the eighth embodiment of the present invention. In the CMOS switch circuit of FIG. 13, the same NMOS switch circuit as in FIG. 6 and the same PMOS switch circuit as in FIG. 8 are connected in parallel. That is, in the NMOS switch circuit, the NMOS transistor 107 is sandwiched between the source of the NMOS transistor 101 and the drain of the NMOS 102. In the PMOS switch circuit, a PMOS transistor 207 is sandwiched between the source of the PMOS transistor 201 and the drain of the PMOS 202. The first terminal T1 of the CMOS switch circuit is commonly connected to the signal source 303, and the second terminal T2 is commonly connected to the capacitor 304. Since the operation and effect of the CMOS switch circuit of FIG. 13 are apparent from the description of FIGS. 6, 8, and 10, the description thereof will be omitted.

(Ninth embodiment)
FIG. 14 shows a CMOS switch circuit according to the ninth embodiment of the present invention, in which the same NMOS switch circuit as in FIG. 7 and the same PMOS switch circuit as in FIG. 9 are connected in parallel. That is, the impedance element 108 is inserted in place of the NMOS transistor 107 in the NMOS switch circuit in the CMOS switch circuit of FIG. 13, and the impedance element 208 is inserted in place of the PMOS transistor 207 in the PMOS switch circuit. The operation and effect of the CMOS switch circuit of FIG. 14 are apparent from the description of FIG. 7, FIG. 9, and FIG.

(Application examples)
Next, an application example of the switch circuit described in the above embodiment will be described. The switch circuit can of course be used in various electronic circuits, but here, a pipeline type A / D converter will be described as an example.

  FIG. 15 is a diagram illustrating a configuration of a pipeline type A / D converter. The analog input signal 10 is sampled and held by a sample and hold circuit (S / H) 11, that is, sampled according to a predetermined sampling clock, and held for a predetermined time. An analog signal output from the sample hold circuit 11 is input to a plurality of conversion stages 12A, 12B,.

  Each of the conversion stages 12A, 12B,..., 12N converts an analog signal input thereto into a digital signal having a relatively small number of bits as will be described later, and an analog residual indicating a conversion error of the converted digital signal. Output a signal.

  Residual signals output from conversion stages 12A, 12B,..., 12N-1 are input to subsequent conversion stages 12B,. The residual signal output from the final conversion stage 12N is converted into a digital signal by a 2-bit sub A / D converter (sub ADC) 13, for example.

  The digital signals output from the conversion stages 12A, 12B,..., 12N and the sub ADC 13 are combined by the digital combining circuit 14, and a high-resolution digital output signal 15 is generated as a whole. The digital signal output from the first conversion stage 12A is the most significant side of the digital output signal 15, and the digital signal output from the sub ADC 13 for A / D converting the residual signal output from the final conversion stage 12N is digital. It is the lowest side of the output signal 15.

  With respect to the same analog signal (sample hold value) output from the sample hold circuit 11, the digital signals output from the conversion stages 12A, 12B,..., 12N and the sub ADC 13 up to the conversion stage for outputting each digital signal. It has a relative delay time corresponding to the total delay time of each stage. Therefore, it goes without saying that the digital synthesis circuit 14 needs to synthesize each digital signal after compensating for such a relative delay time.

  FIG. 16 shows one configuration of the conversion stages 12A to 12N. An analog signal 21 output from the sample hold circuit 11 or the previous conversion stage is input to the conversion stage. The input analog signal 21 is first converted into a digital signal 23 having a relatively small number of bits by the sub ADC 22. The digital signal 23 output from the sub ADC 22 is input to the digital synthesis circuit 15 in FIG.

  The MDAC 24 is a kind of DAC having a sub DAC 25, a subtractor 26 and a residual amplifier 27. The digital signal 23 from the sub ADC 22 is converted into an analog signal by the sub DAC 25, and a difference signal between the analog signal and the analog signal 21 input to the non-variable conversion stage is obtained by the subtractor 26. The difference signal output from the subtractor 26 (referred to as a residual signal) is amplified by a residual amplifier 27. The residual signal 28 output from the residual amplifier 27 is output to the next non-variable conversion stage.

  Here, the sub DAC 25, the subtractor 26, and the residual amplifier 27 constituting the MDAC 24 are realized by a switched capacitor circuit including, for example, a switch group, a capacitor group, and an OTA (Operational Transconductance Amplifier). By using the switch circuit according to the above-described embodiment of the present invention as a switch in such a switched capacitor circuit or a switch in the sample hold circuit 11, the pipeline type A / D converter can be integrated with a small circuit area. It can be realized by a circuit.

  The present invention is not limited to the above-described embodiment, and can be modified and embodied without departing from the scope of the invention. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a circuit diagram showing an NMOS switch circuit according to a first embodiment of the present invention; The figure which shows the relationship between the gate-source voltage and drain current of the NMOS transistor which has a normal threshold voltage, and the NMOS transistor of a low threshold voltage More specifically, the NMOS switch circuit of FIG. Circuit diagram showing a PMOS switch circuit according to a second embodiment of the present invention A circuit diagram more specifically showing the PMOS switch circuit of FIG. Circuit diagram showing an NMOS switch circuit according to a third embodiment of the present invention Circuit diagram showing an NMOS switch circuit according to a fourth embodiment of the present invention The figure which shows the PMOS switch circuit based on the 5th Embodiment of this invention Circuit diagram showing a PMOS switch circuit according to a sixth embodiment of the present invention Circuit diagram showing a CMOS switch circuit according to a seventh embodiment of the present invention The figure which shows the relationship between the input signal voltage Vi of the NMOS switch circuit in the CMOS switch circuit of FIG. 10, a PMOS switch circuit, and a CMOS switch circuit, and the switch conductance at the time of switch ON Circuit diagram showing a CMOS switch circuit according to a seventh embodiment of the present invention Circuit diagram showing a CMOS switch circuit according to an eighth embodiment of the present invention Circuit diagram showing a CMOS switch circuit according to a ninth embodiment of the present invention A block diagram showing a configuration of a pipeline type A / D converter as an example of application of a switch circuit The block diagram which shows the structure of one conversion stage in FIG.

Explanation of symbols

100, 200 ... control signal;
101, 102, 107, 206 ... NMOS transistors 106, 201, 202, 207 ... PMOS transistors 103, 203, 303 ... signal sources 104, 204, 304 ... capacitive elements 105, 105A, 105B, 205, 205A, 205B ... switch elements 108, 208 ... impedance elements

Claims (7)

In a switch circuit connected between a first terminal and a second terminal and performing a switch operation according to a control signal:
A first field effect transistor of a first conductivity type having a gate to which the control signal is input and a drain connected to the first terminal;
A second field effect transistor of a first conductivity type having a gate to which the control signal is input, a drain connected to a source of the first field effect transistor, and a source connected to the second terminal;
A switch circuit comprising a switch element connected between a source of the first field effect transistor and a drain of the second field effect transistor and a constant potential point and controlled by the control signal.   The switch circuit according to claim 1, wherein the switch element is a field effect transistor of a second conductivity type.   The first and second field effect transistors are N-channel MOS transistors, the switch element is a P-channel MOS transistor, the control signal is a voltage signal that transitions between a power supply voltage and a ground potential, and the constant potential The switch circuit according to claim 1, wherein a point has the power supply voltage.   The first and second field effect transistors are P-channel MOS transistors, the switch element is an N-channel MOS transistor, the control signal is a voltage signal that transitions between a ground potential and a power supply voltage, and the constant potential 2. The switch circuit according to claim 1, wherein the point has a ground potential.   2. The switch circuit according to claim 1, wherein the first and second field effect transistors have an absolute value of a threshold voltage equal to or less than half of a power supply voltage. In a switch circuit connected between a first terminal and a second terminal and performing a switch operation in accordance with first and second control signals:
A first field effect transistor of a first conductivity type having a gate to which the first control signal is input and a drain connected to the first terminal;
A second field effect of a first conductivity type having a gate to which the first control signal is input, a drain connected to a source of the first field effect transistor, and a source connected to the second terminal. With a transistor;
A first switch element connected between a source of the first field effect transistor and a drain of the second field effect transistor and a constant potential point and controlled by the first control signal;
A second conductivity type third field effect transistor having a gate to which the second control signal is input and a drain connected to the first terminal;
A fourth field effect of a second conductivity type having a gate to which the second control signal is input, a drain connected to a source of the third field effect transistor, and a source connected to the second terminal; With a transistor;
A switch comprising a second switch element connected between a source of the third field effect transistor and a drain of the fourth field effect transistor and a constant potential point and controlled by the second control signal circuit.   The switch circuit according to claim 6, wherein the first switch element is a second conductivity type field effect transistor, and the second switch element is a first conductivity type field effect transistor.

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