JP2001094425A - Chopper type comparator and a/d converter employing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chopper type comparator whose current consumption is reduced, the voltage gain of the linear amplifier of which can be increased and whose detection sensitivity is enhanced and to provide a successive approximation A/D converter employing the chopper type comparator. SOLUTION: Different gate bias voltage VGa and VGb are applied respectively to gates of a PMOS transistor(TR) 11a and an NMOS TR 12a that are connected in series, a switch 15a is closed to apply a reference voltage Vref to a node 9 thereby pre-charging capacitors 13a, 13b. Then a switch 15b is closed to apply an input voltage Vi to the node 9 and to control a gate voltage of the TRs 11a, 12a through the capacitive coupling of the capacitors 13a, 13b and an output voltage Vout of the chopper type comparator 3a is controlled in response to the difference between the input voltage Vi and the reference voltage Vref. Thus, a thorugh-current of the TRs 11a, 12a can be reduced to decrease the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chopper type comparator and a successive approximation type A / D converter using the same.

[0002]

2. Description of the Related Art Generally, in a chopper type comparator, a capacitor is connected to the input side of a linear amplifier (linear amplifier circuit), and a pair of input terminals for inputting a signal to be compared and a reference signal is connected to a switch. The input side and the output side of the linear amplifier are connected by a switch, and the input signal is compared by controlling on / off of a switch of an input terminal and a switch of the linear amplifier.

FIG. 8 shows a basic configuration of a successive approximation A / D converter disclosed as a prior art in Japanese Patent Application Laid-Open No. 64-57811 as one application example of a chopper type comparator. As shown in FIG.
The analog signal V _i is input to one input terminal of the D / A converter 1 and the analog output V _ref of the D / A converter 1 is input to the other input terminal.
Is entered. The output signal of the comparator 3 is inputted to the successive approximation register and the control logic circuit 2, and the digital signal is sent from the successive approximation register and the control logic circuit 2 to the D / A converter 1, the output latch and the buffer circuit 6, respectively. Is output. In FIG. 8, reference numeral 7 denotes a control register for controlling the entire operation of the successive approximation A / D converter. The D / A converter 1 includes an analog switch group 4 and a series resistor circuit 5 in this example. Input analog signal V from latch and buffer circuit 6
Conversion data D _out corresponding to _i is output.

[0004] Successive comparison register and control logic circuit 2
Is the analog output V of the D / A converter 1.
_ref most levels of near digital signal and the analog input signal V _i is output. Here, the operation of the successive approximation type A / D converter will be described with reference to a flowchart shown in FIG. 9, assuming that the number of bits of the digital data D _out to be A / D converted is N.

First, a voltage (V _fs / 2) that is half of the full-scale voltage V _fs is output by the D / A converter 1 as a reference voltage V _ref (step S 1). In the comparator 3, the reference voltage _Vref and the analog input signal V
The levels of _i are compared (step S2). As a result of the comparison, if the input signal V _i is the reference voltage _{V ref (= V fs / 2} ) less than, for the current reference voltage V _ref, 1 half of that value, i.e. (V _ref / 2 = V _fs / 4) is subtracted to set a new reference voltage (V _fs / 4), and at the same time, 0 is set to _DN , which is the most significant digit of the digital data D _out (step S4). Conversely, if greater than the input signal V _i is the reference voltage _{V ref (= V fs / 2} ) is, for the current reference voltage V _ref, 1 half of that value, i.e. (V _ref
/ 2 = _Vfs / 4) and add a new reference voltage ( _3Vfs /
At the same time as 4) is set, 1 is set to _DN which is the most significant digit of the digital data D _out (step S).
3). Next, the obtained new reference voltage V _ref is input to the comparator 3, the digit position of the digital data is reduced by 1, and the above operation is repeatedly performed until the digit position of the digital data becomes the lowest (step S 5). , S6).

In the successive approximation type A / D converter described above, a chopper type comparator shown in FIG. In FIG. 10, 10
Is a linear amplifier composed of a p-channel MOS transistor (hereinafter, referred to as a pMOS transistor) 11 and an n-channel MOS transistor (hereinafter, referred to as an nMOS transistor) 12. As shown, the pMOS transistor 11 and the nMOS transistor 12 are , Positive supply voltage V _CC supply line and negative supply voltage (or common potential)
It is configured to be connected in series with the supply line of V _SS .

[0007] A switch 19 is connected between the output terminal 18 and the input terminal 17 of the linear amplifier 10.
And one electrode of the capacitor 13 are connected, and the other electrode of the capacitor 13 is connected to the reference voltage V
with _ref are connected to a terminal 16a to be inputted, it is connected to the terminal 16b of the analog signal V _i is inputted through the switch 15b.

The switches 15a, 15b and 19 of the chopper type comparator shown in FIG. 10 are turned on / off at the timing shown in FIG. Here, the ON / OFF control of the switches 15a, 15b and 19 is performed by the successive approximation register and the control logic circuit 2 shown in FIG.

Here, the input voltage of the linear amplifier 10 is
_in , and the output voltage is _Vout , the linear amplifier 10
It has input / output transfer characteristics shown in FIG. Hereinafter, the operation of the chopper type comparator will be described focusing on the on / off operation of the switches 15a, 15b and 19 and referring to the input / output transfer characteristics of FIG. First, the switches 15a,
19 is turned on and the switch 15b is controlled to open. Since the switch 15a conducts, the capacitor 13
Of the other electrode is set to the reference voltage _Vref . Further, since the switch 19 is rendered conductive, the input voltage V _in and the output voltage V of the operating point of the linear amplifier 10 is the linear amplifier
_out is equal, that is, the operating point o shown in the figure is set. At this operating point o, the input voltage a and the output voltage b of the linear amplifier 10 are both held at the intermediate value V _CC / 2 between the power supply voltage V _CC and the common potential V _SS (the common potential V _{CC).
SS is set} to 0V).

Next, the switches 15a and 19 are opened,
The switch 15b is controlled so as to conduct. Thus, depending on whether the analog input voltage V _i is the reference voltage V _ref is less than or greater, by capacitive coupling of the capacitor 13, o the operating point of the linear amplifier 10 is shown in FIG. 12
It is set to either 1 or o2. For example, (V _i <V
_ref ), the linear amplifier is set to the operating point o1. In this case, the operating point o the input voltage V _in is initially set
And the output voltage becomes b1. Conversely, if (V _i > V _ref ), the linear amplifier is set to the operating point o2. At this time, the input voltage V _in
Becomes a voltage a2 higher than the voltage a corresponding to the operating point o set first, and the output voltage becomes b2. As a result, the output voltage V _out of _the linear amplifier according to whether the analog input voltage V _i is to or greater reference signal V _ref is smaller than b1
Or is set to b2, it is possible to compare the analog input voltage V _i and the reference voltage V _ref in response to the output voltage V _out.

[0011]

However, in the above-mentioned conventional chopper type comparator, the first problem is that the current flowing through the linear amplifier becomes the largest when the comparison voltage _Vref is input and in the standby state. There is a disadvantage that current consumption is large. As described above, both the input and output terminals of the linear amplifier are connected to the power supply voltage _Vref when the comparison voltage _Vref is input and during standby.
It is held in midpoint V _CC / 2 of the _CC. At this time, since a large through current flows through the transistors 11 and 12, there is a disadvantage that power consumption increases. As a second problem, when the power supply voltage is large, the fluctuation width of the output voltage _Vout with respect to the fluctuation width of the input voltage Vin becomes relatively small _in the input / output transfer characteristics shown in FIG. FIG. 12 also shows input / output transfer characteristics in the case of V _CC1 smaller than the power supply voltage V _CC for comparison. Greater As shown, when the power supply voltage is V _CC1, large gradients of the input and output characteristics, when the voltage gain of the linear amplifier of the power supply voltage V _CC. That is, the power supply voltage V _CC supplied to the linear amplifier
Increases, the voltage gain decreases, which causes a disadvantage that the detection sensitivity of the comparator decreases.

In view of the above circumstances, the present invention provides a chopper type comparator capable of reducing the current consumption of a linear amplifier, increasing the voltage gain of the linear amplifier in a wide range of power supply voltage, and obtaining a large detection sensitivity. It is an object of the present invention to provide a successive approximation type A / D converter.

[0013]

In order to achieve the above object, a chopper type comparator according to the present invention is a chopper type comparator for comparing an input signal with a reference signal,
A first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential; and a first p-channel transistor connected between a gate of the first p-channel transistor and an input node. A capacitor; a second capacitor connected between the gate of the first n-channel transistor and the input node; and a capacitor connected between a first input terminal to which the reference signal is input and the input node. A first switch, a second switch connected between the second input terminal to which the input signal is input and the input node, and a first gate applied to the gate of the first p-channel transistor A gate bias voltage generation circuit for generating a bias voltage and a second gate bias voltage applied to the gate of the first n-channel transistor; 1 of the switch is turned on, the first
And the second gate bias voltage to the first p
After applying to the gate of the channel transistor and the gate of the first n-channel transistor to precharge the first and second capacitors, the application of the first and second gate bias voltages is stopped, Is turned off, the second switch is turned on, and a signal corresponding to a difference between the input signal and the reference signal is supplied to the first p-channel transistor by capacitive coupling of the first and second capacitors. And a control circuit for applying a voltage to the gate of the first n-channel transistor.

Further, the chopper type comparator according to the present invention comprises a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential, and A first capacitor connected between the gate and the input node;
A second capacitor connected between the gate of the first n-channel transistor and the input node; and a first capacitor connected between a first input terminal to which the reference signal is input and the input node. A switch, a second switch connected between the second input terminal to which the input signal is input, and the input node, a first gate bias voltage applied to the gate of the first p-channel transistor, and A gate bias voltage generating circuit for generating a second gate bias voltage applied to the gate of the first n-channel transistor; and a second p-channel transistor connected in series between the power supply potential and the reference potential And one of the electrodes is connected to the first p-channel transistor and the first n-channel transistor. It is connected to, the other electrode the second
A third capacitor connected to a connection point between the gates of the p-channel transistor and the second n-channel transistor, and one terminal connected between the gates of the second p-channel transistor and the second n-channel transistor. A third switch connected to a connection point, the other terminal of which is connected to a connection midpoint between the second p-channel transistor and the second n-channel transistor, and a first switch that is turned on; Applying first and second gate bias voltages to the gate of the first p-channel transistor and the gate of the first n-channel transistor, respectively;
Precharging the first and second capacitors, turning on the third switch, and precharging the third capacitor, stopping the application of the first and second gate bias voltages; The first and third switches are turned off, the second switch is turned on, and a signal corresponding to a difference between the input signal and the reference signal is changed by the capacitive coupling of the first and second capacitors. A control circuit for applying to the gates of the first p-channel transistor and the first n-channel transistor.

Further, the chopper type comparator according to the present invention comprises a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential, and A first capacitor connected between the gate and the input node;
A second capacitor connected between the gate of the first n-channel transistor and the input node; and a first capacitor connected between a first input terminal to which the reference signal is input and the input node. A switch, a second switch connected between the second input terminal to which the input signal is input, and the input node, a first gate bias voltage applied to the gate of the first p-channel transistor, and A gate bias voltage generating circuit for generating a second gate bias voltage to be applied to the gate of the first n-channel transistor, the gates being connected to each other, and the connection point between the first p-channel transistor and the first p-channel transistor; A second p connected to a midpoint of connection with the n-channel transistor and connected in series between the power supply potential and the reference potential.
Turning on the first switch, and turning on the first and second gate bias voltages by the gate of the first p-channel transistor and the gate of the first n-channel transistor, respectively; After precharging the first and second capacitors, the application of the first and second gate bias voltages is stopped, the first switch is turned off, and the second switch is turned on. And a control for applying a signal corresponding to a difference between the input signal and the reference signal to gates of the first p-channel transistor and the first n-channel transistor by capacitive coupling of the first and second capacitors. And a circuit.

Further, in the present invention, preferably, the gate bias voltage generation circuit sets a voltage substantially lower than the power supply potential by an absolute value of a threshold voltage of the first p-channel transistor as the first bias voltage. And a voltage substantially higher than the reference potential by the threshold voltage of the first n-channel transistor is generated as the second bias voltage.

Further, the A / D converter of the present invention is an A / D converter for outputting a digital signal of N (N is a natural number) bits in accordance with the voltage of the input signal. D / A to convert to signal
A converter, a chopper type comparator for comparing an output signal of the D / A converter with the input signal, and a most significant bit to a least significant bit of the N-bit digital signal according to the output signal of the chopper type comparator A bit determination circuit for sequentially determining and outputting the N-bit digital signal to the D / A converter;
The chopper comparator includes a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential, and a connection between a gate of the first p-channel transistor and an input node. A first capacitor, a second capacitor connected between the gate of the first n-channel transistor and the input node, a first input terminal receiving the reference signal, and the input node. A first switch connected between the second input terminal to which the input signal is input, and a second switch connected between the input node and the second input terminal;
A gate bias voltage generation circuit that generates a first gate bias voltage applied to the gate of the first p-channel transistor and a second gate bias voltage applied to the gate of the first n-channel transistor;
Are turned on to apply the first and second gate bias voltages to the gates of the first p-channel transistor and the first n-channel transistor, respectively, thereby pre-charging the first and second capacitors. After charging, the application of the first and second gate bias voltages is stopped, the first switch is turned off, the second switch is turned on, and the input signal is supplied to the first and second capacitors. And a control circuit for applying a voltage to the gates of the first p-channel transistor and the first n-channel transistor by capacitive coupling.

According to the chopper type comparator of the present invention, a linear amplifier is constituted by the first p-channel transistor and the first n-channel transistor. In the linear amplifier, the gate bias voltage of each transistor is equal to the value of the power supply voltage. Irrespective of the above, they are set independently by the gate bias voltage generation circuit.
For example, the gate bias voltage of the first p-channel transistor is set to a voltage lower than the power supply potential by the absolute value of the threshold voltage of the p-channel transistor, or a voltage slightly lower than this, and the gate of the first n-channel transistor is The bias voltage is set to a voltage higher than the reference potential by the threshold voltage of the n-channel transistor, or a voltage slightly higher than this. Thereby, when the first and second capacitors are precharged, the through current flowing through the first p-channel transistor and the n-channel transistor can be suppressed to be small, and power consumption can be reduced, and the voltage gain of the linear amplifier can be reduced. Is independent of the power supply voltage,
It can always be kept large, and the detection sensitivity of the chopper type comparator can be improved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a chopper type comparator according to the present invention. As shown, in the chopper type comparator 3a of this embodiment, 11a and 12a
Are pMOS transistors and nMOS transistors constituting the linear amplifier 10a, respectively, and 13a and 1
3a is a capacitor, 14a and 14b are gate bias circuits for supplying gate bias voltages of the transistors 11a and 12a, 15a, 15b, 19a and 19b are switches, 16a is an input terminal to which a reference voltage _Vref is inputted, and 16b is an analog terminal. input terminal to which a signal V _i is inputted,
Reference numeral 18 denotes an output terminal of the chopper type comparator 3a.

The chopper type comparator 3a of the present embodiment can be applied to, for example, an A / D converter shown in FIG. In this case, the switches 15a, 15b, 19a, 19b of the chopper type comparator 3a are controlled by the successive approximation register and the control logic circuit 2 of the A / D converter, respectively. Hereinafter, the configuration of the chopper type comparator 3a of the present embodiment will be described with reference to FIG.

[0021] In the chopper type comparator 3a, the gate bias circuit 14a, by 14b, the gate bias voltage different to the gates of the pMOS transistor 11a and the nMOS transistor 12a VG _a and VG _b
Is applied. In the linear amplifier 10a, pMOS
The transistor 11a and the nMOS transistor 12a
Supply line of positive power supply voltage V _CC and negative power supply voltage (common potential)
It is connected in series between the V _SS supply lines. The gate of the pMOS transistor 11a is connected to the gate bias circuit 14a via the switch 19a, and the connection point 17a is connected to one electrode of the capacitor 13a. The gate of the nMOS transistor 12a is connected to the gate bias circuit 14b via the switch 19b, and the connection point 17b is connected to one electrode of the capacitor 13b. In the following description, the connection point 17
a and 17b as nodes 17a and 17b, respectively.
Notation. The other electrodes of capacitors 13a and 13b are commonly connected to node 9, and node 9 is connected to switch 1
With the reference voltage V _ref is connected to the terminal 16a that is input via the 5a, is connected to the terminal 16b of the analog input voltage V _i is inputted through the switch 15b.

FIG. 2 shows the gate bias circuits 14a and 14
4 shows an example of the configuration of b. In addition, as shown in FIG.
Here, the gate bias circuits 14a and 14b are constituted by one circuit. Hereinafter, the gate bias circuit is denoted by reference numeral 14.

As shown in FIG. 2, the gate bias circuit 1
4 is a switch 19c, pMOS transistors 30, 3
1, 32 and nMOS transistors 33, 34, 35,
36. Transistors 30, 33
And 34 are connected in series between the supply line of the power supply voltage V _CC and the common potential V _SS . A bias voltage _Vbs is applied to the gate of the transistor 30, and the transistors 33 and 34
Have a so-called diode connection in which the drain and the gate are connected respectively. Transistors 31, 32,
35 and 36 are connected in series between the supply line of the power supply voltage V _CC and the common potential V _SS . The transistor 31 is dioded, and the connection point 38 between the gate and the drain is connected to one terminal of the switch 19a, and the other terminal of the switch 19a is connected to the node 17a in FIG. The transistor 36 is diode-connected, a connection point 39 between the gate and the drain thereof is connected to one terminal of the switch 19b, and the other terminal of the switch 19b is connected to the node 1 of FIG.
7b.

The gate of the transistor 32 is connected to the switch 1
9c and biased to either the power supply voltage V _CC or the common potential V _SS . The gate of the transistor 35 is connected to a connection point 37 between the gate and the drain of the transistor 33 which is diode-connected.

The gate bias voltage V _bs applied to the gate of the transistor 30, for example, than the power supply voltage V _CC,
A voltage lower than the threshold voltage V _thp of the transistor 30 (V _CC −V _thp ) or a voltage slightly lower than the threshold voltage V _thp . Thus, the transistor 30 supplies a current i _p in the transistors 33 and 34 which are diode-connected. In this case, even when holding the gate of transistor 30 to the common potential V _SS, capable of supplying a current i _p, or, instead of the transistor 30, a resistance element which is constituted by a polysilicon resistor element or impurity diffusion resistors May be used. However, in order to suppress the power supply voltage dependence of the current i _p supplied to the diode 33, the power supply voltage V
_The bias voltage _Vbs set according to _CC is applied to transistor 3
It is desirable to supply to the zero gate.

In the thus configured gate bias circuit 14, for example, the transistors 33, 34,
_Assuming that the threshold voltages of 35 and 36 are both V _thn ,
The transistor 30, when a small current i _p is supplied to the diode-connected transistor 33 and 34, node 37, i.e., the gate voltage of the transistor 35 becomes slightly higher than 2V _thn. When the switch 19c is connected to the power supply voltage V _CC , the transistor 32
Are in a non-conductive state, the current flowing through the transistors 31, 32, 35 and 36 can be cut off, and the current consumption can be reduced. When the switch 19c is connected to the common potential V _SS , the transistor 32 is turned on, and the nodes 38 and 3
Voltage VG _a and VG _b 9 are respectively determined by the following equation.

[0027]

VG _a = V _CC − | V _thp | −ΔV _p (1)

[0028]

VG _b = V _SS + V _thn + ΔV _n (2)

In equations (1) and (2), ΔV _p and ΔV _p
V _n is a voltage dependent on the current i _p supplied by the transistor 30, for example, a threshold voltage V _thp, V _thn smaller voltages of the pMOS transistor 31 and nMOS transistor 36.

The gate bias voltage VG shown in equations (1) and (2) is obtained by the gate bias circuit 14 described above.
_a and VG _b is generated. Switches 19a and 19b
Are turned on, these gate bias voltages are respectively applied to the transistors 11a of the linear amplifier 10a shown in FIG.
And 12a. When the supply of the gate bias voltage is stopped, that is, when the switch 19
When the switches a and 19b are in the off state, the transistor 32 can be turned off by switching the switch 19c to the power supply voltage V _CC , and the transistors 31 and 3 can be turned off.
The current flowing through 2, 35 and 36 can be cut off, and power consumption can be saved.

FIG. 3 shows gate bias voltages VG _a and V G
Transistor 11 G _b are applied to the gates
The gate voltage V _g and the drain of a and 12a - is a graph showing the relationship between the source current I _ds. Curves A and B in FIG.
Correspond to the transistors 11a and 12a, respectively. As shown, when the gate bias voltages to the gates of the transistors 11a and 12a VG _a and VG _b is applied, the drain of these transistors - source current I _ds is kept small. When the gate voltage V _g applied to the transistor 11a rises, the drain - source current decreases, conversely, the gate voltage V _g applied to the transistor 11a is lowered, the drain - inter-gate current To increase. On the other hand, when the gate voltage V _g applied to the transistor 12a rises, the drain - source current is increased, conversely, the gate voltage V _g applied to the transistor 12a is lowered, the drain - inter-gate current Decrease.

FIG. 4 shows the switches 15a, 15b, 19
It is a timing chart which shows ON / OFF control of a, 19b, and 19c. Hereinafter, the operation of the chopper comparator 3a of the present embodiment will be described with reference to FIGS. As described above, the chopper type comparator 3
When a is applied to the A / D converter shown in FIG.
The switches 15a, 15b, 19a, 19b and 19c are controlled by a successive approximation register and a control logic circuit 2 of the A / D converter, respectively.

First, the switches 15a, 19a and 19b
Is turned on, the switch 19c is connected to the common potential V _SS side,
The switch 15b is controlled to open. As a result, the electrode on the node 9 side of the capacitor 13a is set to the reference voltage _Vref, and the electrode on the node 9 side of the capacitor 13b is also set to the reference voltage _Vref . Furthermore, the gate bias circuit 14, the node 17a and 17b are held in the gate bias voltage VG _a and VG _b, respectively.

Next, the switches 15a, 19a and 19
b is opened, the switch 19c is connected to the power supply voltage V _CC , and the switch 15b is controlled to be closed. By capacitive coupling of capacitor 13a and 13b, the difference between the analog input voltage V _i and the reference voltage V _ref (V _i -V _ref)
Is applied to each of the nodes 17a and 17b. The output voltage V _{out of the} linear amplifier depends on whether the input voltage V _i is smaller or larger than the reference voltage V _ref.
Is determined.

[0035] For example, when the input voltage V _i is higher than the reference voltage V _ref, the by capacitive coupling of capacitor 13a and 13b, the gate voltage of the transistor 11a and 12a are both increased, the transistor 11a is turned off, the transistor 12a is turned on Therefore, the output voltage _Vout of the chopper type comparator 3a decreases. Conversely, the input voltage V
_{When i} is lower than the reference voltage _Vref , the transistors 11a and 1
Since both the gate voltages of 2a decrease, the transistor 11a turns on and the transistor 12a turns off.
The output voltage V _out of the chopper comparator 3a is improved.

FIG. 5 shows the input / output transfer characteristics of the chopper type comparator of this embodiment. As shown, for example, when the gate bias voltage VG _a and VG _b is applied to the gates of the transistors 11a and 12a,
Assuming that the drain-source voltages of these transistors are equal, when the switches 14a, 19a and 19 are turned on, the output voltage V _out of the chopper comparator 3a becomes the midpoint between the power supply voltage V _CC and the common potential V _SS. That is, it is held at V _CC / 2 (the common potential V _{SS is set} to 0 V).
When the switches 14a, 19a and 19b are turned off and the switch 15a is turned on, the input voltage V _i is
And 13b by the capacitive coupling of transistor 11
a and 12a are applied to the gates. At this time, when the input voltage V _i is higher than the reference voltage V _ref, the transistor 11
Since the gate voltage V _g of a and 12a are both increased, the output voltage V _out is lowered, approaching to the common potential V _SS. on the other hand,
When the input voltage V _i is lower than the reference voltage V _ref, the gate voltage V _g of the transistor 11a and 12a are both increased,
It approaches the power supply voltage V _CC .

[0037] That is, in the chopper type comparator 3a of the present embodiment, by applying a different gate bias voltage VG _a and VG _b to the gates of the pMOS transistor 11a and the nMOS transistor 12a connected in series, further turns on the switch 15a , The reference voltage _Vref is applied to the node 9 to which the capacitors 13a and 13b are commonly connected via the switch 15a.
a and 13b are precharged. And switch 15
The b ON, by applying an input voltage V _i to node 9, the transistor 1 by capacitive coupling of the capacitor 13a and 13b
By controlling the gate voltages of 1a and 12a, in accordance with the difference between the input voltage V _i and the reference voltage V _ref, the output voltage V _out of _the chopper type comparator 3a is controlled.
When the precharge of the capacitor 13a and 13b, the transistors 11a and 12a are both held in the nonconductive state in response to the gate bias voltage VG _a and VG _b applied, significantly current flowing through the transistor 11a and 12a Power consumption can be reduced.

Second Embodiment FIG. 6 is a circuit diagram showing a second embodiment of a chopper type comparator according to the present invention. As shown, the chopper comparator 3b of the present embodiment is obtained by adding a second-stage comparator 20 to the output side of the chopper comparator 3a of the first embodiment shown in FIG.

As shown, in the chopper type comparator 3b of the present embodiment, the first stage chopper type comparator is the chopper type comparator 3a of the first embodiment.
Therefore, the same elements that constitute the circuit are denoted by the same reference numerals as in FIG. In addition, a detailed description of this portion will be omitted. Hereinafter, the configuration and operation of the second-stage comparator 20 will be described mainly with respect to the chopper-type comparator 3b of the present embodiment.

The second-stage comparator 20 includes a capacitor 21, a switch 22, a pMOS transistor 11b, and an nMOS transistor 12b.
The transistors 11b and 12b are connected in series between the supply line of the power supply voltage V _CC and the common potential V _SS , the gates of these transistors are connected to the node 23, and the connection point between the drains is connected to the output terminal 24. ing. Switch 2
One of the two terminals is connected to the node 23, and the other terminal is connected to the output terminal 24. One terminal of the capacitor 13 is connected to the output terminal 18 of the first-stage comparator, and the other terminal is connected to the node 23. Thus, in the second-stage comparator 20, the pMOS transistor 11b and the nMOS transistor 12b
Constructs a linear amplifier.

In the comparator 20, the switch 22
Are switches 19a and 19b of the first stage comparator
ON / OFF is controlled at the same timing as described above. That is, when the switches 19a and 19b are turned on, the switch 22
Is turned on, and when the switches 19a and 19b are turned off, the switch 22 is also controlled to be turned off. The control of the switch 22 is performed in the same manner as the switches 19a and 19b.
For example, this is performed by the successive approximation register and the control logic circuit 2 of the A / D converter shown in FIG.

Hereinafter, the operation of the chopper type comparator 3b of this embodiment will be described. In the first stage comparator, as described above, the switches 15a, 19a and 19b are controlled to be conductive, and the cache memory 13
a and 13b are precharged. At the same time, 2
In the comparator 20 at the stage, the switch 22 is controlled to be conductive, and the capacitor 21 is precharged. When the switch 22 is turned on, the node 23
And the output terminal 24 is held at the same potential, for example, it is held at an intermediate voltage V _CC / 2 supply voltage V _CC. Further, in the first stage of the comparator, when precharged, the drains of the transistors 11a and 12a - assuming source voltage are equal, the intermediate voltage V of the output terminal 18 of the first stage of the comparator power supply voltage V _{CC Held at CC} / 2. The capacitor 21 is precharged according to the voltage at the output terminal 18 and the node 23 of the first-stage comparator.

Next, after precharging, in the first stage comparator, the switches 15a, 19a and 19b are turned off and the switch 15b is turned on. In response to this, the input voltage V _i is applied to the node 9, the transistors 11a and 12a by capacitive coupling of capacitor 13a and 13b
Are respectively controlled. (V _i -V _ref)
, The output voltage V _out1 of the first-stage comparator is controlled. Here, ideally, the output voltage V _out1 of the first-stage comparator is held at either the power supply voltage V _CC or the common potential V _SS . However, in practice for example, if the input voltage V _i and the reference voltage V _ref is only a slight difference, the amplitude of the output voltage V _out1 is reduced. Therefore, in the present embodiment, the second-stage comparator 20 is provided to further amplify the output voltage V _out1 of the first-stage comparator.

In the second stage comparator 20, as described above, the capacitor 13a of the first stage comparator
And 13b are precharged, the switch 22
Turns on, the node 23 and the output terminal 24 become the same potential,
The capacitor 21 is precharged. During precharge, the output terminal 18 of the first stage comparator is
For example, it held in the intermediate voltage V _CC / 2 supply voltage V _CC. Then, after the precharge, depending on the input voltage V _i, the output terminal 18 of the first stage of the comparator is held to a higher or lower voltage than V _CC / 2. Since the output voltage V _out1 of the first stage of the comparator is applied to the node 23 by capacitive coupling of the capacitor 21, from the output terminal 24 of the second stage of the comparator 20, the output voltage V _out1 of the first stage of the comparator The inverted and amplified voltage V _out is output.

As described above, according to the chopper-type comparator 3b of the present embodiment, the second-stage comparator 20 is further connected to the output side of the chopper-type comparator 3a of the first embodiment. Simultaneously with the precharge of the capacitors 13a and 13b of the first stage comparator, the capacitor 21 is precharged. Thereafter, according to the output voltage _Vout1 of the first stage precharge,
The inverted and amplified voltage _Vout is output to the output terminal 24.
As described above, the chopper comparator 3b of the present embodiment
Has the features of the chopper-type comparator 3a of the first embodiment. In addition, by providing a second-stage comparator, the amplitude of the output voltage _Vout can be kept large, and the comparison sensitivity can be further improved.

Third Embodiment FIG. 7 is a circuit diagram showing a chopper type comparator according to a third embodiment of the present invention. As shown, the chopper comparator 3c of the present embodiment is obtained by adding a second-stage comparator 20a to the output side of the chopper comparator 3a of the first embodiment shown in FIG.

As shown in the figure, in the present embodiment, the first-stage chopper-type comparator has substantially the same configuration as the chopper-type comparator 3a of the first embodiment. The same reference numerals as those in FIG. In addition, a detailed description of this portion will be omitted. Hereinafter, the configuration and operation of the second-stage comparator 20a will be mainly described for the chopper-type comparator 3c of the present embodiment.

The second-stage comparator 20a is a pMOS
It is composed of a transistor 11b and an nMOS transistor 12b. Transistors 11b and 12b
Are connected in series between the supply line of the power supply voltage V _CC and the common potential V _SS, and the gates of these transistors
And the connection point between the drains is connected to the output terminal 24. That is, the second-stage comparator 20a
It is constituted by a linear amplifier composed of a CMOS inverter. The input terminal of the linear amplifier, that is, the node 23 is connected to the output terminal 18 of the first-stage comparator.

Hereinafter, the operation of the chopper type comparator 3c of this embodiment will be described. First, in the first-stage comparator, the switches 15a, 19a and 19b are controlled to be conductive, and the cache memories 13a and 13b
b is precharged. Then, in the first-stage comparator, the switches 15a, 19a and 19b are controlled to open and the switch 15b is controlled to conduct. In response to this, the input voltage V _i is applied to the node 9, the gate voltage of the transistor 11a and 12a are respectively controlled by capacitive coupling of capacitor 13a and 13b, (V
The output voltage V _out1 of the first-stage comparator is controlled according to ( _i− V _ref ).

The output voltage V of the first stage comparator
_out1 is input to the second-stage comparator 20a. 2
The inverted and amplified voltage _Vout is output by the comparator 20a at the stage.

As described above, in the chopper type comparator 3c of the present embodiment, the second stage comparator 20a is connected to the output side of the first stage comparator, and the output voltage V _out1 of the first stage is further inverted and amplified. The output voltage _Vout is output. For this reason, the chopper comparator 3c of the present embodiment is different from the chopper comparator 3c of the first embodiment.
In addition to having the characteristic of a, by providing the second-stage comparator, the amplitude of the output voltage _Vout can be kept large, and the comparison sensitivity can be further improved.

The chopper type comparator according to the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist of the present invention.

[0053]

According to the chopper type comparator of the present invention and the successive approximation type A / D converter to which the chopper type comparator is applied,
Since the gate bias voltages of the pMOS transistor and the nMOS transistor constituting the linear amplifier in the chopper type comparator are controlled independently, when the standby state or the capacitor is precharged,
Through current flowing through the transistor of the linear amplifier can be suppressed low, and power consumption can be reduced. Further, since the voltage gain of the linear amplifier does not depend on the power supply voltage and can maintain a high gain, a high detection sensitivity of the chopper type comparator can be realized over a wide range of the power supply voltage. The D converter can provide an excellent effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a chopper type comparator according to the present invention.

FIG. 2 is a circuit diagram showing a gate bias circuit of the chopper type comparator shown in FIG.

FIG. 3 is a graph showing a relationship between a gate voltage V _g and a drain-source current I _ds of a pMOS transistor and an nMOS transistor.

FIG. 4 is a timing chart showing an operation of a switch of the chopper type comparator shown in FIG.

FIG. 5 is a graph showing input / output transfer characteristics of the chopper comparator shown in FIG.

FIG. 6 is a circuit diagram showing a chopper type comparator according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a chopper type comparator according to a third embodiment of the present invention.

FIG. 8: Successive approximation type A using a chopper type comparator
FIG. 3 is a block diagram illustrating a configuration of a / D converter.

9 is a flowchart showing the operation of the successive approximation A / D converter shown in FIG.

FIG. 10 is a circuit diagram showing a conventional chopper type comparator.

11 is a timing chart showing the operation of the switch of the chopper type comparator shown in FIG.

FIG. 12 is a diagram illustrating the operation principle of a conventional chopper type comparator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... D / A converter, 2 ... Sequential comparison register and control logic circuit, 3, 3a, 3b ... Comparator, 4 ... Analog switch group, 5 ... Series resistor circuit, 6 ... Latch and buffer circuit, 9 ... Input node , 10, 10a ... linear amplifier, 11, 11a, 11b ... p-channel transistor, 12, 12a, 12b ... n-channel transistor,
13, 13a, 13b ... capacitor, 14, 14a, 1
4b: gate bias circuit, 15a, 15b: switch, 16a: input terminal to which a reference signal is input, 16b:
Input terminals for inputting input signals, 17a, 17b: bias voltage output terminals, 19, 19a, 19b, 19c: switches, 20, 20a: second-stage comparator, 21: capacitors, 22: switches, 30, 31, 32 , 33,
34, 35, 36 ... transistor, V _CC ... the power supply voltage, V
_SS ... common potential.

Claims (10)

[Claims] 1. A chopper type comparator for comparing an input signal and a reference signal, comprising: a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential; A first capacitor connected between the gate of the first p-channel transistor and an input node; a second capacitor connected between the gate of the first n-channel transistor and the input node; A first switch connected between a first input terminal to which a reference signal is input and the input node; and a first switch connected between a second input terminal to which the input signal is input and the input node 2 switches; a first gate bias voltage applied to the gate of the first p-channel transistor; and a gate of the first n-channel transistor. A gate bias voltage generating circuit for generating a second gate bias voltage to be applied; turning on the first switch, and applying the first and second gate bias voltages to the gate of the first p-channel transistor and the After applying the voltage to the gate of the n-channel transistor and precharging the first and second capacitors, the application of the first and second gate bias voltages is stopped, and the first switch is turned off. The second switch is turned on, and the first and second switches are turned on.
And a control circuit that applies a signal corresponding to a difference between the input signal and the reference signal to the gates of the first p-channel transistor and the first n-channel transistor by capacitive coupling of the capacitor. 2. The gate bias voltage generation circuit generates a voltage substantially lower than the power supply potential by an absolute value of a threshold voltage of the first p-channel transistor as the first bias voltage, and generates the reference potential. More nearly the first n
2. The chopper-type comparator according to claim 1, wherein a voltage higher by a threshold voltage of the channel transistor is generated as the second bias voltage. 3. The gate bias voltage generation circuit according to claim 2, wherein the second p-channel transistor, the third switch, and the second switch are connected in series between the power supply potential and the reference potential.
An n-channel transistor, a fourth switch connecting the gate and the drain of the second p-channel transistor, and connected between the connection point and the gate of the first p-channel transistor, a fifth switch that connects a gate and a drain of the n-channel transistor and that is connected between the connection point and the gate of the first n-channel transistor; 2. The chopper type according to claim 1, wherein the first and second gate bias voltages are applied to the gates of the first p-channel transistor and the first n-channel transistor, respectively, in a state where the fifth switch is turned on. comparator. 4. A chopper type comparator for comparing an input signal with a reference signal, comprising: a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential; A first capacitor connected between the gate of the first p-channel transistor and an input node; a second capacitor connected between the gate of the first n-channel transistor and the input node; A first switch connected between a first input terminal to which a reference signal is input and the input node; and a first switch connected between a second input terminal to which the input signal is input and the input node 2 switches; a first gate bias voltage applied to the gate of the first p-channel transistor; and a gate of the first n-channel transistor. A gate bias voltage generating circuit for generating a second gate bias voltage to be applied; a second p-channel transistor and a second n-channel transistor connected in series between the power supply potential and the reference potential; Are connected to the first p-channel transistor and the first
A third capacitor connected to a connection midpoint between the second p-channel transistor and the gate of the second n-channel transistor; and a third capacitor connected to a connection point between the gates of the second p-channel transistor and the second n-channel transistor. The terminal is connected to the second p-channel transistor and the second
A third switch, which is connected to a connection point between the gates of the n-channel transistors of the above, and the other terminal of which is connected to a connection point between the second p-channel transistor and the second n-channel transistor; Are turned on to apply the first and second gate bias voltages to the gates of the first p-channel transistor and the first n-channel transistor, respectively, thereby pre-charging the first and second capacitors. After charging, further turning on the third switch, and precharging the third capacitor.
And stopping the application of the second gate bias voltage, turning off the first and third switches, turning on the second switch, and coupling the input signal by the capacitive coupling of the first and second capacitors. A signal corresponding to a difference between the first p-channel transistor and the first p-channel transistor.
And a control circuit for applying a voltage to the gate of the n-channel transistor. 5. The gate bias voltage generation circuit generates a voltage substantially lower than the power supply potential by an absolute value of a threshold voltage of the first p-channel transistor as the first bias voltage, and generates the reference potential. More nearly the first n
5. The chopper type comparator according to claim 4, wherein a voltage higher by a threshold voltage of the channel transistor is generated as the second bias voltage. 6. A chopper type comparator for comparing an input signal with a reference signal, comprising: a first p-channel transistor and a first n-channel transistor connected in series between a power supply potential and a reference potential; A first capacitor connected between the gate of the first p-channel transistor and an input node; a second capacitor connected between the gate of the first n-channel transistor and the input node; A first switch connected between a first input terminal to which a reference signal is input and the input node; and a first switch connected between a second input terminal to which the input signal is input and the input node 2 switches; a first gate bias voltage applied to the gate of the first p-channel transistor; and a gate of the first n-channel transistor. A gate bias voltage generation circuit for generating a second gate bias voltage to be applied; a gate connected to the gate; a connection point connected to a connection midpoint between the first p-channel transistor and the first n-channel transistor; A second p-channel transistor and a second n-channel transistor connected in series between the power supply potential and the reference potential; turning on the first switch; and providing the first and second gates After applying a bias voltage to the gate of the first p-channel transistor and the gate of the first n-channel transistor, respectively, and precharging the first and second capacitors, the first and second gate bias voltages are applied. Is stopped, the first switch is turned off, the second switch is turned on, and the first and second switches are turned off.
And a control circuit that applies a signal corresponding to a difference between the input signal and the reference signal to the gates of the first p-channel transistor and the first n-channel transistor by capacitive coupling of the capacitor. 7. The gate bias voltage generation circuit generates a voltage substantially lower than the power supply potential by an absolute value of a threshold voltage of the first p-channel transistor as the first bias voltage, and generates the reference potential. More nearly the first n
7. The chopper-type comparator according to claim 6, wherein a voltage higher by a threshold voltage of the channel transistor is generated as the second bias voltage. 8. An A / D converter for outputting an n-bit digital signal according to a voltage of an input signal, wherein the A / D converter converts an input digital signal into an analog signal.
A / A converter, a chopper type comparator that compares the output signal of the D / A converter with the input signal as a reference signal, and, from the most significant bit of the n-bit digital signal, according to the output signal of the chopper type comparator A bit determination circuit for sequentially determining the least significant bit and outputting the n-bit digital signal to the D / A converter, wherein the chopper type comparator is connected in series between a power supply potential and a reference potential. A first p-channel transistor and a first n-channel transistor, a first capacitor connected between a gate of the first p-channel transistor and an input node, and a gate of the first n-channel transistor. A second capacitor connected between the input nodes; and a second capacitor to which the reference signal is input. A first switch connected between the first input terminal and the input node; a second switch connected between a second input terminal to which the input signal is input and the input node; A gate bias voltage generating circuit for generating a first gate bias voltage applied to the gate of one p-channel transistor and a second gate bias voltage applied to the gate of the first n-channel transistor; and the first switch Was turned on, and the first and second gate bias voltages were applied to the gate of the first p-channel transistor and the gate of the first n-channel transistor, respectively, to precharge the first and second capacitors. Then, the application of the first and second gate bias voltages is stopped, the first switch is turned off, and the second switch is turned off. Was turned on, the first and second
An A / D converter having a control circuit for applying a signal corresponding to a difference between the input signal and the reference signal to the gates of the first p-channel transistor and the first n-channel transistor by capacitive coupling of the capacitor . 9. The gate bias voltage generation circuit generates a voltage substantially lower than the power supply potential by an absolute value of a threshold voltage of the first p-channel transistor as the first bias voltage, and generates the reference potential. More nearly the first n
9. The A / D converter according to claim 8, wherein a voltage higher by a threshold voltage of the channel transistor is generated as the second bias voltage.
D converter. 10. The gate bias voltage generation circuit, comprising: a second p-channel transistor, a third switch, and a second n-channel transistor connected in series between the power supply potential and the reference potential; A fourth switch connecting the gate and the drain of the second p-channel transistor, connected between the connection point and the gate of the first p-channel transistor, and the gate and the drain of the second n-channel transistor And a fifth switch connected between the connection point and the gate of the first n-channel transistor. The control circuit turns on the third, fourth, and fifth switches. The first and second gate bias voltages are applied to the first p-channel transistor and the first n-channel transistor, respectively. A / D converter according to claim 8 applied to the gate.