JP2003163843A - Image read signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a conventional image read signal processor employing sample-hold circuits provided in duplicate has brought about occurrence of a periodic noise resulting from a difference between output levels caused when there exists a difference between voltages charged up across two capacitors 44, 44B for canceling offset voltages of operational amplifiers. <P>SOLUTION: In configuring the sample-hold circuits in duplicate for the image read signal processor, an operational amplifier 64 provided with a capacitor 67 for canceling an offset voltage is placed at the input of the sample-hold circuits, and then the sample-hold core circuits 69, 70 having sample-hold capacitors 73, 74 or the like are connected in parallel next to the input operational amplifier 64, and each output of the sample-hold core circuits 69, 70 is negatively fed back to the operational amplifier 64 through the offset voltage canceling capacitor 67. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading signal processing apparatus which amplifies an image signal read by an image sensor and then samples and holds the amplified output.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an entire image reading signal processing apparatus for time-sequentially extracting a plurality of image reading signals from an image sensor. In FIG. 4, 30 is an image sensor, 31A to 31M are dual correlation sampling circuits, 32A to 32M are sample and hold circuits, and 33A to 33A.
33M is a switch, 34 is a buffer, 35 is an output terminal,
A, B, and M are processing channels for one image reading signal.

Double correlation sampling circuits 31A-31M
Input the input bias voltage existing in a parasitic capacitance (not shown) on the input side before the image read signal is input from the image sensor 30, and then the image read signal is superimposed on the input bias voltage. It is a circuit for obtaining an output, when only an object is inputted, by amplifying only an amount (that is, an image reading signal) obtained by subtracting the previously inputted input bias voltage. The sample hold circuits 32A to 32M are
This is a circuit for holding the outputs of the double correlation sampling circuits 31A to 31M.

Taking the processing channel A as an example, first, an input signal (image reading signal) from a certain image reading element of the image sensor 30 is supplied to the double correlation sampling circuit 3.
It is amplified by 1 A and held by the sample hold circuit 32 A. In this way, the image sensor 3 is connected to the sample hold circuits 32A to 32M of the respective processing channels A to M.
The amplified output of the image reading signal from each image reading element of 0 is held, but when the switches 33A to 33M are sequentially turned on and taken out to the output terminal 35 via the buffer 34, the time-series signals in one column are obtained. Become.

The time-sequential signal is required to be continuously output as much as possible without a rest period. This is because if there is a rest period, it is necessary to control so that the next circuit will not take in data during the rest period, which makes the control troublesome. Also, if the pause period is provided, the clock frequency during the output period must be increased, and then it becomes necessary to widen the frequency band of the buffer at the final stage.

However, when trying to output continuously,
Problems occur in the sample hold circuit. This is because the sample-hold circuit cannot hold the next sampled data while outputting the held data. Therefore, if the same control signal is used to control sampling and sample hold in each processing channel, the output must be stopped during sampling. In order to avoid such a situation, it is considered that the sample hold circuit of each processing channel is duplicated. Hereinafter, the double correlation sampling circuit and the sample hold circuit will be described in order.

(Double Correlation Sampling Circuit) FIG. 2 is a diagram showing an example of a conventional double correlation sampling circuit.
In FIG. 2, 1 is an image sensor, 2 is a photodiode, 3 is a bias power source, 4 is a capacitor, 5 is a TFT (thin film transistor), 6 is a capacitor, 7 is an input signal line, 8 is a double correlation sampling circuit, and 9 is Reset switch, 10 is an input bias power supply, 11 is an operational amplifier, 12 is a switch, 13 and 14 are capacitors, 15 is a low-pass filter, 16 is a resistor, 17 is a capacitor, 18 is a buffer,
Reference numeral 19 is a DC regeneration capacitor, 20 is a switch, 21 is an output reference power source, 22 is a buffer, 23 is an output terminal, 24
Is a drive pulse generator.

The image sensor 1 is provided with a photodiode 2 having a cathode connected to the positive electrode of the bias power source 3 and an anode connected to the drain of the TFT 5, which detects light. Although only one photodiode 2 is drawn, many photodiodes 2 are actually provided. The capacitance 4 drawn on the anode of the photodiode 2 represents the total capacitance of the self capacitance of the photodiode 2 and the drain side parasitic capacitance of the TFT 5. Further, in the TFT 5, as indicated by the dotted line, there is a small amount of capacitance generated due to overlap with the gate between the gate and the drain D and between the gate and the source S. .
The capacitance 6 represents the total capacitance of the source-side parasitic capacitance of the TFT 5 and the input capacitance of the double correlation sampling circuit 8 composed of an IC.

The double correlation sampling circuit 8 is constructed as an IC, and each switch therein is an analog switch. The drive pulse generator 24 generates a pulse for controlling ON / OFF of the TFT 5 and each switch. An input bias power supply 10 is connected to the input signal line 7 via a reset switch 9. The operational amplifier 11 includes a switch 12 and a capacitor 13 as a negative feedback circuit,
When the switch 12 is turned on, the buffer (gain 1
When the switch 12 is turned off,
It operates as a gain amplifier determined by the capacitance ratio of the capacitors 14 and 13. The negative feedback circuit is duplicated
This is because the operational amplifier 11 performs double correlation sampling.

That is, first, the input bias voltage is input (first sampling), then the input bias voltage superposed with the image reading signal is input (second sampling), and the difference is amplified. To do.

(1) When the reset switch 9 is turned on for a certain period while the input TFT 5 for input bias voltage is turned off, the capacitor 6 is charged by the input bias power source ₁₀ and becomes the input bias voltage V ₁₀ . When the reset switch 9 is turned off and then the switch 12 is turned on, the operational amplifier 11 operates as a buffer, and its output voltage becomes a voltage obtained by adding the offset of the operational amplifier 11 itself to the input bias voltage V ₁₀ . The capacitor 14 at the inverting input terminal is charged to the same voltage by negative feedback. If the offset of the operational amplifier 11 itself is sufficiently small as compared with V ₁₀ , it can be ignored, so that the charging voltage of the capacitor 14 is equal to the input bias voltage V ₁₀ .

The output V _{10 of the} operational amplifier 11 is applied to the DC reproducing capacitor 19 via the low pass filter 15 and the buffer 18. At this time, the switch 20 is also turned on, and the output reference power source 21 is applied from the direction opposite to the DC reproducing capacitor 19. When the voltage of the output reference power source 21 is V ₂₁ , the voltage V ₁₀ -V ₂₁ is charged between the plates of the DC regeneration capacitor 19. After this, the switch 20 is turned off.

The low-pass filter 15 is provided to reduce noise. The cut-off frequency of the amplifier fluctuates somewhat due to manufacturing variations, parasitic capacitance, etc., so it is generally designed to have a larger margin than the specification. The operational amplifier 11 is also usually designed in that way. Therefore, noise outside the required band is also amplified, and it is necessary to reduce them.

The buffer 18 is provided to increase the impedance on the input side as viewed from the low pass filter 15 and to reduce the impedance on the output side as viewed from the DC reproducing capacitor 19. If buffer 18
Without it, the DC regeneration capacitor 19 is connected as the load of the low-pass filter 15, which may lower the cutoff frequency of the low-pass filter 15 and narrow the frequency band.

(2) A current flows according to the amount of light incident on the input photodiode 2 of the input bias voltage + the input signal, the capacitor 4 is charged, and this becomes the image reading signal ΔV. When the TFT 5 is turned on, the voltage V _{10 of the} capacitor 6 on which the image reading signal ΔV is superimposed is input to the operational amplifier 11. The amplification factor A ₁₁ of operational amplifier 11 if 100
If doubled, the output voltage becomes V ₁₀ + 100 × ΔV.

This is applied to the DC reproducing capacitor 19 via the low pass filter 15 and the buffer 18. The DC regeneration capacitor 19 has a voltage (V ₁₀ −
Since the voltage of V ₂₁ ) is charged, the voltage obtained by subtracting the voltage, that is, (V ₁₀ + 100 × ΔV) − (V ₁₀ −V ₂₁ ) = 100 × Δ
A voltage of V + V ₂₁ will be applied to the input of the buffer 22. Therefore, the output obtained at the output terminal 23 is 100 ×
It is ΔV + V ₂₁ .

FIG. 3 is a time chart in the image reading signal processing apparatus. The waveform of the solid line is the waveform when dark (when no light is incident), and the waveform of the one-dot chain line is the waveform when light is incident. The operation will be described below in time.

(1) From time t _{1 to} t ₂ time t ₁ , as shown in FIG. 3B, when the TFT gate drive signal is turned on, the gate signal leaks from the gate to the drain or the source. The feedthrough phenomenon occurs. The leaked signal (charge) causes the capacitance 6
The charging voltage of will rise accordingly. The fact that the waveform in FIG. 3C rises at time t ₁ like the waveform c-1 indicates the voltage (feedthrough voltage). When dark, the input is only the feedthrough voltage, but when light is incident, the input signal ΔV is superposed on the input signal ΔV to form a waveform indicated by a chain line.

The operational amplifier 11, including the feedthrough voltage, amplifies as shown in FIG. 3 (d). The output of the low-pass filter 15 to which the amplified output is input is shown in FIG.
As shown in (e), the output value of the operational amplifier 11 rises with a time constant.

(2) During the time t _{2 to} t ₄ time t ₂ , when the TFT gate drive signal is turned off as shown in FIG.
Since the same amount of electric charge as that leaking into the capacitor 6 leaks when turned on, the potential of the input signal line 7 is a voltage (feedthrough voltage) corresponding to the leaked electric charge, as shown in FIG. 3C. Only drops. The output waveform of the operational amplifier 11 also drops correspondingly. The output of the low pass filter 15 is
From the high value including the amplified value of the feedthrough voltage, the value decreases in accordance with the time constant toward the output value of the operational amplifier 11 that has disappeared.

The output from the output terminal 23 of FIG. 2 is sent to and held by a sample hold circuit (not shown). When sampled at the time t ₃ between time t ₂ ~t _4, obtained a value corresponding to the output E ₁ in the dark, when the light incidence has a value corresponding to the output E ₂ is obtained.

(3) Time t _{4 When the} reset switch 9 is turned on at time t ₄ , the input on the input signal line 7 is reset.

(Sample and Hold Circuit) FIG. 6 shows a conventional example in which the sample and hold circuit is doubled. In FIG. 6, 40 is a first sample and hold circuit, 41 is a second sample and hold circuit, 42 is an operational amplifier, 43 is a switch, 44 and 44B are capacitors, 45 and 46 are switches, 47 is a switch, 48 is a capacitor, 49 and 50 are switches, 51 is an operational amplifier, and 52 is an output terminal.
Each switch is composed of an analog switch such as a MOSFET.

The inverting input terminal (-) of the operational amplifier 42 is
It is connected to the output terminal of the operational amplifier 42 via the switch 43, and is also connected to a fixed potential (earth) via a circuit in which a capacitor 44 and a switch 45 are connected in this order.
The connection point between the capacitor 44 and the switch 45 is connected to the output terminal of the operational amplifier 42 via the switch 46. The output of the operational amplifier 42 is connected to the sample-hold capacitor 48 via the switch 47, and the connection point between them is connected to the input of the operational amplifier 51 via the switch 49. The operational amplifier 51 has an output terminal and an inverting input terminal (−) connected to each other and is operated as a buffer. The second sample and hold circuit 41 has the same configuration as the first sample and hold circuit 40.

The operation of the first sample and hold circuit 40 is as follows. The output from the double correlation sampling circuit is input to the input terminal 39. When only the input bias voltage is input to the double correlation sampling circuit, the switches 43 and 45 are turned on and the switches 46 and 47,
Turn off 49. Then, the operational amplifier 42 has 1
Since the negative feedback of 00% is applied, it operates as a buffer, and when the input bias voltage is V _i and the offset voltage of the operational amplifier 42 itself is V _io , the non-inverting input terminal (+).
A voltage having the same magnitude as V _i + V _io input to the above appears at the output of the operational amplifier 42. The capacitor 44 is charged to its voltage (V _i + V _io ).

Next, with the switches 43 and 45 turned off, the switches 46 and 47 turned on, and the switch 49 turned off, the output V _S from the double correlation sampling circuit when the image reading signal is input is input. Input to the terminal 39. Then, the input becomes V _S + V _i + V _io . When the output voltage of the operational amplifier 42 at this time is V _42, the charging voltage of the capacitor 44 to _{V 42 (V i + V io} ) the voltage obtained by adding (V ₄₂ + V
_i + _Vio ) is input to the inverting input terminal (-). The operational amplifier 42 operates so that the following equation is established. V _S + V _i + V _io = V ₄₂ + V _i + V _io Therefore, V ₄₂ = V _S , and when the switch 47 is turned on, the input signal V _S is charged in the capacitor 48 and sample-held.

The held voltage is taken out to the output terminal 52 via the operational amplifier 51 when the switch 49 is subsequently turned on. While the first sample hold circuit 40 is outputting, the second sample hold circuit 41 can be operated to hold the next data.

Note that, as conventional documents relating to the image reading signal processing device, there are, for example, JP-A-62-185458 and JP-A-62-135775.

[0029]

However, the above-mentioned conventional technique has the following problems. That is, when the sample and hold circuit is doubled, two capacitors 4 for canceling the offset voltage of the operational amplifier are provided.
If there is a difference in the voltage charged in 4, 44B, a difference in the output level will appear due to the difference, but it will be a periodic noise.

Specifically, in the sample-and-hold circuit according to the conventional example of FIG. 6, the sample-and-hold circuits from the same image sensor element are provided in duplicate and the signals are alternately input to them. Although capacitors 44 and 44B for canceling the offset of the operational amplifier are provided, the offset is not completely canceled because of parasitic capacitance (not shown). If there is a difference in the voltages that are not canceled by the two sample-hold circuits, the differences are alternately reflected in the output, and thus periodic noise occurs.

An object of the present invention is to solve the above problems.

[0032]

In order to solve the above problems, in the image reading signal processing apparatus according to the present invention, an output reference power source is connected to a non-inverting input terminal to which a signal is input via a first switch 62. A second switch is connected between the inverting input terminal and the output terminal, and a first capacitor and a third switch are connected in this order between the inverting input terminal and the output reference power source. First and second operational amplifiers, which are provided in the next stage of the first operational amplifier, are connected in parallel to each other, and are operated alternately, and which have a sample-hold switch, a sample-hold capacitor, and a buffer-connected operational amplifier. Between the second sample-and-hold main circuit, the output terminals of the first and second sample-and-hold main circuits, and the connection point between the first capacitor and the third switch. And it has a configuration having a sample-and-hold circuit and a negative feedback circuit formed by a switch, respectively.

In the image reading signal processing apparatus having the above structure, when constructing a double sample and hold circuit, one operational amplifier having a capacitor for offset voltage cancellation is arranged on the input side, and then, for sample and hold. Two sets of sample-and-hold main circuits are configured by connecting two sets of sample-and-hold main circuits having capacitors and the like in parallel, and negatively feeding back each output of these sample-and-hold main circuits through a capacitor for offset voltage cancellation. Are used alternately, whichever is used, the same offset voltage canceling capacitor cancels. Therefore, the problem that periodic noise is generated due to the difference in voltage of the canceling capacitor cannot occur.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration example of a double sampling and holding circuit used in an image reading signal processing apparatus according to an embodiment of the present invention. In FIG. 1, 60
Is an input terminal, 61 is a capacitor, 62 is a switch, 63
Is an output reference power source, 64 is an operational amplifier, 65 is a switch,
66, 67 are capacitors, 68 are switches, 69, 70
Is a sample hold main circuit, 71 and 72 are switches,
73 and 74 are capacitors, 75 and 76 are operational amplifiers, 7
Reference numerals 7 to 80 are switches, and 81 is an output terminal.

An output reference power supply 63 is connected to the non-inverting input terminal of the operational amplifier 64 via a switch 62, a switch 65 is connected between the inverting input terminal and the output terminal, and the inverting input terminal and the output reference are connected. A capacitor 66 and a switch 68 are connected in this order between the power source 63 and the power source 63. To the next stage of the operational amplifier 64, two sets of sample hold main circuits 69 and 70 which are connected in parallel with each other and are operated alternately are connected.

The sample-and-hold main circuits 69 and 70 are
Each is composed of sample and hold switches 71 and 72, sample and hold capacitors 73 and 74, and buffer-connected operational amplifiers 75 and 76. Then, switches 77 and 78 are respectively provided between the output terminals of the sample hold main circuit 69 and 70 and the connection point of the capacitor 66 and the switch 68 to form a negative feedback circuit.

As the operational amplifier 64, a normal operational amplifier composed of two amplification stages, a differential amplification stage and an output amplification stage, is used. On the other hand, as the operational amplifiers 75 and 76,
It is desirable to use an operational amplifier consisting of only a differential amplification stage. The reason will be explained later.

The capacitor 61 corresponds to the DC reproducing capacitor 19 of FIG. 2, and the output reference power supply 63 corresponds to the output reference power supply 21. When the output reference voltage is input,
The switches 62, 65, 68 are turned on. Operational amplifier 6
The voltage V ₆₃ of the output reference power source ₆₃ is applied to the non-inverting input terminal of No. 4, and the capacitor 66 is charged with the offset voltage of the operational amplifier 64. After that, the switch 65 is turned off first, and then the switches 62 and 68 are turned off. The reason why the switch 65 is turned off first is to prevent the value of the offset voltage of the operational amplifier 64 charged in the capacitor 66 from changing, as described below.

FIG. 5 shows the parasitic of the charging voltage of the capacitor 66.
Capacity C_SIt is a figure explaining the change by. In an integrated circuit
When capacitors 66 and 67 are formed, the connection point between them
N is on the silicon substrate side, but its connection point N and fixed potential
Between the large parasitic capacitance C_SExists. Sanawa
The terminal on the connection point N side of the capacitor 66 has a parasitic capacitance C
_SIs connected to a fixed potential. Toko
So that the charging voltage of the capacitor 66 does not change.
In order to make it difficult for the electric charge to discharge
However, for that purpose, the switch is turned off and
A high impedance may be connected.

The switches existing on both sides of the capacitor 66 are 65 and 68. If the switch 68 is turned off first, one terminal of the capacitor 66 is connected to the switch 65 which is on. The other terminal is connected to the fixed potential via the parasitic capacitance C _S.
The parasitic capacitance C _S is not high impedance. This may change the charging voltage of the capacitor 66. If the switch 65 is turned off first, a high impedance is connected to the terminal connected to the inverting input terminal (-) of the operational amplifier 64 among the terminals of the capacitor 66, so that the capacitor 66 is charged. The voltage does not change.

Returning to FIG. 1, when the switch 71 of the first sample hold circuit 69 is turned on, the capacitor 73 is charged by the output of the operational amplifier 64. When the switch 71 is turned on, the switch 77 is also turned on, and the output of the operational amplifier 75 passes through the capacitor 66 and the operational amplifier 6
Negative feedback to 4. The operational amplifier 64 is used for the capacitor 66.
Since the offset voltage is charged, the offset voltage is canceled and the output of the operational amplifier 75 becomes a voltage corresponding to the non-inverting input terminal of the operational amplifier 64. When the switches 71 and 77 are turned off, the voltage of the capacitor 73 is held. The voltage that is held is the switch 7
When 9 is turned on, it is taken out to the output terminal 81.

Next, the second sample hold circuit 70 is used. At this time, the output of the operational amplifier 76 is also negatively fed back through the capacitor 66 by the same operation. As described above, in the sample hold circuit of FIG. 1, since the operational amplifier in the previous stage is commonly used, there is no difference in the influence of the offset voltage when operating the first and second sample hold main circuits.

By the way, the operational amplifier 64 and the operational amplifier 7
5, 76 are connected in cascade, but if an ordinary operational amplifier having two amplification stages is used as an operational amplifier connected in cascade, negative feedback is applied to all of them (switch 7
7), the state approaches an oscillating state due to the input / output propagation delay. Further, if a normal operational amplifier having two amplification stages and a large gain is used with a gain of 1, a large phase compensation capacitor is required, but if it is formed on an integrated circuit, it occupies a large area, This leads to increased costs and is not desirable.

Therefore, the operational amplifiers 75 and 76 which are always used as buffers are composed of only differential amplifier stages. Then, the above-mentioned input / output propagation delay is alleviated, and a large phase compensation capacitor is not required.

When the offset voltage canceling capacitor 66 is connected to the operational amplifier 64, it is desirable to connect the capacitor 67 to the capacitor 66 in series so as to form a negative feedback path from the output terminal of the operational amplifier 64. The reason for doing this is that the negative feedback is performed via the capacitors 66 and 67 even when the switch 65 is turned off or when there is no negative feedback via the switches 77 and 78. Is.

If this negative feedback is not provided, the output of the operational amplifier 64 becomes maximum (power value of the operational amplifier), and the power supply current may fluctuate greatly. The fluctuation of the power supply current adversely affects other circuits (not shown) connected to the operational amplifier 64 on the integrated circuit. However, if the negative feedback path is secured by the capacitors 66 and 67, such a thing can be prevented.

In the sample and hold circuit of FIG. 1, the double sample and hold main circuits 69 and 70 are provided with sample and hold switches 71 and 72, respectively, but the size of the switching noise generated by them is different. If so, each time the above two sample-hold circuits are used alternately, the difference in size will alternately appear in the output. Therefore, when forming the switches 71 and 72 as analog switches on the integrated circuit, it is necessary to form them so that they have the same characteristics as much as possible. For that purpose, it is desirable to form them adjacently on the integrated circuit.

FIG. 7 is a time chart of the circuit of the present invention in which the sampling and holding circuit is doubled. The horizontal axis is time, and ΔV is the magnitude of the image reading signal.
7A shows the input to the input terminal 60, and FIG. 7B shows the input to the operational amplifier 64. Although there is no input signal (image reading signal) at the beginning, the input is made after the time t _10. It has been done. With no input signal, the switch 62 is first turned on at time t ₀ and the voltage of the output reference power supply 63 is applied.

Next, at time t ₁ , the switches 65 and 68 are turned on to charge the capacitor 66 with the offset voltage of the operational amplifier 64. After this, the three switches 62, 65,
68 is turned off. First, the switch 65 is turned off at time t ₂ , and then the other two switches 6 are turned on at time t _3.
Turn off 2,68. The reason is that the charging voltage of the capacitor 66 is not changed, as described above.

Next, at time t ₄ , the sample-hold switch 71 and the negative feedback switch 77 corresponding to the sample-hold main circuit 69 on the currently used side are turned on. The output of the operational amplifier 64 in this state is the capacitor 7
Holds at 3. The operation up to this point is one cycle, but the operation for inputting the image reading signal ΔV is similarly performed in the cycle starting from time t ₇ .

FIG. 8 is a diagram showing a specific circuit of the first-stage amplifier (operational amplifier 64) in the doubled sampling and holding circuit. In FIG. 8, 90 is a power supply line, 91 is a constant current control signal terminal, 92 is a clipping voltage terminal, 93 is a non-inverting input terminal, 94 is a differential amplification stage, 95 is an inverting input terminal, 96 is an output signal line, and 97. Is an output clipping transistor, 98 is an output amplification stage, 99 and 100 are output MOSFETs, 101 is an output terminal, V _DD is a power supply voltage, and GND is a fixed potential.

The output of the differential amplification stage 94 is the output signal line 96.
Is transmitted to the output amplification stage 98 by the MOSFET 100
And the output is taken out from the output terminal 101.
This is the output of the operational amplifier 64. MOSFET 99
Is saturated and supplies a constant current, MOSFET1
The ratio of the current I _ds flowing to the MOSFET 100 and the current flowing to the output terminal 101 is changed according to the output voltage of 00.

However, if the potential across the MOSFET 100 becomes so large that the potential across the MOSFET 99 becomes too small to maintain saturation, a constant current can no longer be supplied. Then, the current flowing from the power supply line 90 to this circuit fluctuates greatly, and such fluctuation adversely affects other circuits not shown through the power supply.

The output clipping transistor 97 is provided to prevent such a state. A fixed potential is applied to the gate of the output voltage from the clip voltage terminal 92, and when the potential across the MOSFET 100 rises above a predetermined level, the output clipping transistor 9
A current flows through 7 to stop the rise. This allows the MOSFET 99 to maintain a saturated state and continue to supply a constant current.

FIG. 9 is a diagram showing a specific circuit of the second-stage amplifier (operational amplifiers 75 and 76) in the doubled sample and hold circuit. In FIG. 9, 110 is a constant current control signal terminal, 111 is an input terminal, 112 is a differential amplifier, 113 is a negative feedback circuit, and 114 is an output terminal. It is composed of one stage of a differential amplifier, and is made into a buffer by making the negative feedback circuit 113 into a short circuit.

[0057]

As described above, the image reading signal processing device according to the present invention has the following effects. That is, when configuring a double sample and hold circuit,
One operational amplifier having a capacitor for offset voltage cancellation is arranged on the input side, and then two sets of sample-hold main circuits having sample-hold capacitors and the like are connected in parallel. By negatively feeding back each of the outputs through the offset voltage canceling capacitor, the same offset voltage canceling capacitor cancels whichever sample hold circuit is used. There is no possibility that periodic noise is generated due to.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a dual sampling and holding circuit used in an image reading signal processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional double correlation sampling circuit.

FIG. 3 is a time chart of a conventional double correlation sampling circuit.

FIG. 4 is a diagram illustrating an entire image reading signal processing device that time-sequentially extracts a plurality of image reading signals from an image sensor.

FIG. 5 is a diagram for explaining a change in a charging voltage of a capacitor 66 due to a parasitic capacitance.

FIG. 6 is a diagram showing a conventional example in which a sampling and holding circuit is doubled.

FIG. 7 is a time chart of the circuit of the present invention in which the sampling and holding circuit is doubled.

FIG. 8 is a diagram showing a specific circuit of a first-stage amplifier in a doubled sampling and holding circuit.

FIG. 9 is a diagram showing a specific circuit of a second-stage amplifier in a doubled sampling and holding circuit.

[Explanation of symbols]

1 ... Image sensor, 2 ... Photo diode, 3 ... Bias power supply, 4 ... Capacitance, 5 ... TFT, 6 ... Capacitance, 7 ... Input signal line, 8 ... Dual correlation sampling circuit, 9 ... Reset switch, 10 ... Input bias Power supply, 11 ... operational amplifier, 12 ... switch, 13, 14 ... capacitor, 15 ...
Low-pass filter, 16 ... Resistor, 17 ... Capacitor, 1
8 ... Buffer, 19 ... DC regeneration capacitor, 20 ... Switch, 21 ... Output reference power source, 22 ... Buffer, 23 ...
Output terminal, 24 ... Drive pulse generator, 30 ... Image sensor, 31A to 31M ... Dual correlation sampling circuit, 3
2A to 32M ... Sample and hold circuit, 33A to 33M
... Switches 33, 34 ... Buffers, 35 ... Output terminals, 3
9 ... Input terminal, 40A, 40B ... Double correlation sampling circuit, 41A, 41B ... Sample hold circuit, 42 ...
Operational amplifier, 43 ... switch, 44 ... capacitor, 4
5, 46 ... Switch, 47 ... Switch, 48 ... Capacitor, 49, 50 ... Switch, 51 ... Operational amplifier, 52 ...
Output terminal, 60 ... Input terminal, 61 ... Capacitor, 62 ...
Switch, 63 ... Output reference power source, 64 ... Operational amplifier, 6
5 ... Switch, 66, 67 ... Capacitor, 68 ... Switch, 69, 70 ... Sample hold main circuit, 71, 7
2 ... switch, 73, 74 ... condenser, 75, 76 ...
Operational amplifier, 77 to 80 ... switch, 81 ... output terminal,
90 ... Power supply line, 91 ... Constant current control signal terminal, 92 ...
Clip voltage terminal, 93 ... Non-inverting input terminal, 94 ... Differential amplification stage, 95 ... Inversion input terminal, 96 ... Output signal line, 97
... Output clip transistor, 98 ... Output amplification stage, 9
9, 100 ... MOSFET, 101 ... Output terminal, 110
... constant current control signal terminal, 111 ... input terminal, 112 ... differential amplifier, 113 ... negative feedback circuit, 114 ... output terminal

Claims (4)

[Claims] 1. A first non-inverting input terminal to which a signal is input
An output reference power source is connected via the switch of the second switch, a second switch is connected between the inverting input terminal and the output terminal, and a first capacitor and a third capacitor are connected between the inverting input terminal and the output reference power source. A first sample-hold main part having a first operational amplifier in which a switch is connected in this order, and a sample-hold switch, a sample-hold capacitor, and a buffer-connected operational amplifier which are provided in a stage subsequent to the first operational amplifier. A circuit and a parallel circuit connected to the first sample-and-hold main circuit and having a sample-and-hold switch, a sample-and-hold capacitor, and a buffer-connected operational amplifier, and operate alternately with the first sample-and-hold main circuit. Second
And a switch between the output terminals of the first and second sample-and-hold main circuits and the connection point between the first capacitor and the third switch. An image reading signal processing device having a sample hold circuit including the negative feedback circuit described above. 2. The first operational amplifier includes a second capacitor connected between an output terminal of the first operational amplifier and a connection point between the first capacitor and a third switch. The image reading signal processing device according to claim 1, wherein 3. The second switch includes the first to third switches.
The image reading signal processing apparatus according to claim 1, wherein the switch is turned off first when the switch is turned off from the turned on state. 4. The first operational amplifier has an output clipping transistor for limiting an increase in the output voltage of the first operational amplifier to a predetermined value that does not cause fluctuations in the power supply current. 1. The image reading signal processing device according to 1.