TWI415085B - Transistor circuits and control methods thereof - Google Patents

Abstract

A transistor output circuit and an outputting method thereof are provided to prevent a slow transient response in an output transistor. A transistor circuit includes a first output transistor(10), a second output transistor(12), and a switch device. The switching device couples the output of the first and second output transistors to a common output successively. The first output transistor and the second output transistor provide the output signal to the common output of the transistor circuit. The first output transistor and the second output transistor provide the same output with a stable state. When the output of the first output transistor is coupled to the common output, the switching device is operated so that the change of a driving condition voltage of the first output transistor is disconnected in the second output transistor.

Description

Transistor circuit and transistor circuit control method

The present invention relates to a transistor output circuit, i.e., a circuit having an output transistor for providing a variable output voltage or current over time. An example of such a circuit is a current sampling circuit that provides a current output based on a sensing function.

In some sensing applications, a sensing device (eg, a diode or transistor) produces an output current that is dependent on the parameter to be sensed. There are a wide range of applications in which current sensors can be used, and the invention can be implemented in any application, for example, in the case of a photosensor, the parameter to be sensed can be a light level; or in a temperature sensor In the example, the parameter to be sensed may be temperature. This sensor will measure physical properties such as light, temperature, tension or other forces.

For the quality of the maintenance signal, such as the signal to noise ratio, the output current of the sensor will typically be very small, which facilitates the conversion of the signal into a more robust form of proximity to the sensor. Sampling of current is required where the signal changes over time or when the outputs of multiple sensors are multiplexed (as is the case with a sensor array).

Figure 1 shows a known simple sampling circuit.

For example, the current to be sampled includes a photocurrent, which is represented by current source CS1. This current flows through the P-type drive transistor T1p, which has a capacitor C1 connected between its source and the gate. This electric The container thus stores the gate-source voltage corresponding to the current being sampled.

This circuit has a first switch S1 (controlled at timing Clk1) that is interposed between the gate and drain of transistor T1p to conduct current crystal T1p such that it provides the current being sampled. The second switch S2 (controlled by the timing Clk2) couples the transistor T1p to the current source CS1, and the third switch S3 (controlled by the timing Clk3) couples the transistor T1p to the output terminal OUT of the sampling circuit.

As shown in Fig. 2, during the sampling period S, the switches S1 and S2 are closed and the switch S3 is opened. The current to be sampled (photocurrent in this example) flows through the transistor T1P. The voltage appearing at the gate and drain of the transistor T1p is stabilized by the value of the gate current that produces the transistor T1p, which is equal to the photocurrent. This voltage becomes stored in capacitor C1. During the sustain period H, switches S1 and S2 are open and switch S3 is closed. The gate-to-source voltage of transistor T1p is maintained by capacitor C1, so that the sampled photocurrent is available at the output of this circuit.

The time required to sample this current is proportional to (C1 + Cd) / gm1, where Cd represents the capacitance of the sensor (ie, the photodiode) and gm1 represents the transduction of the transistor Tp1. When the current to be measured is small, the transistor T1p will operate in the secondary threshold region. In this region, the value of gm1 is proportional to the drain current Id1. Therefore, when the current to be sampled is low, the settling time will be prolonged.

Low temperature polysilicon (LTPS) technology provides a complex CMOS circuit integrated into a large area substrate and used to fabricate devices such as active array liquid crystal displays. Integrate the sensor into Displayes have received increasing attention, and therefore, the design of thin film transistor (TFT) circuits from these sensors has become more important. The thin mode die in the circuit from the sensing device is biased close to its threshold voltage, or especially when dealing with very small currents, even in the secondary threshold region as explained above. At these bias conditions, the thin mode electron crystal can reveal some undesired reactions.

When the bias voltage applied to the thin mode transistor changes, the thin film transistor exhibits a current overshoot or undershoot phenomenon. As shown in Fig. 3, it shows how the gate current of the transistor changes when the step voltage is applied to the gate of the transistor. When the gate-source voltage is switched from the first value VGS1 to the second lower value VGS2, the gate current ID of the n-type thin film transistor initially decreases toward a lower level, but increases with time until It reaches a steady state value. When the gate-source voltage is switched from the lower second value VGS2 to the first value VGS1, the gate current ID initially increases toward a higher level, but decreases with time until it reaches a steady state value. This transient current response is due to carrier trapping within the device, and the magnitude of the transient current and the time required for the current to reach its steady state value can significantly affect the circuit performance of the device. As is typical in the case where the device is biased in an analog circuit, this reaction is most pronounced when the thin film transistor is operating in the secondary threshold region but also meaningfully close to the threshold voltage.

The magnitude of the transient current can be more than 50%, and the time required for the current to reach its steady state can be more than 50 ms. This is much slower than other transient current reactions in this circuit, such as reactions from capacitor charging times. Therefore, in electricity In the output of the stream sampling circuit, the transient current response becomes the primary source of error.

Figure 4 shows the measured buckling current transient current response of the n-type low temperature polycrystalline germanium film transistor when the gate-source voltage is ramped from 2.5V to 1.0V at time t=0. The drain current initially drops to approximately 0.5 nA, but rises to 2.3 nA over a period of approximately 30 ms.

In some circuits, these thin film transistors experience significant disturbances in their gate voltages in addition to any changes associated with the signal being processed. An example of this may be that the node must be precharged to a certain voltage level before a signal voltage is applied to or generated on one of the nodes of the circuit. These disturbances trigger the slow transient current shown in Figure 4, which may then produce an error at the output of this circuit.

Not only for current sensing applications, this problem typically occurs when the transistor provides a varying output voltage or current.

The present invention provides a transistor circuit comprising a first output transistor, a second output transistor, and a switch configuration. The first and second output transistors are used to provide an output signal to a common output of the transistor circuit. The switch configuration sequentially couples the output of the first output transistor to the output of the second transistor to the common output, wherein the first and second output transistors are controlled to provide the same steady state output. The switch configuration is adapted to operate such that when the output of the first output transistor is coupled to the common output, the complex change in the drive state voltage of the first output transistor is isolated from the second output transistor.

In one example, the transistor circuit is a current sampling circuit. The first output transistor includes a current sampling transistor for sampling the current. The second output transistor includes a transistor that delivers a current output, and the second output transistor is coupled in parallel with the first output transistor. The transistor circuit further includes a first transistor gate-source capacitor. The switch configuration selectively couples a gate voltage of the first output transistor to a gate of the second output transistor. The switch configuration includes a coupling switch that opens when the change is independent of the current sampled by the first output transistor, to prevent the gate-source voltage of the first output transistor from being coupled to the second output transistor, and the coupling switch is turned off The gate voltage of the first output transistor is transferred to the first transistor gate-source capacitance.

The transistor circuit further includes a second transistor gate-source capacitor.

This transistor circuit operates in three modes. In the current sampling mode, the first output transistor samples the current and the gate-source voltage of the first output transistor is stored in the second transistor gate-source capacitance. In the transfer mode, the gate voltage of the first output transistor is transmitted to the first transistor gate-source capacitor through the coupling switch. In the output mode, the second output transistor provides an output current that is derived from the voltage of the second transistor gate-source capacitor.

In another implementation, the first output transistor is part of the first amplifier. The second output transistor is part of the second amplifier and the second amplifier is connected in parallel to the first amplifier. The switch configuration includes a plurality of output switches that are respectively coupled to the first and second amplifiers to selectively couple an amplified output of each of the first and second amplifiers to a common output. The switch configuration includes a feedback switch and an input switch. The feedback switch is coupled to the common output terminal and Between the input terminals, and coupled to the first and second amplifiers. The input switch is coupled between the input end of the circuit and the input end, and is coupled to the first and second amplifiers. In one example, the transistor circuit operates in three modes. In the reset mode, the feedback switch and the equal output switch are turned on, and the input switch is turned off. In the first input mode, the first amplifier provides an output signal to the common output, and the feedback switch is turned off, and the input switch is turned on. In the second input mode, the second amplifier provides an output signal to the common output, and the feedback switch is turned off and the input switch is turned on.

The invention further provides a transistor circuit control method, comprising the steps of: coupling an output end of a first output transistor to a common output terminal; and coupling an output end of the second output transistor to a common output terminal. When the output end of the first output transistor is coupled to the common output terminal, the complex change in the driving state voltage of the first output transistor is isolated from the second output transistor. The first and second output transistors are controlled to provide the same steady state output.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

The present invention provides a transistor circuit and control method in which an output signal is provided by a first output transistor followed by a second output transistor. When the output end of the first output transistor is coupled to the common output terminal, the change in the gate-source voltage of the first output transistor is isolated from the second output transistor. However, the first and second output transistors are controlled to provide The same steady state output signal. The change is not related to the control input signal (eg, with respect to the reset operation) and the change in the transistor drive voltage is applied only to the first transistor.

First, an embodiment will be used to illustrate the current sampling circuit and method of the present invention. A first (current sampling) transistor is used to sample a current, and a second (current output) transistor is connected in parallel with the first transistor. In this case, the change with the sampled current and on the gate-source voltage is applied only to the first transistor. Only the stable gate voltage of the first transistor is transferred to the second transistor such that the second transistor avoids the transient current response delay.

Fig. 5 is a diagram showing an example of a transistor configuration using a current sampling circuit as a part. In Fig. 5, the transistor shown on the left side is replaced by the configuration of the transistor and the switch on the right side. These switches represent individual transistors or CMOS transmission gates.

The circuit includes a first (current sampling) transistor 10 (T1) for sampling a current and including a second (current output) transistor 12 (T2) in parallel with the first transistor 10. The gate-to-source voltage storage capacitor 14 (Cgs) is used to store the gate-to-source voltage of the second transistor 12.

The coupling switch 16 is used to selectively couple the gate of the first transistor 10 to the gate of the second transistor 12.

The two transistors 10 and 12 are coupled between the power rail "drain (D)" and "source (S)". Each of the transistors 10 and 12 has a switch 18/20 in series such that each transistor can be switched to detach or enter the circuit.

When the coupling switch 16 is turned on, it prevents a change in the gate-source voltage of the first transistor 10 from being coupled to the second transistor 12. In these voltage changes The prevention function provided by the coupling switch 16 is useful in situations where the sampling current is not relevant but is instead related to one of the reset operations of the circuit. When the coupling switch 16 is turned off, the gate voltage is transferred to the capacitor 14.

The circuit operates in the following three modes: current sampling mode: the first transistor 10 samples a current, and the gate-source voltage is stored; the transmission mode: the gate voltage of the first transistor 10 is transmitted to the coupling switch 16 to a gate of the second transistor 12; and an output mode: the second transistor 12 provides an output current obtained by the voltage of the storage capacitor 14.

When this circuit is operated in the first mode (current sampling mode), the gate-to-source voltage of the transistor is expected to change significantly. The first transistor 10 provides a drain current. Switch 18 is closed and switches 16 and 20 are open. In this state, the gate-to-source voltage of the second transistor 12 is maintained by the capacitor 14 (the capacitor 14 can be a true capacitor or only the capacitance of the transistor itself).

The second transistor 12 can provide a mode in which the change in the gate-source voltage is more limited or the change in the gate-source voltage is only caused by a change in the signal being processed by the circuit. Extreme current. In this mode, switch 18 is open and switches 16 and 20 are closed.

Under this method, the circuit is operated such that the second transistor 12 is only subjected to a significant change in the gate-source voltage, and a significant change in the gate-source voltage corresponds to the signal being processed. change. This mode of operation corresponds to the output mode described above.

The characteristics of the transistors 10 and 12 are identical on the surface, but the first transistor 10 The drain current is modified by the slow transient current effect, while the drain current of the second transistor 12 is not limited by the slow transient current response.

A key application of the method proposed by the present invention is to have circuitry operating in the sub-threshold region, particularly circuitry for sampling very low currents. The concept is to transfer the gate-source voltage from a sampling transistor that has sampled the current and is experiencing a slow transient current effect to a large change that has not experienced the gate-source voltage and therefore does not exhibit a slow transient current effect. The output transistor.

Figure 6 shows an embodiment of a current sampling circuit using the present invention, and Figure 7 shows a possible control signal timing.

The current (photocurrent) to be sampled is generated by the photodiode 30. In Fig. 6, the photodiode is represented by a current source CS6 and a capacitor Cp connected in parallel.

This current is sampled and maintained by the combination of transistors 10 and 12. The two CMOS inverters A1 and A2 amplify the error voltage, which is generated based on the difference between the photocurrent and the drain current of the transistor 10 or 12. This amplification step reduces the settling time of the circuit.

This circuit has a complex switch to control different modes of operation. These switches include a first set of switches that are controlled by a timing control signal Φ1. One of them is a reset switch 38 for short-circuiting the gate-source voltage capacitor 32 (Cs) connected to the first transistor 10. Inverters A1 and A2 also include bypass switches having the same timing to reset the feedback control loop (which includes the amplifier chain).

The second set of switches has a timing control signal Φ2. One of them is a switch (switch 18) that places the first transistor 10 inside or outside the circuit, and the other is the output switch 34. The coupling switch 16 is subjected to a timing control signal Controlled, it is opposite to the timing control signal Φ2. The switch 20 used to switch the transistor 12 into the circuit is also subjected to timing control signals. (ie, the complementary signal of Φ2) is controlled.

The feedback control loop includes a capacitor 40 (Ck) that will have a timing control signal The voltage (ie, the complementary signal of Φ1) is coupled to the input of the amplifier chain. As described above, this further confirms that a positive voltage is applied to the gate of the transistor during the sampling period. This amplifier chain has an output capacitor 42 (Cc). The capacitors of the amplifier chain store the offset voltage, and when the charge on these capacitors disappears over time, these capacitors are reset as part of the sampling operation.

As shown in Fig. 7, the control signals Φ1 and Φ2 are initially at a high level. The gate-source voltage of the first transistor is set to 0V as a reset operation, and the switches across inverters A1 and A2 are turned off, so that the threshold voltage of the inverter is established at its input and output terminals. This represents a reset of the feedback loop.

During the sampling period (S) of nearly 50 μs, the control signal Φ1 becomes a low level, and the control signal Φ2 is held at a high level.

Capacitor 40 produces a small increase in voltage at the input of inverter A1, and then produces a positive step on the gate voltage of first transistor 10. The positive step described above is preferable to the gate voltage of the first transistor 10 which is maintained at 0 V or becomes a negative value because the gate voltage of the first transistor 10 has been maintained at 0 V or becomes a negative value. The settling time of the sampling circuit becomes limited by the photocurrent and capacitance of the photodiode.

During sampling, the feedback operation is used to control the gate-source voltage of the first transistor 10 such that the gate current becomes equal to the photocurrent (the inverter in the feedback chain draws a negligible current at its output) . However, the initial step of the gate-source voltage of the first transistor 10 and subsequent control in the device can cause the aforementioned transient current response.

When the feedback is enabled, it compensates for the transient current by adjusting the value of the gate-source voltage. However, if the photocurrent is sampled by the first transistor 10 and then the photocurrent is maintained by maintaining the gate-source voltage of the device at a fixed value, the gate current changes over time and is directed toward the gate. - A steady state value shift of one of the source voltages. After the feedback loop is turned on, an error in the sampled current is increased at the end of the sampling operation. In order to avoid this effect, once the gate-source voltage has been established at the gate of the first transistor 10, this voltage is transferred to the gate of the second transistor 12, wherein the second transistor 12 does not experience the first The initial step of the gate of crystal 10, therefore, does not exhibit a slow change in the drain current. This transfer is accomplished by switching control signal Φ2 to a low level and maintaining control signal Φ1 at a low level (i.e., during a transfer period (T) of approximately 50 μs).

The coupling switch 16 between the two transistors 10 and 12 is turned off and charge sharing occurs between the capacitor 14/32 and the output capacitor 42 of the amplifier configuration. At the same time, the switch 18 in series with the drain of the first transistor 10 is turned on, and the switch 20 in series with the drain of the second transistor 12 is turned off, so that the second transistor 12 becomes connected to the feedback loop.

The feedback is then operated to adjust the gate-to-source voltage of the second transistor 12 until the drain current of the second transistor 12 is equal to the photocurrent.

Therefore, there is an effective second sampling period using the second transistor 12 as part of the transmission period.

At the terminal during the transfer, the control signals Φ1 and Φ2 become high (i.e., enter the sustain period (H)), the gate of the second transistor 12 becomes isolated, and the gate-source voltage is maintained by the capacitor 14. The drain current of the second transistor 12 then provides the output terminal OUT of the current-sampling circuit.

The proposed method can be applied to a thin film transistor circuit in which a slow transient current response of the device's drain current causes an error due to a change in the gate voltage.

This circuit is an example of a special case in sensing applications, especially when sensing small currents with respect to light intensity or temperature. This circuit can also be applied to other circuits in which the thin film transistor undergoes a gate voltage transient and is required to generate a properly defined drain current, for example, a circuit using a precharge technique.

For example, the present invention can be used in a display device that processes light sensor signals. In this example, light sensing can be used to control the display to automatically correlate to ambient light levels, and this control architecture is known. Light sensing can also be used to characterize the aging of a light source, such as a backlight within an electroluminescent display or, more specifically, a display pixel itself.

Another application of the invention is an amplifier or buffer circuit.

Figure 8 is a diagram showing a voltage amplifying circuit using the method of the present invention, again providing the advantage of reducing slow transient current errors.

This circuit has two inverting voltage amplifiers, INVA and INVB, which are configured in such a way as to operate as a unity gain amplifier, ie after feedback operation, The output voltage Vout is equal to the input voltage Vin. Of course, this is only an example of an amplifier operating like a buffer, but is implemented in the amplification circuit on the same principle.

A switch configuration includes output switches 80 and 82 to selectively couple each amplifier output to a common output 84. A feedback switch 85 is coupled between the common output terminal 84 and the input terminal 86 and is coupled to the first and second amplifiers. The input switch 88 is coupled between the circuit input terminal Vin and the input terminal 86 and coupled to the first and second amplifiers.

Each amplifier has a feedback switch that shorts its input and output, which forces the amplifier's threshold voltage to appear between the input and output. Each amplifier also has a capacitor CA/CB at its input.

Figure 9 shows the timing of each switch, such as the timing of signals Φ1 to Φ4.

During the first operational period 90 (which may be during reset), signal Φ1 is at a high level such that the input voltage is provided to both amplifiers. Signals Φ2, Φ3, and Φ4 are low levels. A voltage equal to (VthA-Vin) is established across capacitor CA, and a voltage equal to (VthB-Vin) is established across capacitor CB, where VthA and VthB are the threshold voltages of amplifiers INVA and INVB, respectively.

If the supply voltage is 5V, the threshold voltages VthA and VthB can be assumed to be 2.5V.

During the second operation period 92 (during the first feedback period), the signals Φ1 and Φ4 are at a low level, and the signals Φ2 and Φ3 are at a high level. This means that the amplifier INVA is operating in feedback mode and its input signal will initially be: VthA+VthB-Vin=5-Vin

For example, if Vin is 4V and the input of amplifier INVA is 2V, this means that the thin film transistor forming amplifier INVA will experience a step voltage of nearly 2.5V to 1V.

This step is likely to cause a slow transient current as described in Figure 3, which means that it will take several milliseconds (ms depending on the gain of the amplifier) before the output voltage Vout becomes equal to Vin.

In the third period 94 (second feedback period), the signal Φ4 becomes a high level, and the signal Φ3 becomes a low level. The amplifier INVA is separated from the feedback loop and the amplifier INVB will operate in the feedback mode. During this period, compared with the condition experienced by the thin film transistor of the amplifier INVB when the signal Φ3 is high, since the output voltage Vout has experienced some transient current when the signal Φ3 is high, the thin film transistor at the amplifier INVB Will experience less voltage steps.

Thus, it can be seen that the output signals (whether voltage or current) enabled by the present invention from a transistor are continuously provided by a two-phase isoelectric crystal or a dissimilar transistor circuit. The two transistor or transistor circuits are controlled to be driven to provide the same output signal. However, in this sequence, only the first transistor or the first transistor circuit is fully experienced with a change in drive state between two output cycles, such as produced during reset.

The circuit shown is merely an independent example, and there are many other current sensing circuits and amplifying circuits known to those of ordinary skill in the art to which the present invention pertains. Moreover, the invention is more generally applied to an output circuit to provide a current or voltage output from an output transistor depending on the input state.

The switches shown in this circuit can of course also be implemented by individual transistor or transistor gate circuits, and if such a circuit is integrated into the base of another device, such as a display, devices of the same technology will be used for these switches as well as Other circuit components on this substrate. Accordingly, the circuit implementations shown will be conventional to those of ordinary skill in the art to which the invention pertains.

In general, the invention can be applied to a circuit in which the circuit undergoes a periodic reset or pre-charge operation, resulting in a change in the transistor gate voltage that does not originate from a change in the control input signal, and the transistor gate The pole voltage changes. The method of the present invention provides an output transistor that is isolated from these changes such that the output transistor avoids slow transient current reactions (in addition to the large change effect on the current being sampled).

In the context of this description and patent, it will be appreciated that portions of the gate-source capacitance may include the capacitance of the transistor itself or an additional capacitor that can store the gate-source voltage in the transistor circuit.

Different variations will be understood by those of ordinary skill in the art to which the invention pertains.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

C1, Cd‧‧‧ capacitor

Clk1, Clk2, Clk3‧‧‧ timing

CS1‧‧‧current source

OUT‧‧‧ output

Tp1‧‧‧O crystal

VDD, VDD‧‧‧ voltage source

S1, S2, S3‧‧‧ switch

H‧‧‧Maintenance period

S‧‧‧Sampling period

VGS1‧‧‧ gate-source voltage first value

VGS2‧‧‧ gate-source voltage second value

ID‧‧‧汲polar current

10 (T1), 12 (T2) ‧ ‧ transistor

14(Cgs)‧‧‧ Storage Capacitors

16, 18, 20‧ ‧ switch

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

10 (T1), 12 (T2) ‧ ‧ transistor

14(Ct)‧‧‧ Storage Capacitors

16, 18, 20‧ ‧ switch

30‧‧‧Photosensitive diode

32 (Cs) ‧ ‧ capacitor

34, 38‧‧‧ switch

40 (Ck), 42 (Cc), Cp‧‧ ‧ capacitors

A1, A2‧‧‧ Inverter

CS6‧‧‧current source

OUT‧‧‧ output

Φ1, Φ2 , ‧‧‧control signal

S‧‧‧Sampling period

T‧‧‧Transfer period

H‧‧‧Maintenance period

80, 82, 85, 88‧‧ ‧ switch

84‧‧‧ Output

86‧‧‧ input

Cload‧‧‧ capacitor

INVA, INVB‧‧ amp amplifier

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Φ1, Φ2, Φ3, Φ4‧‧‧ control signals

90‧‧‧Reset period

92‧‧‧First feedback period

94‧‧‧Second period of return

Figure 1 shows a known current sampling circuit; Figure 2 is a timing diagram for explaining the circuit operation of Figure 1; and Figure 3 shows the current overshoot or undershoot observed in the reaction of a thin film diode. Figure 4 illustrates the transient current response of the drain current measured in the n-type low temperature polysilicon film; Figure 5 shows the configuration of the transistor according to an embodiment of the present invention; and Fig. 6 shows the current sampling according to an embodiment of the present invention. Fig. 7 is a timing chart showing a control signal in Fig. 6; Fig. 8 is a voltage amplifying circuit according to an embodiment of the present invention; and Fig. 9 is a timing chart showing a control signal in Fig. 8.

10 (T1), 12 (T2) ‧ ‧ transistor

14(Cgs)‧‧‧ Storage Capacitors

16, 18, 20‧ ‧ switch

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

Claims (16)

A transistor circuit comprising: a first output transistor; a second output transistor, wherein the first and second output transistors are used to provide an output signal to a common output of the transistor circuit; And a switch configuration, comprising: at least two output switches respectively disposed to the first and second output transistors for selectively connecting one of the output terminals of the first output transistor and the second output transistor An output terminal is coupled to the common output terminal, wherein the first and second output transistors are controlled to provide the same steady state output; and a coupling switch electrically connected to the first and second outputs respectively a transistor, wherein the coupling switch is adapted to operate such that when the output of the first output transistor is coupled to the common output, a complex change in a driving state voltage of the first output transistor is isolated The second output transistor. The transistor circuit of claim 1, further comprising a current sampling circuit, wherein: the first output transistor comprises a current sampling transistor for sampling a current; the second output transistor comprises Transmitting a current output of one of the transistors, and the second output transistor is coupled in parallel with the first output transistor; the transistor circuit further includes a first transistor gate-source capacitance; The coupling switch selectively couples a gate voltage of the first output transistor to a gate of the second output transistor; wherein the change is independent of the current sampled by the first output transistor The coupling switch is opened to prevent a gate-source voltage of the first output transistor from being coupled to the second output transistor, and the coupling switch is turned off to transmit the gate voltage of the first output transistor to The first transistor gate-source capacitance. The transistor circuit of claim 2, further comprising a second transistor gate-source capacitor. The transistor circuit of claim 3, wherein the transistor circuit operates in three modes: a current mode, in which the first output transistor samples the current, and The gate-source voltage of the first output transistor is stored in the second transistor gate-source capacitance; a transmission mode in which the gate voltage of the first output transistor is transmitted through the coupling a switch is coupled to the first transistor gate-source capacitance; and an output mode in which the second output transistor provides an output current that is derived from the second transistor gate-source The voltage of the pole capacitor. The transistor circuit of claim 4, wherein in the transfer mode, the current is further sampled by the second output transistor. The transistor circuit of claim 3, further comprising a reset switch for shorting the second transistor gate-source capacitance. The transistor circuit of claim 1, wherein: the first output transistor is part of a first amplifier; and the second output transistor is part of a second amplifier, the second amplifier is connected in parallel In the first amplifier. The transistor circuit of claim 7, wherein the switch configuration comprises: a feedback switch coupled between the common output end and an input end, and coupled to the first and second And an input switch coupled between the input of the circuit and the input, and coupled to the first and second amplifiers. The transistor circuit of claim 8, wherein the transistor circuit operates in three modes: a reset mode in which the feedback switch and the output switch are turned on, And the input switch is turned off; a first output mode, in the first input mode, the first amplifier provides the output signal to the common output terminal, and the feedback switch is turned off, the input switch is turned on; and a second An output mode, in the second input mode, the second amplifier provides the output signal to the common output, and the feedback switch is turned off, the input switch is turned on. The transistor circuit of claim 5, wherein the first and second output transistors comprise a plurality of thin film CMOS low temperature polysilicon transistors. Such as the transistor circuit described in claim 1 of the patent scope, the The first and second output transistors comprise a plurality of thin film CMOS low temperature polysilicon transistors. A transistor circuit control method includes: coupling an output end of a first output transistor to a common output terminal; coupling an output end of a second output transistor to the common output terminal; An output transistor is used to sample a current, and a gate-source voltage of the first output transistor is stored in a first transistor gate-source capacitor, wherein when the complex voltage at the gate-source voltage changes Regarding the current sampled, the change in the gate-source voltage is isolated from the second output transistor; transmitting a gate voltage of the first output transistor to a second transistor gate-source Capacitor; and using the second output transistor to provide an output current, wherein the output current is obtained from a voltage of the second transistor gate-source capacitance; wherein the first and second output transistors are controlled To provide the same steady state output. The transistor circuit control method of claim 12, further comprising shorting the first transistor gate-source capacitor within a reset operation between current sampling timings. The transistor circuit control method of claim 12, further comprising: when the gate voltage of the first output transistor is transmitted, using the second output transistor, and using the second output transistor One gate-source The pole voltage is stored in the second transistor gate-source capacitance. The transistor circuit control method of claim 13, further comprising shorting the first transistor gate-source capacitor within a reset operation between current sampling timings. The transistor circuit control method of claim 12, further comprising a voltage amplification method, wherein the first output transistor is a part of a first amplifier, and the second output transistor is a second amplifier A portion of the second amplifier is coupled in parallel with the first amplifier.