JPH11327515A - Load driving circuit and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load driving circuit by which the voltage to a drive load is not affected by the variation of characteristics of transistors. SOLUTION: This load driving circuit is provided with switches SW1 to SW4, a capacitor C1, a logic circuit 13 and an analog switch Q1. Respective one ends of the switches SW1, SW2 are connected to a signal line S, the other end of the switch SW1 is connected to one end of the switch SW3 and one end of the capacitor C1 and an input video signal Vin is connected to the other end of the switch SW3. The other end of the capacitor C1 is connected to the input terminal of the logic circuit 13 and the output terminal of the logic circuit 13 is connected to the gate terminal of the analog switch Q1. A first voltage VDD is impressed on the source terminal of the analog switch Q1 and the other end of the SW2 is connected to the drain terminal of the switch Q1. The signal line S is connected to one end of the switch SW4 and a second voltage VD is impressed on the other end of the switch SW4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for supplying an external input signal to a driving load, for example, a signal line driving circuit of a liquid crystal display device integrated with a driving circuit.

[0002]

2. Description of the Related Art A liquid crystal display device has a pixel array section in which signal lines and scanning lines are arranged in a matrix, and a driving circuit for driving the signal lines and scanning lines. Conventionally, since the pixel array section and the drive circuit are formed on separate substrates, it is difficult to reduce the cost of the liquid crystal display device.
It has also been difficult to increase the ratio of the actual screen size to the external dimensions of the liquid crystal display device.

[0003]

Recently, a TFT (Thin Film Transistor) is formed on a glass substrate by using polysilicon as a material.
Since the manufacturing technology for forming r) has been advanced, the use of this technology has made it possible to form the pixel array section and the drive circuit on the same substrate.

However, it is difficult at present to form a polysilicon TFT having uniform characteristics on a glass substrate, and the threshold voltage, the mobility and the like vary.
Therefore, even if the pixel array section and the drive circuit are formed on the same substrate, display quality such as uneven brightness may be reduced due to variations in TFT characteristics, and power consumption may increase.

The present invention has been made in view of the above points, and an object of the present invention is to provide a load driving circuit in which a voltage supplied to a driving load does not fluctuate due to variations in transistor characteristics. To provide.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the invention according to claim 1 comprises a first switching means, a second switching means, a capacitor, and a control circuit which is provided when an input voltage exceeds a predetermined threshold voltage. A load driving circuit comprising: a logic circuit whose output logic is inverted; and switching control means for controlling on / off of said first switching means, wherein a driving load is provided at a first end of said first switching means. And an input signal is supplied to a second end of the first switching means and a first end of the capacitor, and a second end of the capacitor is connected to an input terminal of the logic circuit, and the switching control means Turning off the first switching means for a predetermined period so that the input voltage of the logic circuit becomes substantially equal to the threshold voltage of the logic circuit, and then turning on the first switching means, The switching means is when the first switching means is on. As a voltage substantially equal to the input voltage to the driving load is supplied, whether or not to connect the reference voltage terminal the driving load according to the output of the logic circuit is for switching control.

According to a second aspect of the present invention, the first, second, third, fourth, fifth, and sixth switching means, the first and second capacitors, and the input voltage having a predetermined threshold voltage And a switching control means for controlling on / off of the first, third and fourth switching means, the load driving circuit comprising: A drive load is connected to the first end of the switching means, and an input signal is applied to each of the second end of the first switching means, the first end of the first capacitor, and the first end of the second capacitor. The second terminal of the first capacitor is connected to a first terminal of the third switching unit and an input terminal of the logic circuit, and a second terminal of the third switching unit is connected to the first terminal of the third switching unit. And the second terminal of the second capacitor is connected to the fourth terminal.
Is connected to a first end of the switching means, a second end of the fourth switching means is connected to a second voltage terminal, and the switching control means is configured to charge the first and second switches in response to the input signal. Second
The first switching means is turned off and the third and fourth switching means are turned on so as to be stored in the first capacitor.
Switching control, and then the first, third, and fourth
The second switching control for turning off the switching means is performed.
A third switching control is performed in which the first switching means is turned on and the third and fourth switching means are turned off, and the fifth and sixth switching means perform the logic control at the time of the second switching control. The first and second capacitors are reciprocally charged and discharged according to the output of the logic circuit so that an input voltage of the circuit becomes substantially equal to a threshold voltage of the logic circuit.
Switching means for connecting the driving load and the reference voltage terminal according to the output of the logic circuit so that a voltage substantially equal to the input voltage is supplied to the driving load at the time of the third switching control. The switching control is performed to determine whether or not the switching is performed.

According to a third aspect of the present invention, when the input voltage exceeds a predetermined threshold voltage, the first, second, third, fourth, and fifth switching means, the first and second capacitors, and A load driving circuit comprising: a logic circuit whose output logic is inverted; and switching control means for controlling on / off of said first, third and fourth switching means. First
A drive load is connected to the end, and a second
An input signal is supplied to each of a first end of the first capacitor, a first end of the first capacitor, and a first end of the second capacitor;
A second terminal of the first capacitor is connected to a first terminal of the third switching means and an input terminal of the logic circuit, and a second terminal of the third switching means is connected to a first voltage terminal. , A second end of the second capacitor is connected to a first end of the fourth switching means, a second end of the fourth switching means is connected to a second voltage terminal, The switching control means includes:
A first switching control for turning off the first switching means and turning on the third and fourth switching means so that the electric charge corresponding to the input voltage is stored in the first and second capacitors. Then, a second switching control for turning off the first, third and fourth switching means is performed, and thereafter, the first switching means is turned on and the third and fourth switching means are turned off. The fifth switching means performs the third switching control, and the fifth switching means controls the logic circuit so that an input voltage of the logic circuit becomes substantially equal to a threshold voltage of the logic circuit at the time of the second switching control. Controlling whether or not each second end of the first and second capacitors is short-circuited with each other according to an output;
The second switching means connects the drive load and a reference voltage terminal according to the output of the logic circuit so that a voltage substantially equal to the input voltage is supplied to the drive load during the third switching control. The switching control is performed to determine whether or not to connect.

According to a ninth aspect of the present invention, a signal array and a scanning line are formed vertically and horizontally, and a pixel array section having pixel electrodes arranged in a row near an intersection of these lines, and a scanning line drive for driving the scanning line In a liquid crystal display device in which a circuit and a signal line driving circuit for driving a signal line are formed over the same substrate, the signal line driving circuit switches a polarity of a signal voltage supplied to the signal line; A first load driving circuit according to any one of claims 1 to 7, and a second load driving circuit according to any one of claims 1 to 7, wherein the first and second load driving circuits are configured to receive the input signal. , And the polarity switching circuit alternately selects one of the outputs of the first and second load driving circuits at a predetermined timing and outputs the signal line. Is to be supplied to

The invention of claim 1 will be described with reference to FIGS. 1 and 2, for example. "First switching means" is replaced by the switch SW1 of FIG. 1, and "second switching means" is replaced by an analog switch Q1.
The "capacitor" is replaced with the "logic circuit" in the capacitor C1.
“Switching control means” corresponds to the switch switching control circuit 12 of FIG. 2, and “drive load” corresponds to the signal line S.

The invention of claim 2 will be described with reference to FIGS. 2 and 6, for example. "First switching means" is a switch SW1 of FIG. 6, and "second switching means" is an analog switch Q1.
The "third switching means" is on the switch SW5, the "fourth switching means" is on the switch SW6, the "fifth switching means" is on the transistor Q2, and the "sixth switching means" is on the transistor Q5.
3, the "first capacitor" is in the capacitor C1, the "second capacitor" is in the capacitor C3, the "logic circuit" is in the logic circuit 13, the "first voltage terminal" is in the 0V terminal,
The “second voltage terminals” correspond to the 10 V terminals, respectively.

The invention of claim 3 will be described with reference to FIG. 8, for example. The "first switching means" is a switch SW of FIG.
1, the "second switching means" is connected to the analog switch Q1,
The "third switching means" is on the switch SW5, the "fourth switching means" is on the switch SW6, the "fifth switching means" is on the transistor Q4, and the "first capacitor" is the capacitor C1.
The "second capacitor" is connected to the capacitor C3, the "logic circuit" is connected to the logic circuit 13, the "first voltage terminal" is connected to a 0V terminal, and the "second voltage terminal" is connected to a 10V terminal. Corresponding.

The "seventh switching means" according to the fourth aspect is shown in FIG.
It corresponds to the switch SW3 of 6,8.

The "eighth switching means" according to the fifth aspect is shown in FIG.
It corresponds to the switch SW2 of 6,8.

The "ninth switching means" according to the sixth aspect is shown in FIG.
This corresponds to the switches SW6 and SW8.

The invention of claim 9 will be described with reference to FIGS. 2 and 3, for example. The “pixel array section” corresponds to the pixel array section 2 of FIG. 3, and the “scan line drive circuit” corresponds to the scan line drive circuit 4. ,
The "signal line drive circuit" corresponds to the signal line drive circuit 3, the "first load drive circuit" corresponds to the load drive unit 11a, and the "second load drive circuit" corresponds to the load drive unit 11b.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a load driving circuit according to the present invention will be specifically described with reference to the drawings. Hereinafter, an example in which the load driving circuit according to the present invention is applied to a signal line driving circuit of a liquid crystal display device will be described.

(First Embodiment) FIG. 1 is a circuit diagram of a first embodiment showing a configuration of a main part of a load driving circuit according to the present invention, and FIG. 2 is a schematic block diagram showing a configuration of the entire load driving circuit. FIG. 3 is a schematic block diagram of a liquid crystal display device using the load drive circuit of FIG. 2 as a signal line drive circuit.

The liquid crystal display device shown in FIG.
A pixel array section 2 in which Sn and scanning lines G1 to Gn are formed vertically and horizontally and TFTs 1 for pixel display are arranged in rows near their intersections, and a signal line driving circuit 3 for driving each of the signal lines S1 to Sn
And a scanning line driving circuit 4 for driving each of the scanning lines G1 to Gn.

Each part constituting the liquid crystal display device of FIG. 3 is formed on the same substrate, and the transistors constituting the signal line driving circuit 3 and the scanning line driving circuit 4 are TFTs 1 for pixel display.
It is formed by the same manufacturing process.

The signal line driving circuit 3 is configured using the load driving circuit shown in FIG. The load drive circuit shown in FIG. 2 includes load drive units 11a and 11b for positive polarity and negative polarity provided for each of the signal lines,
a and a switch switching control circuit 12 for switching and controlling various switches in 11b.

The reason why the load driver 11a for the positive polarity and the load driver 11b for the negative polarity are separately provided is as follows.
Alternatively, the polarity of the drive voltage of the signal line is switched in units of one horizontal line or one frame.

FIG. 1 is a circuit diagram of the load driver 11a for positive polarity. As shown in FIG. 1, each of the load driving units 11a includes switches SW1 to SW4, an analog switch Q1 composed of a PMOS transistor, a logic circuit 13 in which two inverters are connected in cascade, and a capacitor C1. As shown in FIG. 3, a TFT for pixel display, a liquid crystal capacitor, an auxiliary capacitor, and the like are connected to the signal line S driven by the load driving units 11a and 11b. The load on the line S is equivalently converted to a resistance R and a capacitor C.
It is represented by 2.

One end of each of the switches SW1 and SW2 is connected to the signal line S, the other end of the switch SW1 is connected to one end of the switch SW3 and one end of the capacitor C1, and the other end of the switch SW3 is supplied with the input video signal Vin. You. The other end of the capacitor C1 is connected to the input terminal of the logic circuit 13,
Is connected to the gate terminal of the analog switch Q1. A first voltage VDD (for example, 10 V) is applied to a source terminal of the analog switch Q1, and the other end of the switch SW2 is connected to a drain terminal thereof. Switch SW4
Is connected to a signal line S, and a second voltage VD (for example, 5 V) is applied to the other end of the switch SW4. The switches SW1 to SW4 are switched by the switch switching control circuit 12 shown in FIG.

In FIG. 1, the switch SW1 and the capacitor C1
A, the connection point between the capacitor C1 and the logic circuit 13 is b, the connection point between the logic circuit 13 and the analog switch Q1 is c, and the connection point between the switches SW1 and SW2 is d.

FIG. 4 is a timing chart of each part in the load driving circuit 11a of FIG. 1. Hereinafter, the operation of the circuit of FIG. 1 will be described with reference to this timing chart. First, time T1 to T2
During the period of switch SW, the switch switching control circuit 12
1 to SW3 are turned off and the switch SW4 is turned on. Thereby, the voltage of the signal line S (point d in FIG. 1) becomes the second voltage V
The voltage becomes the same as D (for example, 5 V).

Next, during the period from time T2 to T3, the switch switching control circuit 12 turns on only the switch SW3.
Thus, the voltage at point a in FIG. 1 becomes equal to the voltage of the input video signal Vin. In FIG. 4, the voltage of the input video signal Vin is
An example in which the voltage is 7.5 V is shown. During this period, the signal line S
The voltage at (point d in FIG. 1) becomes 5V.

Here, assuming that the voltage at the input terminal (point b in FIG. 1) of the logic circuit 13 is slightly higher than the threshold voltage of the logic circuit 13 (for example, 5 V), The voltage at the output terminal (point c in FIG. 1) becomes 10 V, which is substantially equal to the power supply voltage. Therefore, the analog switch Q1 is turned off during this period.

Next, after the time T3, the switch switching control circuit 12 turns on the switches SW1 and SW2,
Turn off SW3 and SW4. At time T3, a in FIG.
Since the point is 7.5 V and the point d is 5 V, when the switch SW1 is turned on, the voltage at the point a is reduced by the point d. In response, the voltage at the point b in FIG. 1, which is the other end of the capacitor C1, also decreases, and the output of the logic circuit 13 is inverted to a low level (for example, 0 V). As a result, the analog switch Q1 is turned on, and the first voltage VDD is turned on.
Is supplied to the signal line S via the analog switch Q1 and the switch SW2, and the voltage of the signal line S (point d in FIG. 1) gradually increases.

When the voltage of the signal line S increases, the voltages at points a and b in FIG. 1 also increase accordingly. Eventually, time T
4, the voltage of the signal line S becomes equal to 7.5 V which is the voltage of the input video signal Vin, and the input voltage of the logic circuit 13 exceeds the threshold voltage (5 V) of the logic circuit 13 and the logic circuit 13 Is inverted again to a high level (for example,
10V). As a result, the analog switch Q1 turns off.

When the analog switch Q1 is turned off, the capacitance C2 on the signal line S is gradually discharged, and the voltage at the point d in FIG. 1 drops, but the voltage at the input terminal (point b in FIG. 1) of the logic circuit 13 becomes low. When the voltage falls below the threshold voltage of the logic circuit 13, the analog switch Q1 is turned on again, and the voltage at point d in FIG. 1 rises again. By repeating such operations,
The voltage of the signal line S (point d in FIG. 1) is held at 7.5 V, which is the voltage of the input video signal Vin.

FIG. 5 is a circuit diagram showing a detailed configuration of the load driver 11b for negative polarity. As shown in FIG. 5, the load driving section 11b has a point that the analog switch Q1 is n-type,
The point that the source electrode of the analog switch Q1 is grounded is different from the load driver 11a in FIG. 1, and the other configuration is the same.

As described above, in the first embodiment, the feedback loop is formed by the switches SW1 and SW2, the capacitor C1, the logic circuit 13, and the analog switch Q1 shown in FIG. If the voltage of the input video signal Vin is lower than the voltage of the input video signal Vin, the analog switch Q1 is turned on to perform control to increase the voltage of the signal line S. If the voltage of the signal line S is higher than the voltage of the input video signal Vin, the analog switch is switched. Control is performed to turn off Q1 and reduce the voltage of the signal line S. Thus, the voltage of the signal line S is set to a voltage substantially equal to the voltage of the input video signal Vin.

In the first embodiment, the input voltage of the logic circuit 13 in the signal line driving circuit 3 is set to a voltage substantially equal to the threshold voltage of the logic circuit 13 beforehand. , The voltage of the signal line S is not affected even if the characteristics of the transistors constituting the signal line driving circuit 3 vary.

(Second Embodiment) The logic circuit 1 shown in FIG.
3 is configured by combining transistors, the output level of the logic circuit 13 may change due to variations in the threshold value and mobility of the transistors, and the circuit may not operate normally.

Therefore, the second embodiment described below is characterized in that the variation in the characteristics of the logic circuit 13 is canceled.

FIG. 6 is a circuit diagram of a second embodiment of the load driving circuit, which is used as the signal line driving circuit 3 of the liquid crystal display device, as in the first embodiment. The circuit of FIG. 6 includes switches SW1 to SW4, an analog switch Q1 composed of a PMOS transistor, a logic circuit 13 in which inverters are cascaded in two stages, and a capacitor C1.
And In addition, the circuit of FIG. 6 includes a capacitor C3, switches SW5 to SW7, and PMOS transistors Q2 and Q3.

One end of each of the capacitors C1 and C3 and a switch
One ends of SW1 and SW3 are connected to each other. Capacitor C
1 has an input terminal of the logic circuit 13 and a switch SW5.
Is connected, and the other end of the switch SW5 is set to a third voltage (for example, 0 V). One end of a switch SW6 is connected to the other end of the capacitor C3, and a fourth voltage (for example, 10 V) is applied to the other end of the switch SW6.

The output terminal of the logic circuit 13 has a switch SW7
Is connected to the gate terminal of the analog switch Q1, and the other end of the switch SW7 is connected to the gate terminals of the transistors Q2 and Q3. One of the source / drain electrodes of the transistor Q2 is connected to a capacitor C1 and a switch.
It is connected between SW5 and the other is connected to CN terminal.
One of the source / drain electrodes of the transistor Q3 is connected between the capacitor C3 and the switch SW6, and the other is connected to the CNR terminal.

In FIG. 6, the connection point between the switches SW1 and SW3 and the capacitors C1 and C3 is a, the connection point between the capacitor C1 and the logic circuit 13 is b, and the connection point between the logic circuit 13 and the analog switch Q1 is c. The connection point between the switches SW1 and SW2 is d, and the connection point between the capacitor C3 and the switch SW6 is e.

FIG. 7 is a timing chart of each part in the load drive circuit of FIG.
The operation of the circuit of FIG.

First, during the period from time T11 to T12, the switch switching control circuit 12 turns on only the switch SW4.
As a result, the voltage of the signal line S becomes the same voltage (for example, 5 V) as the second voltage VD.

Next, during the period from time T12 to time T13, the switch switching control circuit 12 turns off the switches SW1, SW2 and SW4 and turns on the switches SW3, SW5 to SW7. As a result, the voltage at point a in FIG. 6 becomes the voltage of the input video signal Vin. FIG. 7 shows an example in which the voltage of the input video signal Vin is 7.5V. Since the switch SW1 is off, the voltage of the signal line (point d in FIG. 6) becomes 5V. Also switch
Since SW5 and SW6 are on, the connection point between capacitor C1 and switch SW5 (point b in FIG. 6) is 0V, and the connection point between capacitor C2 and switch SW6 (point e in FIG. 6) is 10V. Therefore, the output of the logic circuit 13 also becomes low level (about 0 V), and the analog switch Q1 and the transistors Q2 and Q3 are both turned on.

Next, during the period from time T13 to T15, the switch switching control circuit 12 turns on only the switch SW7.
After time T13, the CN terminal is set to 10V and the CNR terminal is set to 0V. The voltage setting of the CN terminal and the CNR terminal is performed by the switch switching control circuit 12 or another circuit block.

At time T13, the output of logic circuit 13 is at the low level, so that transistors Q2 and Q3 are both turned on, and the voltage at the connection point (point b in FIG. 6) between capacitor C1 and switch SW5 gradually increases. Then, the voltage at the connection point (point e in FIG. 6) between the capacitor C3 and the switch SW6 gradually decreases.

At time T14, the voltage at point b in FIG. 6 exceeds the threshold voltage (for example, 5.5 V) of the logic circuit 13, and
The output of the logic circuit 13 becomes high level (about 10 V), and the analog switch Q1 and the transistors Q2 and Q3 are both turned off. Therefore, during the period from time T14 to time T15, FIG.
Is the threshold voltage of the logic circuit 13 (for example,
5.5V), and the voltage at point e in FIG. 6 becomes a predetermined voltage (for example, 4.5V).

That is, when the input voltage of the logic circuit 13 becomes higher than the threshold voltage of the logic circuit 13, the transistor Q2 turns off and the input voltage of the logic circuit 13 decreases. When the voltage drops below the threshold voltage of the logic circuit 13, the transistor Q2 turns on and the input voltage of the logic circuit 13 rises. By such control, the voltage of the input terminal of the logic circuit 13 (point b in FIG. 6) is controlled to be equal to the threshold voltage of the logic circuit 13.

Next, at time T15, the switch switching control circuit 12 turns on the switches SW1, SW2, and SW7 and turns off the switches SW3, SW4, SW5, and SW6. At the time T15, the voltage of the signal line S is 5 V, and the voltage at the point a in FIG. 6 is 7.5 V. Therefore, the voltage at the point a in FIG. Thereby, the logic circuit 13
The voltage of the input terminal (point b in FIG. 6) also drops and the logic circuit 1
3, and the output of the logic circuit 13 becomes low level (about 0 V). Accordingly, the analog switch Q1 is turned on, the voltage of the signal line S (point d in FIG. 6) increases, and the voltages at points a, b, and e in FIG. 6 also increase accordingly.

Next, at time T16, the voltage at the input terminal (point b in FIG. 6) of the logic circuit 13 exceeds the threshold voltage of the logic circuit 13, and the output terminal of the logic circuit 13 goes high (about 10V). )become. Thereby, the analog switch Q1
Is turned off and the voltage of the signal line S (point d in FIG. 6) gradually decreases due to the discharge of the capacitor C2. However, when the voltage drops to a certain extent, the analog switch Q1 turns on again and the voltage of the signal line S increases again. .

By repeating such an operation, the signal line S (point d in FIG. 6) becomes the voltage of the input video signal Vin (about 7.
5V).

After the voltage of the signal line S becomes substantially constant (after time T18), the switch SW7 may be turned off.

As described above, the circuit of FIG. 6 is provided with the two capacitors C1 and C3 which perform charging and discharging in the opposite directions, and even if the threshold voltage of the logic circuit 13 varies, these capacitors C1 and C3 are not changed. Since the voltage at the connection point a does not fluctuate, the input voltage of the logic circuit 13 can be made substantially equal to the threshold voltage of the logic circuit 13 before the input video signal Vin is supplied to the signal line S.

As in the first embodiment, the signal line S
Is higher than the voltage of the input video signal Vin, the analog switch Q1 is turned off to lower the voltage of the signal line S. When the voltage of the signal line S becomes lower than the voltage of the input video signal Vin, the analog switch Q1 is turned off. Since the control is performed to increase the voltage of the signal line S by turning on, the voltage of the signal line S can be made substantially equal to the voltage of the input video signal Vin.

(Third Embodiment) A third embodiment is a simplified version of the circuit of the second embodiment (FIG. 6).
FIG. 8 is a circuit diagram of a third embodiment of the load drive circuit,
Similar to the first and second embodiments, this is used, for example, as the signal line driving circuit 3 of the liquid crystal display device shown in FIG.

The circuit of FIG. 8 is characterized in that a transistor Q4 is provided instead of the transistors Q2 and Q3 of the circuit of FIG. One of the source / drain electrodes of the transistor Q4 is connected between the capacitor C1 and the switch SW5, and the other is connected between the capacitor C3 and the switch SW6. The gate terminal of the transistor Q4 is connected to one end of the switch SW7.

In FIG. 8, the connection point between the switches SW1 and SW3 and the capacitors C1 and C3 is a, the connection point between the capacitor C1 and the logic circuit 13 is b, and the connection point between the logic circuit 13 and the analog switch Q1 is c. The connection point between the switches SW1 and SW2 is d, and the connection point between the capacitor C3 and the switch SW6 is e.

FIG. 9 is a timing chart of each part in the load driving circuit of FIG. 8. Hereinafter, FIG.
The operation of the circuit of FIG.

First, during the period from time T21 to T22, the switch switching control circuit 12 turns on only the switch SW4. As a result, the voltage of the signal line S becomes the same voltage (for example, 5 V) as the second voltage VD.

Next, during the period from time T22 to time T23, the switch switching control circuit 13 turns off the switches SW1, SW2 and SW4 and turns on the switches SW3, SW5 to SW7. This allows
The voltage at point a in FIG. 8 is the voltage of the input video signal Vin (for example,
7.5V). During this period, since the switch SW1 is off, the voltage of the signal line S (point d in FIG. 8) becomes 5V. Also, since the switches SW6 and SW7 are on, FIG.
Point b becomes 0V and point e becomes 10V. Therefore, the output of the logic circuit 13 also becomes low level (about 0 V), and the transistor Q4 is turned on.

Next, during the period from time T23 to time T25, the switch switching control circuit 13 turns on only the switch SW7. At this time, since the transistor Q4 is on,
Point b and point e are short-circuited, and both voltages change in the same direction. Specifically, the voltage at point b gradually increases from 0 V,
The voltage at point e gradually decreases from 10V.

At time T24, the voltage at the input terminal (point b in FIG. 8) of the logic circuit 13 exceeds the threshold voltage of the logic circuit 13, and the output voltage of the logic circuit 13 goes high (for example, 10 V). Change. Thereby, the transistor Q4
Is turned off, and the voltage at the point b does not rise any more.

Thereafter, when the voltage at the point b decreases due to the discharge of the capacitor C1 and eventually falls below the threshold voltage of the logic circuit 13, the output of the logic circuit 13 again changes to low level (for example, 0 V), and the transistor Q4 turns on again, and the voltage at point b in FIG. 8 rises. By repeating such an operation, the input terminal of the logic circuit 13 (b in FIG. 8)
The voltage at (point) becomes substantially equal to the threshold voltage of the logic circuit 13.

Next, at time T25, the switch switching control circuit 13 turns on the switches SW1, SW2, and SW7, and turns off the switches SW3, SW4, SW5, and SW6. This allows
The voltage at the points a and b in FIG. 8 drops once, the analog switch Q1 turns on, and the voltage of the signal line S gradually increases. Thereafter, at time T26, the voltage at point b exceeds the threshold voltage of the logic circuit 13, and the output of the logic circuit 13 is inverted to a high level (for example, 10 V). This allows
The analog switch Q1 is turned off, and the voltage of the signal line S does not increase any more.

As described above, in the third embodiment, one end of each of the capacitors C1 and C3 is connected to the source / drain electrode of the transistor Q4, and the gate electrode of the transistor Q4 is controlled according to the output voltage of the logic circuit 13. As a result, the voltage at the point b and the voltage at the point e in FIG. 8 can be controlled reciprocally, and the voltage at the input terminal (point b in FIG. 8) of the logic circuit 13 is logically similar to the second embodiment. The threshold voltage of the circuit 13 can be made substantially equal.

In the above-described first to third embodiments, the example in which the load driving circuit according to the present invention is applied to the signal line driving circuit 3 in the liquid crystal display device has been described. Besides, it can be widely applied.

The switches shown in FIG. 1 and the like can be configured using transfer gates and analog switches. The switches SW2 and SW4 shown in FIG.
Is not always necessary and may be omitted.

Further, in FIG. 1 and the like, an example has been described in which the logic circuit 13 is configured by cascade-connecting two stages of inverters. No restrictions.

[0068]

As described in detail above, according to the present invention, after setting the voltage of the input terminal of the logic circuit to be substantially equal to the threshold voltage of the logic circuit, an external input signal is applied to the driving load. Therefore, even if the threshold value of the logic circuit varies, the voltage supplied to the drive load is not affected. Therefore, when the present invention is applied to, for example, a signal line drive circuit of a liquid crystal display device, a drive circuit integrated liquid crystal display device having excellent display quality without luminance unevenness can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment showing a configuration of a main part of a load drive circuit.

FIG. 2 is a schematic block diagram illustrating the configuration of the entire load driving circuit.

FIG. 3 is a schematic block diagram of a liquid crystal display device using the load driving circuit of FIG. 2 as a signal line driving circuit.

FIG. 4 is a timing chart of each part in the load drive circuit of FIG. 1;

FIG. 5 is a circuit diagram showing a detailed configuration of a load driver for negative polarity.

FIG. 6 is a circuit diagram of a second embodiment of the load drive circuit.

FIG. 7 is a timing chart of each part of the load drive circuit of FIG. 6;

FIG. 8 is a circuit diagram of a third embodiment of the load drive circuit.

FIG. 9 is a timing chart of each part in the load drive circuit of FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 TFT 2 Pixel array part 3 Signal line drive circuit 4 Scan line drive circuit 11a, 11b Load drive part 12 Switch switching control circuit 13 Logic circuit Q1 Analog switch Q2, Q3 Transistor SW1-SW4 Switch

Claims (9)

[Claims] A first and second switching means, a capacitor, a logic circuit for inverting an output logic when an input voltage exceeds a predetermined threshold voltage, and an on / off switch for the first switching means. A load control circuit comprising: a switching control means for controlling the load; a driving load connected to a first end of the first switching means; a second end of the first switching means and a first end of the capacitor. And a second end of the capacitor is connected to an input terminal of the logic circuit, and the switching control means determines that an input voltage of the logic circuit is substantially equal to a threshold voltage of the logic circuit. So that the first switching means is turned off for a predetermined period, and then the first switching means is turned on. The second switching means applies the drive load to the driving load when the first switching means is turned on. A voltage substantially equal to the input voltage is supplied. , The load driving circuit, characterized by switch controlling whether to connect the reference voltage terminal the driving load according to the output of the logic circuit. 2. The first, second, third, fourth, fifth and sixth aspects.
Switching means, first and second capacitors, a logic circuit for inverting output logic when an input voltage exceeds a predetermined threshold voltage, and ON / OFF of the first, third, and fourth switching means. A switching control means for controlling turning-off of the first switching means, wherein a driving load is connected to a first end of the first switching means; a second end of the first switching means; An input signal is supplied to each of a first end of the capacitor and a first end of the second capacitor, and a second end of the first capacitor is connected to a first end of the third switching means and the logic circuit. A second terminal of the third switching means is connected to a first voltage terminal; a second terminal of the second capacitor is connected to a first terminal of the fourth switching means. And a second end of the fourth switching means is connected to a second voltage terminal. The switching control means turns off the first switching means and turns on the third and fourth switching means so that electric charges corresponding to the input signal are accumulated in the first and second capacitors. The first switching control is performed, and then the first,
A second switching control for turning off the third and fourth switching means is performed, and thereafter, the first switching means is turned on and the third switching means is turned on.
And a third switching control for turning off the fourth switching means, wherein the fifth and sixth switching means are arranged such that, when the second switching control is performed, the input voltage of the logic circuit is a threshold voltage of the logic circuit. The first and second capacitors are charged and discharged reciprocally according to the output of the logic circuit so that the input voltage becomes substantially equal to the input voltage during the third switching control. A load drive circuit for switching between connection and non-connection of the drive load and a reference voltage terminal in accordance with an output of the logic circuit so that substantially equal voltages are supplied to the drive load. 3. The first, second, third, fourth and fifth switching means, the first and second capacitors, and the output logic is inverted when the input voltage exceeds a predetermined threshold voltage. What is claimed is: 1. A load driving circuit comprising: a logic circuit; and switching control means for controlling on / off of said first, third, and fourth switching means, wherein said first driving means is driven by a first end of said first switching means. A load is connected, an input signal is supplied to each of a second end of the first switching means, a first end of the first capacitor, and a first end of the second capacitor; A second end of the third switching means is connected to a first end of the third switching means and an input terminal of the logic circuit; a second end of the third switching means is connected to a first voltage terminal; A second end of the second capacitor is connected to a first end of the fourth switching means; A second end of the switching unit is connected to a second voltage terminal, and the switching control unit is configured to switch the first switching so that a charge corresponding to the input voltage is stored in the first and second capacitors. A first switching control for turning off the means and turning on the third and fourth switching means is performed.
A second switching control for turning off the third and fourth switching means is performed, and thereafter, the first switching means is turned on and the third switching means is turned on.
And a third switching control for turning off a fourth switching means, wherein the fifth switching means makes the input voltage of the logic circuit substantially equal to the threshold voltage of the logic circuit at the time of the second switching control. The first circuit according to the output of the logic circuit.
And controlling whether or not each second end of the second capacitor is short-circuited with each other. The second switching means supplies a voltage substantially equal to the input voltage to the drive load during the third switching control. A load driving circuit for controlling whether or not to connect the driving load and a reference voltage terminal in accordance with an output of the logic circuit. 4. The apparatus according to claim 1, further comprising: seventh switching means to which said input signal is supplied to a first terminal and a second terminal of said first switching means is connected to a second terminal. 4. The load driving circuit according to claim 1, wherein said seventh switching means is turned on only while said one switching means is off. 5. An apparatus according to claim 5, further comprising: an eighth switching means connected between the driving load and the second switching means, wherein the switching control means is configured such that an input voltage of the logic circuit is a threshold voltage of the logic circuit. 5. The load drive circuit according to claim 1, wherein said eighth switching means is turned on after the value becomes substantially equal to the following. 6. A ninth switching means having a first terminal connected to the drive load and a second terminal applied with a predetermined voltage, wherein the switching control means turns on the first switching means. 6. The load driving circuit according to claim 1, wherein the ninth switching means is turned on for a predetermined period to set one end of the driving load to a predetermined voltage. 7. The logic circuit according to claim 1, wherein the logic circuit is formed by cascading one or more inverting amplifier circuits whose output logic is inverted at a predetermined threshold voltage. The load drive circuit as described. 8. The apparatus according to claim 1, wherein said driving load is a signal line for supplying pixel data to a pixel electrode.
8. The load drive circuit according to any one of claims 7 to 7. 9. A pixel array section having signal lines and scanning lines formed vertically and horizontally and having pixel electrodes arranged near intersections of these lines, a scanning line driving circuit for driving the scanning lines, and a signal line. 8. A liquid crystal display device having a signal line driving circuit for driving the same on a same substrate, wherein the signal line driving circuit switches a polarity of a signal voltage supplied to a signal line, and a polarity switching circuit. And a second load drive circuit according to any one of claims 1 to 7, wherein the first and second load drive circuits are configured to receive the input signal. A signal voltage having different voltage levels is output based on a signal, and the polarity switching circuit alternately selects one of the outputs of the first and second load driving circuits at a predetermined timing and outputs a signal. To feed the wire A liquid crystal display device according to symptoms.