KR100218511B1 - Liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device that uses a front gate to form a storage capacitor. The present invention relates to a liquid crystal display device that forms a storage capacitor. By doing so, there is an effect that can improve the characteristics of the product.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display device, and more particularly, to a method for driving a liquid crystal display device in which a holding capacitor is formed by using a front gate.

In general, thin film transistor liquid crystal displays have liquid crystal panels, drive integrated and peripheral rooms

Made of sheet

A plurality of pixels for display operation are formed in the liquid crystal panel, and these pixels are driven by signals applied through wirings. The wiring includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or a data line for transferring an image signal, and each pixel is connected to one gate line and one data line. In addition, a thin film transistor is formed at a portion where the gate line and the data line cross each other.

A method of driving a display screen of a liquid crystal display using the thin film transistor

Is configured to control the data input for each line in the horizontal direction to be sequentially driven in one horizontal line in the vertical direction to drive all the lines corresponding to a predetermined time to configure the display screen.

In addition, in driving such a liquid crystal display, a storage capacitor is applied to form a storage capacitor for applying a data signal to each pixel and holding the first applied signal until the next data signal is applied. ). As a method of using such a storage capacitor electrode, a shear gate method and an independent wiring method are generally used.

The independent wiring method adds one wiring to the pixel area independently of the gate line.

To form a storage capacitor electrode via the pixel electrode and the insulating film.

In the front gate method, a storage capacitor is formed by connecting a pixel electrode formed in each pixel to a gate line applying a scan signal to a neighboring pixel, and using the neighboring gate line as the storage capacitor electrode.

The shear gate method is advantageous in that there is no additional process than the independent wiring method, and it is common to use the shear gate method to realize a high aperture ratio.

In the front gate type liquid crystal display, since the storage capacitor electrode uses the gate line of the front end, an additional gate line is added to a portion not shown on the display screen to form the storage capacitor electrode in the first pixel row. Doing. This is called gate line 0.

It is necessary to apply a constant voltage to the gate line 0 for the function of the storage capacitor electrode and apply a gate off signal to give the same characteristics as the other storage capacitor electrode.

However, since the gate driving integrated circuit does not have an additional output signal for the gate line 0, the signal for the gate line 0 must be supplied externally.

Next, referring to the accompanying drawings, the driving method of the conventional liquid crystal display device according to the prior art will be described in more detail as follows.

1 is a circuit diagram showing a structure of a liquid crystal display device of a shear gate type according to the related art.

As shown in FIG. 1, a display panel of a liquid crystal display according to the related art includes a plurality of gate lines G ₁ , G ₂ , and the like. , G _n-3 , G _n-2 , G _n-1 , G _n ) and a number of data lines (D ₁ , D ₂ , , D _m ) intersect each other to define the pixel region P. Each pixel area P is a switching element, and the first terminal is a gate line G ₁ , G ₂ ,. , G _n-3 , G _n-2 , G _n-1 , G _n ), and the second terminal are data lines D ₁ , D ₂ , , Dm, and the third terminal are formed with a thin film transistor TFT having one terminal connected to the other terminal of the liquid crystal capacitor C _1C connected to the common electrode Vcom. In each pixel area P, one terminal is connected to the third terminal of the thin film transistor TFT, and the other terminal is connected to the gate lines G ₀ , G ₁ , and the front end. , G _n-3 , G _n-2 , and G _{n -1} are formed to hold the capacitor Cst. Therefore, the other terminal of the storage capacitor Cst formed in the pixel region P of the first column is connected to the gate line G ₀ further formed.

In the conventional front gate type liquid crystal display, an output corresponding to gate ₂ (G ₂ ) or gate _n (G _n ) is applied to gate ₀ to apply a signal to gate 0 (G ₀ ). The signal is applied to the line G ₀ .

However, the conventional front gate type liquid crystal display device has a gate line G ₂ .

Alternatively, since the output corresponding to gate n (G _n ) is connected to gate 0 (G ₀ ), an additional load is generated on gate ₂ (G ₂ ) or gate _n (G _n ) so that another load is generated. Unlike the gate line, the scan signal is delayed.

Another method is to construct a circuit externally and apply a signal to gate line 0.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and to equalize the charge amount of the pixel electrode formed in all the pixels by controlling the charge amount of the holding capacitor formed in the first pixel row.

1 is a circuit diagram showing the structure of a liquid crystal display device according to the prior art.

2 is a circuit diagram showing the structure of a liquid crystal display according to an embodiment of the present invention.

3 is a circuit diagram illustrating a structure of a liquid crystal display according to another exemplary embodiment of the present invention.

4 is a graph illustrating characteristics of charged pixel voltages of pixel electrodes in a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a diagram showing the structure and characteristics of a holding variable capacitor used in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a plan view of a part of a dot inverted liquid crystal display in FIG. 3; FIG.

FIG. 7 is a circuit diagram of supplying a signal to gate line 0 in the dot inverted liquid crystal display of FIG.

In the liquid crystal display according to the present invention, a storage variable capacitor capable of changing the charge amount is formed in the first pixel row using the gate line 0 as one terminal.

The other terminal of the holding variable capacitor becomes each pixel electrode formed in the pixel row.

Such a holding capacitor consists of an insulating film and a conductive layer between the pixel electrode and the gate line 0.

The insulating film is a nitride film or an oxide film, and the conductive layer is an amorphous silicon layer composed of a doped portion and an undoped portion.

In the driving method, the liquid crystal display device satisfies even one gate line in the gate line inversion method and the frame inversion method, but in the dot inversion method, the liquid crystal display device has a phase inverted with neighboring data lines. Since the data signal is applied, the even gate number 0 connected to the even pixel and the odd gate number 0 connected to the odd pixel are formed separately in the first pixel row.

In the liquid crystal display according to the present invention, the storage variable capacitor formed in the first pixel row may form a desired charging amount according to the voltage applied through the gate line 0. As a result, the potential of the pixel electrode formed in the first pixel row is changed.

Next, embodiments of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice the present invention.

FIG. 2 is a circuit diagram showing a structure of a liquid crystal display according to a first embodiment of the present invention, and FIG. 3 is a circuit diagram showing a structure of a liquid crystal display according to a second embodiment of the present invention.

FIG. 2 illustrates a liquid crystal display according to a first exemplary embodiment of the present invention, and as in the related art, a plurality of gate lines G ₁ and G ₂ , which define a pixel region P, are illustrated. , G _n-3 , G _n-2 , G _n-1 , G _n ) and a number of data lines (D ₁ , D ₂ , , D _n ) are formed by crossing each other. In each pixel area P, thin film transistors TFTs, which are switching elements, are formed. The gate electrodes of the thin film transistors TFT include gate lines G ₁ , G ₂ , and the like. , G _n-3 , G _n-2 , G _n-1 , G _n ), and the drain electrodes are connected to the data lines D ₁ , D ₂ , , D _m ), and the source electrode is connected to the other terminal of the liquid crystal capacitor C _1c having one terminal connected to the common electrode Vcom. Also, in each pixel area P except the first pixel area P, one terminal is connected to the source electrode of the thin film transistor TFT, and the other terminal is connected to the gate lines G ₁ , G ₂ , and the front end. , G _n-3 , G _n-2 , and G _n-1 ) are provided with a holding capacitor C _st .

Unlike the related art, in the first pixel region P, a storage variable capacitor G _stv having one terminal connected to the source electrode of the thin film transistor TFT and the other terminal connected to the gate line G _{0 of 0} is provided. Formed.

The method of connecting one gate line G ₀ to the storage variable capacitor C _stv is a line reversal method of inverting one pixel row in units, but sequentially from the gate line 1 to the last gate line. However, it is preferable to the frame inversion method of inverting the time which is turned on once in units, but not to the dot inversion method of inverting the pixel region P in units.

3 shows the structure of a liquid crystal display of a front gate applied to a dot inversion scheme.

A such, the rest of the structure is connected in turn via the same from the structure of the two, and a variable for holding in the first are formed on the second pixel row increases passer emitter (C _stv) two 0 gate line (G0o, G0e) have. A variable capacitor for maintaining the even-numbered pixel region (C _stv) is 0. gate line is connected with the (G0e), odd-numbered sustain variable capacitors (C _stv) for the second pixel region is connected to the gate line (G0o) 0 have.

In the liquid crystal display of dot inversion, data lines D ₁ , D ₂ , , It is necessary to consider that a data signal having an inverted phase is applied to a data line adjacent to each other, the data signal input to D _m ), so two gate lines G _0o and G _0e are required.

When more specifically explained, where 0 gate line _{(G 0, G 0o, G} 0e) maintaining a variable capacitor (C _stv) for which is connected to the following:

4 is a diagram illustrating characteristics of a charged pixel voltage of a pixel electrode in a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4A illustrates an equivalent circuit for one pixel. The thin film transistor TFT is disposed at the intersection of the gate line G and the data line D. As described above, one pixel area P is illustrated. The liquid crystal capacitor C _1c and the storage capacitor C _{st are} connected to the thin film transistor TFT. In the unit pixel region P, a parasitic capacitance C _ds is formed between the source electrode s and the drain electrode d of the thin film transistor TFT, and the parasitic capacitance is formed between the gate electrode g and the drain electrode d. The capacitance Cgd is formed.

4B illustrates the voltage V _p of the pixel electrode formed in the pixel region P when the gate voltage V _g and the data voltage V _d are applied.

Applying a gate voltage (V _g) immediately after the data voltage (V _d) applied to the pixel electrode of the source electrode (S) and via the drain electrode (d) data voltage (V _d) a pixel area (P) Is approved. When the data voltage V _d is completely applied to the pixel electrode such that the pixel voltage V _p and the data voltage V _d become the same, when the gate voltage V _g is turned off, the data voltage V _d is and the pixel voltage (V _p) is to be kept the same, the gate voltage (V _g) is the pixel voltage (Vp) is also a pixel voltage (V _p) by ΔVp the falling moment is changed. This is called a kick back or feedthrough voltage. This is because parasitic capacitance Vgs is formed in the thin film transistor TFT. The expression ΔVp is expressed as follows.

ΔV _p = ΔV _g × [C _gd / (C _st + C _cl + C _gd )]

It is preferable to increase C _st in order to reduce ΔV _p , but there is a problem in that the aperture ratio decreases because a portion where the pixel electrode and the gate line or the independent wiring overlap is made large.

Therefore, in the liquid crystal display according to the present invention, the variable capacitance for maintaining the value of C _st

It intended to form a foundation (C _stv) to adjust the pixel voltage (V _p) to control the kickback voltage (ΔV _p).

In other words, normally white (normally white) type display the brightness of the first pixel line in the liquid crystal display brighter than the other pixel lines, to increase the charge of the variable capacitor (C _stv) for maintaining reducing ΔVp the kickback voltage change ΔVp This is a complementary adjustment towards the black data level. The voltage difference between the common voltage V _com and the pixel voltage V _p is made larger.

The structure of the variable capacitor C _stv for maintaining the liquid crystal display according to the present invention is as follows.

5 is a view illustrating a variable capacitor for use in a liquid crystal display according to an exemplary embodiment of the present invention.

It is a figure which shows the structure and characteristic of a sheeter.

FIG. 5A illustrates the structure of the holding variable capacitor C _stv , in which a first electrode 20 is formed on a portion of the substrate 10, and an insulating film 30 covering the first electrode 20 is formed on the substrate. Formed. An amorphous silicon layer 40 and an amorphous silicon layer 50 doped with N-type impurities at a high concentration are successively formed on the insulating film 30, and the low second electrode 60 is formed thereon.

Here, the manufacturing method of the storage variable capacitor (C _stv ) may be formed at the same time forming the thin film transistor (TFT), wherein the first electrode 20 is a gate line (G ₀ , G _0o , ₀₎ ,

G _0e ) and the second electrode 60 is a pixel electrode formed in the pixel region P.

The holding variable capacitor C _stv is applied to the two electrodes 20 and 60 because the amorphous silicon layers 40 and 50, which are conductive layers, are additionally disposed between the first electrode 20 and the second electrode 60. The capacitance C ₁₂ may be changed depending on the voltage V ₁₂ (see FIG. 5B).

Looking at the structure of the liquid crystal display device is applied such a variable capacitor (C _stv )

As follows.

FIG. 6 is a plan view illustrating a portion of a dot inversion liquid crystal display of FIG. 3.

As shown in FIG. 6, the dot inverted liquid crystal display according to the exemplary embodiment of the present invention has gate lines G _0o and G _0e and gate line G _{1 in the} horizontal direction on the substrate 10. Are parallel to each other, and the data lines D ₁ and D ₂ defining the pixel region P intersect with each other and are formed in the vertical direction. A thin film transistor TFT including a semiconductor layer 70 made of an amorphous silicon layer is formed at a portion where the gate line G ₁ and the data lines D ₁ and D ₂ intersect each other. The pixel electrode 80 connected to the thin film transistor TFT is formed at P). The first gate line G ₁ is a front end of the second gate line (not shown), and a branch of the storage capacitor 81 overlapping the pixel electrode 80 is formed to form the storage capacitor C _st . It is. 0 gate line (G _0o, G _0e) is a pixel electrode (80 driven by the No. 1 gate line (G1) to form a variable capacitor (C _stv) for holding a front end of the gate line (G ₁₎ 1 ) And a holding capacity branch 82 is formed. In addition, a conductive layer made of an amorphous silicon layer having the same properties as that of the semiconductor layer 70 is disposed at the portion where the storage capacitor branch 82 and the pixel electrode 80 overlap the gate lines G _0o and G _0e . 90 is formed.

Through the conductive layer 90, the capacitance can be variably formed between the branch 82 for the storage capacitance of the gate lines G _0o and G _0e and the pixel electrode 80.

In the dot inverted liquid crystal display, since data signals having opposite phases are always applied to the _first data line D ₁ and the second data line D ₂ , two gate lines G _0o and G _0e are applied. This is essential. In addition, since the pixel voltages of the pixel electrode 80 receiving the data signal through the _first data line D ₁ and the second data line D ₂ also have opposite phases, two gate lines G0o, The voltages applied to G0e) must also be applied opposite phases.

7 is a voltage generation circuit for a gate line signal of line 0 according to the present invention.

Referring to FIG. 7, the voltage generation circuit includes a reference voltage generator 100, a first analog switch 200, and a second analog switch 300.

The reference voltage generation unit 100 inputs two variable resistors VR1 and VR2 sequentially connected between a power supply voltage Vcc and ground and two operational amplifiers 101 for inputting voltages of the variable resistors VR1 and VR2. , 102). Each of the operational amplifiers 101 and 102 is a kind of unity gain buffer that operates as a voltage follower. The non-inverting input terminal and the output terminal of the operational amplifiers 101 and 102 are connected to each other, and voltages of the variable resistors VR1 and VR2 are respectively input to the inverting input terminals. The outputs of the two operational amplifiers 101 and 102 are provided to the first analog switch 200 and the second analog switch 300. The output of the operational amplifier 101 is provided to the two switches 200 and 300 as a high level voltage, and the output of the operational amplifier 102 is provided to the two switches 200 and 300 as a low level voltage. The high and low levels may be adjusted by the two variable resistors VR1 and VR2, respectively.

The first analog switch 200 selects one of a high level voltage or a low level voltage output from the reference voltage generator 100 according to a signal inversion control pulse RVS, and the second analog switch 300. Selects either the high level voltage or the low level voltage according to the inversion signal / RVS of the signal inversion control pulse. The output signal of the switch 200 is provided to the odd-numbered zero gate line G0o, and the output signal of the switch 300 is provided to the even-numbered zero gate line G0e. In this case, since the switching operations are controlled by signals in which the two switches 200 and 300 are opposite in phase to each other, the signals output from the respective switches are opposite in phase to each other. For example, when the high level voltage of the two inputs is selected by the first analog switch 200 by the high level signal inversion control pulse RVS, the inversion signal / RVS of the low level signal inversion control pulse is selected. In the second analog switch 300, a low level voltage of two inputs is selected.

Thus, as described above, the voltage circuit of FIG. 7 can provide voltages that are out of phase with each other to drive the odd-numbered zero gate lines and the even-numbered zero gate lines.

Therefore, in the liquid crystal display according to the present invention, by adjusting the capacitance of the first pixel row by using a variable capacitor, the amount of charge of the holding capacitor formed in all the pixels is uniformed, thereby improving product characteristics. have.

Claims (6)

A variable capacitor for a liquid crystal display device comprising a transparent insulating substrate, a first electrode formed on the substrate, an insulating film covering the first electrode, a conductive layer formed on the insulating film, and a second electrode formed on the conductive layer. . The variable capacitor of claim 1, wherein the conductive layer comprises an amorphous silicon layer and a doped amorphous silicon layer. A plurality of gate regions and a plurality of data lines that are formed to cross each other, and are formed at an intersection portion of the gate line and the data line, and are connected to a gate electrode connected to the gate line and the data line. A thin film transistor including a drain electrode and a source electrode, the pixel electrode being connected to the source electrode, one terminal connected to the pixel electrode, and the other terminal connected to the common electrode. A liquid crystal capacitor, a retention capacitor in which one terminal is connected to the pixel electrode in each of the pixel regions except for the pixel region in the first row, and the other terminal is connected to the gate line in the front end, the pixel in the first row. One side terminal is connected to the source electrode in the region. The other terminal includes a liquid crystal display device including a variable capacitor for holding a gate that is connected to line and a single zero. The liquid crystal display of claim 3, wherein a voltage is applied to the gate line 0 to change the amount of charge of the storage variable capacitor to adjust the voltage of the pixel electrode formed in the pixel area of the first row. The other variable of the holding variable capacitor of the pixel area of the first row. A liquid crystal display device whose side terminal is connected to one gate line. The liquid crystal display of claim 5, wherein the other terminals of the even-numbered holding variable capacitor and the odd-numbered holding variable capacitor in the first row are connected to two different gate lines.