KR100783709B1 - liquid crystal device for compensating kick-back voltage and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display for compensating kickback voltage and a driving method thereof.

The present invention provides a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a plurality of dummy gate lines arranged in parallel with the gate lines, and are formed in regions where the gate lines and the data lines cross each other. A liquid crystal panel including a plurality of pixels including a switching element connected to a gate line and a data line, a pixel electrode connected to the switch element, and a dummy switch connected to the pixel electrode and connected to the dummy gate line; A scan driver supplying a gate voltage to the gate line and the dummy gate line; And a data driver for supplying a corresponding gray voltage to the data line according to an applied data signal.

According to the present invention, by making the kickback voltage generated in each pixel of the liquid crystal panel the same, flicker caused by the kickback voltage difference can be prevented, and as a result, the image quality of the liquid crystal display can be remarkably improved.

LCD, LCD, Picture Quality Improvement, Kickback Voltage, Dummy Switch

Description

Liquid crystal display for compensating kick-back voltage and driving method

1 is a pixel equivalent circuit diagram of a general thin film transistor liquid crystal display.

2 is a diagram illustrating voltage distortion caused by a kickback voltage.

3 is a pixel structure diagram according to an embodiment of the present invention.

4 is a pixel structure diagram illustrating a kickback voltage compensation principle according to an exemplary embodiment of the present invention.

5 is an overall structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for compensating kickback voltage.

A TFT-LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field.

On the substrate of such a TFT-LCD, a plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed, and an area surrounded by the gate lines and the data lines defines one pixel. TFTs are formed at portions where the gate lines and the data lines of each pixel cross each other.

1 shows an equivalent circuit for a unit pixel in a typical TFT-LCD.

As shown in FIG. 1, the gate electrode, the source electrode, and the drain electrode of the TFT 10 are connected to the gate line, the data line, and the pixel electrode P, respectively. A liquid crystal material is formed between the pixel electrode P and the common electrode Com, which is equivalently represented as a liquid crystal capacitor Clc. The storage capacitor Cst is formed between the pixel electrode and the common electrode, and the parasitic capacitance Cgd is generated between the gate electrode and the drain electrode due to misalignment.

The operation of the TFT-LCD will be described as follows.

First, the TFT 10 is applied by applying a gate-on voltage to the gate electrode connected to the gate line to be displayed, and then applying the data voltage Vd + representing the image signal to the source electrode to apply the data voltage to the drain electrode. Do it. Then, the data voltage Vd + is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the pixel electrode P, respectively, and an electric field is formed by the potential difference between the pixel electrode P and the common electrode Com. do. At this time, since the liquid crystal deteriorates when an electric field in the same direction is continuously applied to the liquid crystal material, the LCD panel drives the image signal to be positively and negatively repeated with respect to the common electrode in order to prevent deterioration of the liquid crystal.

On the other hand, when the TFT is turned on, the voltage applied to the liquid crystal capacitor Clc and the auxiliary capacitor Cst should be maintained even after the TFT is turned off, but the parasitic capacitance Cgd between the gate electrode and the drain electrode is maintained. Due to this, the voltage applied to the pixel electrode causes distortion. The distorted voltage is called a kickback voltage, and the kickback voltage ΔV is obtained by the following equation.

Here, ΔVg means the amount of change in the gate voltage (Vg _on- Vg _off ).

This voltage distortion always acts in the direction of lowering the voltage of the pixel electrode regardless of the polarity of the data voltage, which is illustrated in FIG. 2.

In Fig. 2, Vg, Vd, and Vp represent the gate voltage, the data voltage, and the voltage of the pixel electrode, respectively, and Vcom and ΔV represent the common electrode voltage (common voltage) and kickback voltage, respectively. As shown by a dotted line in Fig. 2, in an ideal TFT-LCD, when the gate voltage Vg is on, the data voltage Vd is applied to the pixel electrode to maintain the data voltage even when the gate voltage is turned off. In the LCD, as shown by the solid line of FIG. 2, in the portion where the gate voltage is changed, the pixel voltage is lowered by the kickback voltage due to the kickback voltage ΔV.

Therefore, the maximum data voltage applied when driving each cell of the liquid crystal requires a voltage higher than the operating range of the liquid crystal cell, and in order to apply the liquid crystal voltage having the same magnitude as that of the liquid crystal voltage applied in the odd frame during the inversion driving, even in the even frame. The common voltage considering the kickback effect by the parasitic capacitance of the TFT should be applied to the common electrode.

In this case, a design in which the kickback voltage ΔV is optimized is required so that the kickback voltage cannot be adjusted by one common voltage. To this end, the parasitic capacitance of the TFT should be minimized and the accumulation capacity should be designed large enough.

In addition to the kickback effect due to the parasitic capacitance, the kickback voltage may also vary depending on the position of the screen due to the delay resistance of the wiring.

In general, since the gate line and the data line have resistances and parasitic capacitances, there is a delay of the gate voltage and the data voltage by the time constant determined by the product of these two values, and the signal delay increases the size of the liquid crystal panel. The bigger it gets.

That is, the farther the gate voltage is from the input terminal, that is, the larger the delay of the gate signal is, the smaller the change amount of the gate voltage (ΔVg in Equation 1) is. As a result, the kickback voltage ΔV becomes smaller.

As described above, since kickback voltages having different values are generated over the entire liquid crystal panel, even if the common voltage is constantly applied, the voltages charged to the pixels in units of frames are not maintained because the voltages are not maintained at the center of the pixel voltages. And thus flicker occurs. This phenomenon becomes even more problematic as the screen of the liquid crystal display becomes larger and the gate lines become longer.

In particular, since the driving distance of the TFT is relatively long in a large screen liquid crystal display device, the width / length ratio of the TFT channel must be increased to improve the TFT performance or increase the gate-on voltage. do. However, in order to increase the gate-on voltage, reducing the L (length) of the channel below the minimum specification determined by the process capability increases the defects such as channel short.

In addition, since a TFT in a high-resolution liquid crystal panel needs to charge a load capacitance (liquid crystal capacitance and auxiliary capacitance) for a relatively short driving time, the W / L ratio of the channel is increased, and parasitic capacitance is also increased. The voltage drop becomes large.

Therefore, the technical problem to be achieved by the present invention is to make the kickback voltage compensation over the entire liquid crystal panel.

In particular, the present invention is to ensure that the kickback voltage compensation is uniformly performed over the entire screen even in a large screen liquid crystal display.

In accordance with an aspect of the present invention, a liquid crystal display device includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, and a plurality of dummy gate lines arranged in parallel with the gate lines. And a switching element formed at an area where the gate line and the data line cross each other, a switching element connected to the gate line and the data line, a pixel electrode connected to the switch element, and a dummy connected to the pixel electrode and connected to the dummy gate line. A liquid crystal panel including a plurality of pixels including a switch; A scan driver supplying a gate voltage to the gate line and the dummy gate line; And a data driver for supplying a corresponding gray voltage to the data line according to an applied data signal.

Here, the gate voltages applied to the gate line and the dummy gate line have inverted values.

The dummy switch may include a TFT in which a gate electrode is connected to the dummy gate line, and a source electrode and a drain electrode are connected to the pixel electrode. In this case, the width and length of the channel between the source electrode and the drain electrode of the switching element are referred to as W1 and L1, respectively, and the width and the length of the channel between the source electrode and the drain electrode of the dummy switch are referred to as W2 and L2, respectively. In this case, it is preferable that the relationship of W2 = 0.5W1 and L1 = L2 is established.

In addition, a method of driving a liquid crystal display according to another aspect of the present invention includes a plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a plurality of dummy gate lines arranged in parallel with the gate lines, A switching element formed in an area where the gate line and the data line cross each other, a switching element connected to the gate line and a data line, a pixel electrode connected to the switch element, and a dummy switch connected to the pixel electrode and connected to the dummy gate line, respectively. A method of driving a liquid crystal display device having a plurality of pixels, the method comprising: supplying a data voltage to the data line; And simultaneously supplying a gate voltage to the gate line and the dummy gate line, and the gate voltages applied to the gate line and the dummy gate line are inverted from each other.                     

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention in detail.

3 is an equivalent circuit diagram of a pixel for kickback voltage compensation according to an exemplary embodiment of the present invention.

As shown in FIG. 3, each pixel of the liquid crystal display according to the exemplary embodiment of the present invention has a gate electrode, a source electrode, and a drain electrode respectively disposed on the gate line Gn, the data line Dm, and the pixel electrode P. A liquid crystal capacitor Clc and an auxiliary capacitor Cst formed between the connected TFT and the pixel electrode P and the common electrode Com. In particular, the drain electrode and the source electrode are connected to the pixel electrode P. It further includes a dummy switch (DS) made of a TFT. The dummy switch DS is connected to a dummy gate line / Gn formed separately.

Here, parasitic capacitances of Cgs1 and Cgs2 are formed between the TFT, the gate electrode and the source electrode of the dummy switch DS, and parasitic fluxes of Cgd1 and Cgd2 are formed between the gate electrode and the drain electrode, respectively.

On the other hand, the gate signals inverted to each other are supplied to the gate electrode of the TFT and the gate electrode of the dummy switch DS. That is, as shown in FIG. 3, when a high level gate signal is supplied to the gate electrode of the TFT through the gate line Gn, the gate electrode of the dummy switch DS is connected to the gate electrode of the dummy switch DS through the dummy gate line / Gn. The gate signal is supplied.

Therefore, even if the pixel voltage Vp drops due to the parasitic capacitance Cgd1 of the TFT, the compensation voltage is driven by the dummy switch DS driven by the gate signal having a value inverted with the gate signal applied to the TFT. The applied and dropped pixel voltage Vp is compensated.

4 shows the principle that the pixel voltage drop is compensated by the TFT and the dummy switch.

As shown in FIG. 4, the drop of the pixel voltage Vp charged to the pixel electrode is caused by the parasitic capacitance Cgd1 formed between the gate electrode and the drain electrode of the TFT to which the low-level gate signal Gn is applied. Although generated, the pixel voltage Vp is pulled up by the parasitic capacitance Cgd2 formed between the gate electrode and the drain electrode of the dummy switch DS to which the high level gate signal / Gn is applied. Vp) compensation is made.

In this case, the pixel width compensation may be performed by appropriately adjusting the channel width W2 between the source electrode and the drain electrode of the dummy switch DS. Specifically, when the width and length of the channel between the source electrode and the drain electrode of the TFT are W1 and L1, respectively, and the width and length of the channel between the source electrode and the drain electrode of the dummy switch DS are W2 and L2, respectively, The dummy switch DS is configured such that a relationship of W2 = 1 / 2W1 and L1 = L2 is established. According to this relationship, when the high level signal is applied to the gate electrode of the dummy switch DS and the dummy switch DS is turned on, the signal applied through the gate electrode of the dummy switch DS is applied to the source electrode and the drain electrode. Since the width W2 of the channel between the source electrode and the drain electrode of the dummy switch DS is smaller than the channel width W1 of the TFT by being supplied to the pixel electrode through the pixel electrode, the parasitic capacitance of the TFT The generated pixel voltage Vp drop can be sufficiently compensated.

5 illustrates the overall structure of a liquid crystal display according to an exemplary embodiment of the present invention having such a pixel structure.

As shown in FIG. 5, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 1, a scan driver 2, a data driver 3, a voltage generator 4, and a timing controller 5. ).

The timing controller 5 is an R (red), G (green), B (blue) data signal, a vertical synchronization signal (Vsync) that is a frame discrimination signal, and a row discrimination signal from a graphic controller (not shown) outside the LCD module. The horizontal synchronization signal Hsync and the clock signal MCLK are provided to output a digital signal for driving the scan driver 2 and the data driver 3.

The driving voltage generator 4 outputs the gate-on signal voltage Von, the gate-off signal voltage Voff, and the common voltage Vcom serving as a reference for the data voltage in the TFT to the scan driver 2.

The scan driver 2 includes a shift register (not shown), a level shifter (not shown), a buffer (not shown), and the like, and receives a digital signal from the timing controller 5, and the driving voltage generator The voltages Von, Voff, and Vcom are received from (4) to open the path so that voltage values to be applied to each pixel on the LCD panel are transferred to the corresponding pixel. That is, the gate-on voltage synchronized with the digital signals (CPV signal and 0E signal) output from the timing controller 5 is sequentially applied to the gate lines.

The data driver 3 is driven by a signal output from the timing controller 5 to apply a data voltage to all data lines in synchronization with the driving of the scan driver 2.

In the liquid crystal panel 1, a data line transferring a data voltage from the data driver 3 and a gate line transferring a gate voltage from the scan driver 2 are formed to cross each other, and the gate line and the data line cross each other. A pixel having a structure as shown in FIG. 3 is formed.

In particular, in the exemplary embodiment of the present invention, dummy gate lines are separately formed in each liquid crystal panel so that a signal having a value inverted from the gate signal applied to the TFT of each pixel is supplied to the dummy switch DS. Therefore, the scan driver 2 generates two gate signals having inverted values and applies them to one pixel.

Next, an operation of the liquid crystal display according to the exemplary embodiment of the present invention having such a structure will be described.

External signal sources, for example, R (red), G (green), and B (blue) data signals from a graphic control unit (not shown) outside the LCD module, a vertical synchronization signal (Vsync) that is a frame discrimination signal, and a row discrimination signal When the horizontal sync signal Hsync and the clock signal MCLK are provided, the timing controller 5 outputs a digital signal for driving the scan driver 2 and the data driver 3.

The scan driver 2 provides the gate-on voltage Von provided from the driving voltage generator 4 to the TFT of each pixel so that the data voltage can be applied to the pixels according to the digital signal provided from the timing controller 5. To turn it on selectively. In this case, the scan driver 2 provides the gate-on voltage Von to the TFT of each pixel, and at the same time, the dummy gate voltage Voff having a value inverted from the gate-on voltage Von by the dummy switch DS of each pixel. ).

The data driver 3 transfers the voltage into the liquid crystal panel 1 by selecting a voltage corresponding to each data when a signal instructing the liquid crystal panel 1 to lower the image data stored in each shift register is received. do.

As a result, the data voltage supplied from the data driver 3 through the TFT of each pixel is provided to the pixel electrode to perform image display, and at this time, the dummy switch of each pixel is kept off.

Next, when the gate-off voltage Voff is provided to the TFT of each pixel by the scan driver 2, the dummy gate voltage Von having a value inverted with the gate-off voltage Voff is supplied to the dummy switch of each pixel. to provide.

Therefore, even if the parasitic capacitance Cgd1 is generated due to the turning-off of the TFT of each pixel to generate the pixel voltage drop ΔVp, the source electrode of the dummy switch DS is turned on by the turn-on operation of the dummy switch DS. As the charge applied through the drain electrode is supplied to the pixel electrode, voltage compensation corresponding to voltage enhancement (ΔVp) of the pixel voltage is achieved.

Therefore, the pixel voltage is maintained unchanged even when the gate voltage applied to the TFT is turned on / off, thereby preventing flickering due to the kickback voltage.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and of course, various other modifications and changes are possible.

As described above, according to the present invention, the kickback voltage generated at each pixel of the liquid crystal panel is removed, thereby preventing flicker caused by the kickback voltage. Therefore, the image quality of the liquid crystal display device can be remarkably improved.

In addition, the driving factor can be minimized in the afterimage caused by the minimum kickback voltage.

Claims (5)

A plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a plurality of dummy gate lines arranged in parallel with the gate lines, and formed in a region where the gate lines and the data lines intersect, respectively; A liquid crystal panel including a plurality of pixels including a switching element connected to a data line, a pixel electrode connected to the switch element, and a dummy switch connected to the pixel electrode and connected to the dummy gate line; A scan driver supplying a gate voltage to the gate line and the dummy gate line; And A data driver supplying a corresponding gray voltage to the data line according to an applied data signal Liquid crystal display comprising a. The method of claim 1, And a gate voltage applied to the gate line and the dummy gate line is inverted from each other. The method of claim 1, And the dummy switch comprises a TFT having a gate electrode connected to the dummy gate line, and a source electrode and a drain electrode connected to the pixel electrode. The method of claim 3, When the width and length of the channel between the source electrode and the drain electrode of the switching element are called W1 and L1, respectively, and the width and the length of the channel between the source electrode and the drain electrode of the dummy switch are called W2 and L2, respectively, W2 The relationship of = 0.5W1 and L1 = L2 is established. A plurality of gate lines, a plurality of data lines insulated from and intersecting the plurality of gate lines, a plurality of dummy gate lines arranged in parallel with the gate lines, and formed in a region where the gate lines and the data lines intersect, respectively; A driving method of a liquid crystal display device having a plurality of pixels including a switching element connected to a data line, a pixel electrode connected to the switch element, and a dummy switch connected to the pixel electrode and connected to the dummy gate line. Supplying a data voltage to the data line; Simultaneously supplying a gate voltage to the gate line and the dummy gate line And a gate voltage applied to the gate line and the dummy gate line to be inverted with each other.

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