KR101123075B1 - Method of compensating kickback voltage and liquid crystal display using the save - Google Patents

Abstract

The present invention relates to a kickback voltage compensation method and a liquid crystal display device to reduce flicker and afterimage using the same.

Kickback voltage compensation method of the present invention comprises the steps of setting a plurality of blocks each comprising a plurality of liquid crystal cells; Measuring a kickback voltage at each of the liquid crystal cells of the block at the left end of the blocks and the liquid crystal cell of the block at the right end of the blocks; Calculating kickback voltages of blocks existing between the block at the left end and the block at the right end through approximation using the measured kickback voltage; Adding kickback voltages of the blocks to at least one of a liquid crystal pixel voltage and a common voltage of the liquid crystal cell, and measuring the kickback voltage in each of the block at the left end and the block at the right end, Measuring a kickback voltage in one liquid crystal cell present in the left end block; And measuring a kickback voltage in one liquid crystal cell present in the block at the right end.

Description

Kickback Voltage Compensation Method and Liquid Crystal Display Using Them {METHOD OF COMPENSATING KICKBACK VOLTAGE AND LIQUID CRYSTAL DISPLAY USING THE SAVE}             

1 is an equivalent circuit diagram of a unit pixel of a general liquid crystal display device.

2 is a waveform diagram showing a kickback voltage.

3 is a diagram illustrating a kickback voltage differently displayed at each position of a liquid crystal display panel.

4 is a flowchart illustrating step by step a control procedure of a kickback voltage compensation method according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an example of a kickback voltage compensation method according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

7 illustrates vertical and horizontal block indication signals.

FIG. 8 is a circuit diagram illustrating the kickback voltage compensation circuit of FIG. 6.

9 is a waveform diagram illustrating a change in liquid crystal pixel voltage due to a kickback compensation voltage.                 

10 is a block diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 11 is a diagram illustrating a common electrode of the liquid crystal display panel illustrated in FIG. 10.

FIG. 12 is a circuit diagram illustrating the kickback voltage compensation circuit shown in FIG. 10 in detail.

13 is a waveform diagram illustrating a change in a common voltage due to a kickback compensation voltage.

<Explanation of symbols for main parts of drawing>

11 pixel electrode 12 common electrode

50, 90: timing controller 51, 91: data driving circuit

52, 92: kickback voltage compensation circuit 53, 93: gate driving circuit

54, 94: liquid crystal display panel 55, 95: driving voltage generator

71 AND gate 72 switch element

73, 113: adder 74, 114: buffer

75, 115: Kickback Voltage Generator

The present invention relates to a kickback voltage compensation method and a liquid crystal display device to reduce flicker and afterimage using the same.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

A thin film transistor for driving the liquid crystal cell at the intersection of the gate line GL and the data line DL and crossing the gate line GL and the data line GL on the lower glass substrate of the liquid crystal display panel as shown in FIG. 1. (Thin Film Transistor; hereinafter referred to as "TFT") is formed. In addition, a storage capacitor is formed in the liquid crystal display panel to maintain the voltage of the liquid crystal cell. In FIG. 1, Clc is equivalent to the capacitance of the liquid crystal cell, and Cst is equivalent to the storage capacitor Cst.

When the data voltage is applied to the pixel electrode 11 and the common voltage Vcom is applied to the common electrode 12 formed on the upper glass substrate, the liquid crystal cell is transmitted while the arrangement of the liquid crystal molecules is changed by an electric field applied to the liquid crystal layer. It controls the amount of light or blocks the light. The data voltage is supplied at a gamma voltage preset according to the driving voltage characteristic of the liquid crystal cell.

2 illustrates a scan pulse SCP supplied to the gate line GL and a voltage Vlc charged in the liquid crystal cell.

Referring to FIG. 2, the scan pulse SCP is set to a gate high voltage Vgh set as a voltage for turning on a TFT, and a voltage for turning off the TFT. Swing between the gate low voltage (Vgl). During the scanning period in which the scan pulse SCP maintains the gate high voltage Vgh, the liquid crystal cell Vlc charges the data voltage Vdata supplied as the gamma voltage and charges the charged voltage to the storage capacitor Cst. It is maintained at the set voltage for a certain time.

If the voltage of the same polarity is continuously applied to the liquid crystal cell, the liquid crystal and the display image deteriorate. For this reason, the liquid crystal display drives the liquid crystal cell with an AC data voltage whose polarity is periodically reversed. The polarity of the data voltage is reversed every frame around the common voltage Vcom applied to the common electrode 12.

However, the kickback voltage or the feed-through voltage (ΔVp) generated by the parasitic capacitance of the TFT serves as a major deterrent to the image quality of the liquid crystal display. The kickback voltage DELTA Vp is defined by Equation 1 below.

Here, 'Cgd' is a parasitic capacitance formed between the gate terminal of the TFT connected to the bar gate line GL and the drain terminal of the TFT connected to the pixel electrode 11 of the liquid crystal cell as shown in FIG. Von-Voff is a difference voltage between the gate high voltage Vgh and the gate low voltage Vgl of the scan pulse SCP. Von corresponds to the gate high voltage Vgh and Voff corresponds to the gate low voltage Vgl. do.

Due to the kickback voltage, a voltage applied to the pixel electrode 11 of the liquid crystal cell is changed, causing flicker and an afterimage on the display image. For example, if the polarity of the data is inverted at 60 Hz, the difference in luminance occurs between the radix frame and the even frame due to the kickback voltage, and the 30 Hz flicker appears on the display image. (DC offset) is applied to shift the voltage vs. transmittance characteristic of the liquid crystal cell, resulting in afterimage sticking.

In addition, the kickback voltage may be measured in the liquid crystal cell to compensate the kickback voltage, but the kickback voltage is not the same in all the liquid crystal cells disposed in the liquid crystal display panel, and thus it is impossible to optimize the kickback voltage. This is because the gate high voltage Vgh applied to the TFTs varies depending on the position from the gate driving circuit due to the RC delay due to the wiring length of the gate line GL, and the electrostatic discharge of the liquid crystal cells depends on the position from the data driving circuit. This is because the capacity value is different. In order to measure the kickback voltage depending on the position of the liquid crystal display panel for each liquid crystal cell, a test pad needs to be added corresponding to each liquid crystal cell, and there is no design margin therefor.

Accordingly, it is an object of the present invention to provide a kickback voltage compensation method for compensating for each of the different kickback voltages according to the position of a liquid crystal display panel.

Another object of the present invention is to provide a liquid crystal display device which can reduce flicker and afterimage by using the kickback voltage compensation method.

In order to achieve the above object, the kickback voltage compensation method according to an embodiment of the present invention comprises the steps of setting a plurality of blocks each comprising a plurality of liquid crystal cells; Measuring a kickback voltage at each of the liquid crystal cells of the block at the left end of the blocks and the liquid crystal cell of the block at the right end of the blocks; Calculating kickback voltages of blocks existing between the block at the left end and the block at the right end through approximation using the measured kickback voltage; Adding kickback voltages of the blocks to at least one of a liquid crystal pixel voltage and a common voltage of the liquid crystal cell, and measuring the kickback voltage in each of the block at the left end and the block at the right end, Measuring a kickback voltage in one liquid crystal cell present in the left end block; And measuring a kickback voltage in one liquid crystal cell present in the block at the right end.

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Computing the kickback voltage of the blocks existing between the block of the left end and the block of the right end by using the measured kickback voltage, the kickback voltage measured in the block of the left end to the left end Matching the kickback voltages of the remaining liquid crystal cells; Mapping the kickback voltage measured in the right end block to kickback voltages of the remaining liquid crystal cells in the right end; Making the number of factors of the kickback voltage measured in the block of the left end larger while the block closer to the block of the left end increases the number of factors of the kickback voltage measured in the block of the right end; Making the number of factors of the kickback voltage measured in the block at the right end of the block closer to the right end of the block increases while increasing the number of factors of the kickback voltage measured in the block at the left end of the block; Computing the kickback voltage in each of the blocks as an average value through the matrix operation.

A liquid crystal display device according to the present invention comprises: a liquid crystal display panel having m × n (where m and n are integers) liquid crystal cells, a pixel electrode and a common electrode for applying an electric field to the liquid crystal cells; A data driver circuit for supplying a liquid crystal pixel voltage supplied to the pixel electrode; A driving voltage generation circuit for supplying a common voltage to the common electrode; An approximation using the kickback voltage measured in each of the block at the left end and the block at the right end of the plurality of blocks each including j × k (where j and k are integers smaller than m and n), respectively A kickback voltage generation circuit configured to generate kickback compensation voltages of the blocks by calculating kickback voltages of blocks existing between the block at the left end and the block at the right end; And a kickback compensation circuit for adding a kickback compensation voltage from the kickback voltage generating circuit to at least one of the liquid crystal pixel voltage and the common voltage.

The liquid crystal display further includes a control signal generation circuit for generating a control signal indicating the size of the block.

The kickback compensation circuit adds the same kickback voltage to the liquid crystal pixel voltages supplied to the liquid crystal cells in the same block in response to the control signal.

The control signal includes a horizontal control signal indicating a horizontal length of the block; And a vertical control signal indicative of the longitudinal length of the block.

The kickback compensation circuit includes: an AND gate for performing an AND operation on the horizontal control signal and the vertical control signal; A switch element outputting the kickback voltage in response to an output of the AND gate; And an adder for adding a kickback voltage from the switch element and the liquid crystal pixel voltage.

The common electrode is divided into a plurality.

Each of the divided common electrodes is supplied with a common voltage to which different kickback compensation voltages are added.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 13.

In Equation 1, since the capacitance Clc of the liquid crystal cell is different depending on the vertical axis of the liquid crystal display panel, that is, the position on the Y axis, it can be replaced by the Y-axis variable, and Von, the turn-on voltage of the TFT, It depends on the horizontal axis, that is, the position on the X axis. This is because when the data voltage is supplied in the vertical direction, the liquid crystal cells are connected in parallel between the data line and the common electrode so that the liquid crystal cells close to the data driving circuit have a relatively large capacitance value, while the liquid crystal cells far from the data driving circuit are provided. This is because the capacitance value thereof is relatively small, and Von becomes smaller due to the delay of Von applied to the TFT far from the gate driving circuit compared to the TFT close to the gate driving circuit due to the RC delay.

Equation 2 below assumes that m x n liquid crystal cells are arranged in a matrix type on the liquid crystal display panel, and that the data driving circuit is provided on the upper side of the liquid crystal display panel and the gate driving circuit is provided on the left side of the liquid crystal display panel. In Equation 1, "Clc" is substituted with "Clc (x, n)" as the Y-axis variable and "Von" with "Von (m, y) as the X-axis variable, where Clc ( x, n) is the capacitance of an arbitrary nth liquid crystal cell on the X axis, and Von (m, y) is the gate high voltage Vgh applied to the TFT connected to any mth liquid crystal cell on the Y axis.

Since the capacitance of the liquid crystal cells decreases farther from the data driving circuit, the bar kickback voltage Vk, which can be seen in Equation 2, becomes larger toward the left side of the LCD panel in FIG. 3 and increases toward the left side of the LCD panel. Therefore, when the kickback voltage Vk is measured at each position of the liquid crystal display panel, the kickback voltage Vk (x0, n) of the lower left liquid crystal cell is determined based on the point a in the center> Vk (x0, y0)>> The kickback voltage Vk (m, y0) of the upper right liquid crystal cell is different at each position of the liquid crystal display panel.

4 shows step by step the control procedure of the kickback voltage compensation method according to an embodiment of the present invention.

Referring to FIG. 4, in the kickback voltage compensation method according to the present invention, a block including j × k (where j and k are integers of 2 or more) liquid crystal cells is set, and the blocks are m × formed in the liquid crystal display panel. The n liquid crystal cells are virtually partitioned. (S1) Hereinafter, a kickback voltage compensation method according to the present invention will be described with reference to FIG. 5 with assuming j and k as "2".                     

Subsequently, in the kickback voltage compensation method according to the present invention, the kickback voltage Vk is measured in the liquid crystal cells under measurement of the first block BL1 at the left end and the fifth block BL5 at the right end in FIG. 5. 0,0) and Vk (8,0)) are measured, respectively. (S1) This measurement method applies a test data voltage to a unit liquid crystal cell and is a difference between the voltage of the liquid crystal cell and the applied voltage lowered by the parasitic capacitance of the TFT. Obtained, any known measuring method is possible.

의 행렬(Matrix)의 대표값 즉, (Vk5×Vk1)-(Vk1×Vk1)의 평균값으로, 제3 블록(BL3)의 킥백전압(Vk3)은

의 행렬의 대표 값 즉, (Vk5×Vk5)-(Vk1×Vk1)에 대한 평균값으로 산출된다. 그리고 제4 블록(BL4)의 킥백전압(Vk4)은

의 행렬의 대표값 즉, (Vk5×Vk5)-(Vk5×Vk1)에 대한 평균값이다.In the kickback voltage compensation method according to the present invention, the kickback voltage Vk1 measured in the unit liquid crystal cell of the first block BL1 is replaced with the kickback voltages of other liquid crystal cells included in the first block BL1, and the fifth block. After replacing the kickback voltage Vk5 measured in the unit liquid crystal cell of BL5 with the kickback voltages of the other liquid crystal cells included in the fifth block BL5, the first block BL1 and the fifth block BL5 Based on the kickback voltages Vk1 and V5, the kickback voltages of the second to fourth blocks BL2, BL3, and BL4 existing between the first block BL1 and the fifth block BL5 are approximated (S3). In the approximation of the second to fourth blocks BL2, BL3, and BL4, first, the closer to the first block BL1, the greater the number of factors of the kickback voltage VK1 of the first block BL1, The number of factors of the kickback voltage VK5 of the five blocks BL5 is made relatively small. The closer to the fifth block BL5, the greater the number of factors of the kickback voltage VK5 of the fifth block BL5, while the number of factors of the kickback voltage VK1 of the first block BL1 is relatively smaller. do. Therefore, the kickback voltage Vk2 of the second block BL2 is

The kickback voltage Vk3 of the third block BL3 is the representative value of the matrix Matrix, that is, the average value of (Vk5 × Vk1) − (Vk1 × Vk1).

It is calculated as a representative value of the matrix of ie, (Vk5 x Vk5)-(Vk1 x Vk1). The kickback voltage Vk4 of the fourth block BL4 is

Representative values of the matrix, i.e., average values for (Vk5 x Vk5)-(Vk5 x Vk1).

In the kickback voltage compensation method according to the present invention, steps S1 to S3 are repeated for all blocks in the liquid crystal display panel to approximate the kickback voltages of all blocks by matrix operation using dithering. In the kickback voltage compensation method according to the present invention, the kickback voltage of each block obtained in steps S1 to S3 is supplied to the liquid crystal pixel voltage, that is, the analog gamma voltage or the common electrode of the liquid crystal cell, as the kickback compensation voltage. The kickback voltage is compensated by adding to the common voltage.

The kickback voltage compensator according to the present invention can be implemented as an integrated circuit (IC) by programming the steps S1 to S3, and also stores the kickback compensation voltage for each block in a lookup table and uses a lookup table and an adder. The kickback voltage is compensated by synchronizing the kickback compensation voltage of each block with data supplied to the block.

6 schematically shows a liquid crystal display according to a first embodiment of the present invention.

Referring to FIG. 6, in the liquid crystal display according to the present invention, m × n liquid crystal cells are arranged in a matrix type, and m data lines D1 to Dm and n gate lines G1 to Gn intersect each other. A liquid crystal display panel 54 having a TFT formed at an intersection thereof, a data driving circuit 51 for supplying liquid crystal pixel voltage as data to the data lines D1 to Dm of the liquid crystal display panel 54, and A kickback voltage compensation circuit 52 for adding the set kickback compensation voltages to the liquid crystal pixel voltages, a gate driving circuit 53 for supplying scan signals to the gate lines G1 to Gn, and a liquid crystal display panel; A driving voltage generator 55 for generating driving voltages supplied to the 54 and a timing controller 50 for controlling the data driving circuit 51, the gate driving circuit 53, and the kickback voltage compensation circuit 52. It is provided.

In the liquid crystal display panel 54, liquid crystal is injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal display panel 54 cross each other. The TFT formed at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn has a liquid crystal pixel voltage on the data lines D1 to Dn in response to a scan signal from the gate lines G1 to Gn. Is supplied to the liquid crystal cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the corresponding gate lines G1 to Gn, and the source electrodes are connected to the corresponding data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal display panel 54. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 54, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner side of the liquid crystal display panel 54 in contact with the liquid crystal. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell and the common electrode line (not shown) to maintain a constant voltage of the liquid crystal cell. do.

The data driving circuit 51 converts the digital video data RGB into an analog gamma voltage corresponding to the gray level value of the data in response to the data control signal DDC from the timing controller 50 and converts the analog gamma voltage into a liquid crystal. The pixel voltage is supplied to the data lines D1 to Dm as the pixel voltage.

The kickback voltage compensation circuit 52 stores the kickback compensation voltage for each block of the liquid crystal display panel obtained by the kickback voltage compensation method described above in response to the horizontal and vertical block command signals De and Ge from the timing controller 50. The kickback voltage is compensated for each block by adding to the liquid crystal pixel voltage from the driving circuit 51.

The gate driving circuit 53 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 50 to supply the data. Select the horizontal line.

The driving voltage generator 55 boosts or decompresses a VCC voltage supplied from a system (not shown) to generate a VDD voltage, a gamma voltage Vgamma1 to Vgamman, a gate high voltage Vgh, and a gate low voltage A voltage supplied to the liquid crystal display panel 54 such as Vgl and the common voltage Vcom is generated. The VDD voltage and gamma voltages Vgamma1 to Vgamman are supplied to the data driving circuit 51 as analog gamma voltages.

The timing controller 50 uses the vertical / horizontal synchronization signal and the clock signal to control the gate control signal GDC for controlling the gate driving circuit 53 and the data control signal DDC for controlling the data driving circuit 51. And a horizontal and vertical block command signal (De, Ge) for controlling the kickback voltage compensation circuit (52). The timing controller 50 rearranges the digital video data RGB to supply the data driving circuit 51. The horizontal and vertical block command signals De and Ge indicate horizontal and vertical sizes of 2x2 blocks as shown in FIG. 7. The timing controller 50 divides the main pixel clock (Main Pixel CLK) or Tclk supplied from a system (not shown) into two to generate a horizontal block indication signal (De), and the CPV clock (CLK Per Vertical: Tvclk) from the system. Is divided by two to generate a vertical block instruction signal Ge of one horizontal period 1H.

8 shows the kickback voltage compensation circuit 52 in detail.

Referring to FIG. 8, the kickback voltage compensation circuit 52 includes an AND gate 71, a switch element 72 having a control terminal connected to an output signal of the AND gate 71, a liquid crystal pixel voltage Vdata, and a switch element ( And an adder 73 for generating the kickback compensation data voltage CVdata by adding the output of the output 72, and a kickback voltage generator 75 for each block. The output terminal of the adder 73 is connected with a buffer 74 and a capacitor C for suppressing the variation of the output voltage.

The AND gate 71 performs an AND operation on the horizontal and vertical horizontal and vertical block indication signals De and Ge to generate a high logic output in a block of size 2 × 2.

The switch element 72 is turned on in response to the output signal of the AND gate 71 so that the same kickback compensation voltage Vk is applied to each of the liquid crystal pixel voltages supplied to the 2x2 liquid crystal cells in the same block. The kickback compensation voltage Vk is output for each block in units of blocks.

The adder 73 adds the kickback compensation voltage Vk for each block from the switch element 72 to the liquid crystal pixel voltage Vdata supplied from the data driving circuit 51 to output the kickback compensation data voltage CVdata. This kickback compensation data voltage CVdata is supplied to the data line DL via the buffer 74 and charged to the liquid crystal cells in each block. The kickback compensation data voltage CVdata reversely compensates for the reduction of the liquid crystal cell voltage Vdata, that is, the kickback voltage as shown in FIG. 9.

The kickback voltage generator 75 selectively outputs the kickback voltage for each block obtained by the approximation of FIG. 4 in response to the vertical and horizontal block command signals De and Ge.

10 schematically illustrates a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 10, in the liquid crystal display according to the present invention, m × n liquid crystal cells are arranged in a matrix type, and m data lines D1 to Dm and n gate lines G1 to Gn intersect each other. A liquid crystal display panel 94 having a TFT formed at an intersection thereof, a data driving circuit 91 for supplying liquid crystal pixel voltage as data to the data lines D1 to Dm of the liquid crystal display panel 94, and a gate line. Gate driving circuit 93 for supplying scan signals to the signals G1 to Gn, a driving voltage generator 95 for generating driving voltages supplied to the liquid crystal display panel 94, and a predetermined kickback for each block A kickback voltage compensation circuit 92 for adding the compensation voltage to the common voltage Vcom, and a timing controller 90 for controlling the data driving circuit 91 and the gate driving circuit 93 are provided.

In the liquid crystal display panel 94, liquid crystal is injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal display panel 94 cross each other. The TFT formed at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn has a liquid crystal pixel voltage on the data lines D1 to Dn in response to a scan signal from the gate lines G1 to Gn. Is supplied to the liquid crystal cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the corresponding gate lines G1 to Gn, and the source electrodes are connected to the corresponding data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, and a common electrode (not shown) are formed on the upper glass substrate of the liquid crystal display panel 94. The common electrode is divided into four as shown in FIG. 11 to include four common electrodes 100A to 100D, and the common electrodes 100A to 100D are different from each other to which the kickback compensation voltage from the kickback voltage compensation circuit 92 is added. Common voltages VcomA to VcomD are applied. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 94, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface of the liquid crystal display panel 94 in contact with the liquid crystal. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell and the common electrode line (not shown) to maintain a constant voltage of the liquid crystal cell. do.

The data driving circuit 91 converts the digital video data RGB into an analog gamma voltage corresponding to the gray level value of the data in response to the data control signal DDC from the timing controller 90 and converts the analog gamma voltage into a liquid crystal. The pixel voltage is supplied to the data lines D1 to Dm as the pixel voltage.

The gate driving circuit 93 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the gate control signal GDC from the timing controller 90 to supply the data. Select the horizontal line.                     

The driving voltage generator 95 boosts or decompresses a VCC voltage supplied from a system (not shown), thereby generating a gamma voltage (Vgamma1 to Vgamman), a gate high voltage (Vgh), and a gate low voltage (Vgamma1 to Vgamman) generated by a divided voltage of the VDD voltage and the VDD voltage. Vgl) and common voltage Vcom. The VDD voltage and gamma voltages Vgamma1 to Vgammann are supplied to the data driving circuit 91 as analog gamma voltages.

The kickback voltage compensating circuit 92 divides the liquid crystal display panel 94 into four quadrants corresponding to the four common electrodes 100A to 100B. Four other kickback compensation common voltages are generated. The kickback voltage compensation circuit 92 adds the four kickback compensation common voltages to the common voltage Vcom from the driving voltage generator 95 to optimize the common voltages VcomA to the quadrants of the liquid crystal display panel 94. VcomD). The kickback compensation voltage at each of the very small blocks compared to the four divided common electrodes 100A to 100D is obtained through the approximation of FIGS. 4 and 5.

The timing controller 90 uses a vertical / horizontal synchronization signal and a clock signal to control the gate control signal GDC for controlling the gate driving circuit 93 and the data control signal DDC for controlling the data driving circuit 91. Occurs.

12 shows the kickback voltage compensation circuit 92 in detail.

Referring to FIG. 12, the kickback voltage compensation circuit 92 includes an adder 113 and a kickback voltage generator 115 for adding kickback voltages VkA to VkD to a common voltage Vcom. The input / output terminals of the adder 73 are connected with buffers 74 and capacitors C1 and C2 for suppressing variations in output voltage.

The adder 113 adds the kickback compensation voltages Vk optimized for each quadrant in the four quadrants of the liquid crystal display panel to the common voltage Vcom from the driving voltage generator 95, thereby providing four kickback compensation common voltages VcomA to VcomD. ) The first kickback compensation common voltage VcomA is applied to the upper left end of the common electrode 100A in one quadrant through the silver dot as shown in FIG. 11, and the second kickback compensation common voltage VcomB is provided through the silver dot. It is applied to the upper right end of the common electrode 100B in two quadrants. The third kickback compensation common voltage VcomC is supplied to the lower left end of the common electrode 100C in three quadrants through the silver dots as shown in FIG. 11, and the fourth kickback compensation common voltage VcomD is the four quadrants through the silver dots. Is supplied to the lower right end of the common electrode 100C. The kickback compensation common voltages VcomA to VcomD reversely compensate for different kickback voltages in each quadrant of the liquid crystal display panel 94 as shown in FIG. 13.

The kickback voltage generator 115 generates optimized kickback voltages VkA to VkD in each quadrant of the liquid crystal display panel 94 based on the kickback voltage for each block obtained by the approximation of FIG. 4.

The kickback voltage compensation method and the liquid crystal display device using the same according to the present invention compensate for the kickback voltage when the gate line GL is applied to a liquid crystal display panel which can reduce the RC delay in the gate line GL by using a metal having a low specific resistance. The effect can be made larger.

As described above, the kickback voltage compensation method according to the present invention divides the liquid crystal cells of the liquid crystal display panel into blocks having a predetermined size, and calculates the kickback voltage by a dithering method or an approximation method through matrix operation in each block. By adding the star kickback voltage to the liquid crystal pixel voltage or the common voltage, each of the different kickback voltages can be optimally compensated according to the position of the liquid crystal display panel. The LCD according to the present invention can reduce flicker and afterimages by using the kickback voltage compensation method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the common voltage generator according to the present invention has been described as a circuit for generating a common voltage of a liquid crystal display device, in a display device other than the liquid crystal display device or other power supply device, the necessary voltage can be compensated according to temperature without difficulty of configuration. Can be. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

Setting a plurality of blocks each including a plurality of liquid crystal cells; Measuring a kickback voltage at each of the liquid crystal cells of the block at the left end of the blocks and the liquid crystal cell of the block at the right end of the blocks; Calculating kickback voltages of blocks existing between the block at the left end and the block at the right end through approximation using the measured kickback voltage; Adding kickback voltages of the blocks to at least one of a liquid crystal pixel voltage and a common voltage of the liquid crystal cell; Measuring a kickback voltage in each of the block at the left end and the block at the right end, Measuring a kickback voltage in one liquid crystal cell present in the left end block; Kickback voltage compensation method comprising the step of measuring the kickback voltage in one liquid crystal cell present in the block of the right end. delete The method of claim 1, Computing the kickback voltage of the blocks existing between the block of the left end and the block of the right end through the approximation using the measured kickback voltage, Mapping the kickback voltage measured in the left end block to kickback voltages of the remaining liquid crystal cells in the left end; Mapping the kickback voltage measured in the right end block to kickback voltages of the remaining liquid crystal cells in the right end; Making the number of factors of the kickback voltage measured in the block of the left end larger while the block closer to the block of the left end increases the number of factors of the kickback voltage measured in the block of the right end; Making the number of factors of the kickback voltage measured in the block at the right end of the block closer to the right end of the block increases while increasing the number of factors of the kickback voltage measured in the block at the left end of the block; Kickback voltage compensation method comprising the step of calculating the average of the kickback voltage in each of the blocks through a matrix operation. a liquid crystal display panel having m × n (where m and n are integers) liquid crystal cells, a pixel electrode and a common electrode for applying an electric field to the liquid crystal cells; A data driver circuit for supplying a liquid crystal pixel voltage supplied to the pixel electrode; A driving voltage generation circuit for supplying a common voltage to the common electrode; An approximation using the kickback voltage measured in each of the block at the left end and the block at the right end of the plurality of blocks each including j × k (where j and k are integers smaller than m and n), respectively A kickback voltage generation circuit configured to generate kickback compensation voltages of the blocks by calculating kickback voltages of blocks existing between the block at the left end and the block at the right end; And a kickback compensation circuit for adding a kickback compensation voltage from the kickback voltage generating circuit to at least one of the liquid crystal pixel voltage and the common voltage. The method of claim 4, wherein And a control signal generating circuit for generating a control signal indicating the size of the block. The method of claim 5, The kickback compensation circuit, And adding the same kickback voltage to the liquid crystal pixel voltages supplied to the liquid crystal cells in the same block in response to the control signal. The method of claim 5, The control signal is, A horizontal control signal indicating a horizontal length of the block; And a vertical control signal indicative of the longitudinal length of the block. The method of claim 7, wherein The kickback compensation circuit, An AND gate for performing an AND operation on the horizontal control signal and the vertical control signal; A switch element outputting the kickback voltage in response to an output of the AND gate; And an adder for adding a kickback voltage from said switch element and said liquid crystal pixel voltage. The method of claim 4, wherein The common electrode, Liquid crystal display characterized in that divided into a plurality. The method of claim 9, And a common voltage to which the kickback compensation voltages are added to each of the divided common electrodes.

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