JP3129913B2 - Active matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device using a liquid crystal or the like, in which each picture element is provided with an auxiliary capacitance element for assisting a picture element capacity.

[0002]

2. Description of the Related Art Conventionally, in a simple matrix type liquid crystal display device, a large number of scanning signal electrodes are formed on one substrate and a large number of display signal electrodes are formed on the other substrate in a direction orthogonal to the scanning signal electrodes. These substrates are opposed to each other via a liquid crystal layer. Such a simple matrix system is widely used as a liquid crystal display device of various matrix systems because of its simple structure and easy upsizing.

However, liquid crystal does not always have good responsiveness because the change in optical characteristics with respect to the voltage change is relatively gradual. Moreover, in the simple matrix method, as the number of scanning signal electrodes increases, the period during which the voltage of the display signal is applied to each picture element becomes shorter. Therefore, sufficient display contrast cannot be obtained by using this simple matrix type liquid crystal display device for a display such as a recent personal computer or multimedia device which requires a high resolution and moves a cursor at a high speed with a mouse or the like. . Further, the simple matrix method has a disadvantage that image quality is impaired because a linear pattern is easily generated by crosstalk. Therefore, an active matrix method has conventionally been used for a liquid crystal display device that requires high resolution and high-speed display.

The structure of the active matrix type liquid crystal display device will be described with reference to FIGS. Here, for simplicity of explanation, a simple 4 rows × 4
A liquid crystal display device with 16 picture elements in columns is shown.

[0005] As shown in FIG.
A matrix consisting of 4 rows × 4 columns surrounded by a chain line A
6 areas are arranged as picture elements. A total of four scanning signal lines Y1 to Y4 are laid one by one along each row of these picture elements, and a total of four display signal lines X1 to X4 are formed one by one along each column. Is laid. It should be noted that the numbers attached to the symbols of the scanning signal line Y and the display signal line X indicate the corresponding row numbers and column numbers, respectively.

Further, the liquid crystal panel 1 is provided with a scanning signal line driving circuit 2 and a display signal line driving circuit 3, and the scanning signal lines Y1 to Y4 are connected to the scanning signal line driving circuit 2, respectively. The display signal lines X1 to X4 are connected to the display signal line drive circuit 3, respectively. The scanning signal line driving circuit 2 is supplied with power from an ON voltage power supply circuit 4 and an OFF voltage power supply circuit 5 outside the liquid crystal panel 1. The ON voltage power supply circuit 4 is a power supply circuit for supplying a high voltage level ON voltage VON, and the OFF voltage power supply circuit 5 is
Although the voltage is sufficiently lower than ON, the level switches between a relatively high voltage and a relatively low voltage every horizontal scanning period.
The power supply circuit supplies the F voltage VOFF. The scanning signal line driving circuit 2 sequentially shifts the pulse in the shift register every horizontal scanning period, and switches the ON voltage VON and the OFF voltage VOFF by the level shifter according to the pulse, so that all the scanning signals are always The lines Y1 to Y4 are set to the OFF voltage VOFF, and the scanning signals are output as the ON voltage VON for each scanning signal line Y1 to Y4 in sequence for approximately one horizontal scanning period every vertical scanning period. The display signal line driving circuit 3 serially converts display signals sequentially supplied from the outside of the liquid crystal panel 1.
The signals are output to the respective display signal lines X1 to X4 by parallel conversion. At this time, the display signal line drive circuit 3 outputs the display signal as an oscillating voltage whose voltage level switches every horizontal scanning period.

Each of the picture elements is provided with a picture element capacitance CP, an auxiliary capacitance CS, and a thin film transistor SW. As shown in FIG. 4, the picture element capacitance CP is a capacity constituted by the picture element electrode EPA and the counter electrode EPB which are arranged to face each other, and the auxiliary capacitance CS is the first electrode ESA and the second electrode E
This is a capacitive element made of SB. In FIG. 3, for example, in the case of a picture element in the second row and the fourth column, the numbers of the row number and the column number indicating the arrangement of the picture element are referred to as a picture element capacitance CP24, an auxiliary capacitance CS24, and a thin film transistor SW24. Is appended to the sign. The thin film transistor SW of each pixel has a source connected to the display signal line X corresponding to the column of the pixel, and a drain connected to the pixel capacitance CP of the pixel.
And the first electrode ESA of the auxiliary capacitance CS. The gate of the thin film transistor SW is connected to a scanning signal line Y corresponding to the row of the picture element, and the scanning signal line Y is turned on at a high voltage level of the ON voltage V.
When it is turned on, the display signal line X and the pixel electrode EPA are electrically connected.
The connection between them is cut off regardless of the switching of the level of the FF voltage VOFF.

The counter electrode E of the picture element capacitance CP in each picture element
PB is commonly connected to a counter electrode power supply circuit 6 outside the liquid crystal panel 1. The counter electrode power supply circuit 6
The power supply circuit supplies a common electrode voltage VQ that switches between a relatively high voltage level and a relatively low voltage level every horizontal scanning period in synchronization with the F voltage power supply circuit 5. The second electrode ESB of the auxiliary capacitance CS in each of the picture elements in the first to third rows is connected to the respective scanning signal lines Y2 to Y4 corresponding to the adjacent second to fourth rows. Further, the second electrode ESB of the auxiliary capacitance CS in each picture element in the fourth row is connected to the same counter electrode power supply circuit 6 as the counter electrode of the picture element capacitance CP via the last row return line YR. When the second electrodes ESB of the picture elements in the first to third rows are connected to the nearest neighboring scanning signal lines Y2 to Y4, all the second
Compared with the case where the electrode ESB is connected to the OFF voltage power supply circuit 5, the counter electrode power supply circuit 6, and the like, the amount of wiring on the substrate can be significantly reduced.

In the liquid crystal panel 1, a picture element electrode substrate and a counter electrode substrate are actually arranged to face each other with a gap therebetween, and a liquid crystal is filled between them. The scanning signal line driving circuit 2 and the display signal line driving circuit 3, and the scanning signal lines Y1 to Y4, the last line return line YR, and the display signal lines X1 to X4 are all formed on the opposing surface of the pixel electrode substrate. Have been. Further, the thin film transistor SW and the auxiliary capacitance CS of each picture element are also formed on the opposing surface of the picture element electrode substrate. Thin film transistor SW
Is the scanning signal line Y on the opposing surface of the pixel electrode substrate.
[Thin Film Transisto] formed by a thin film of amorphous Si or the like at the intersection of
r]. The auxiliary capacitance CS is a capacitance element in which a first electrode ESA and a second electrode ESB are formed on a facing surface of a pixel electrode substrate via a ferroelectric material, and the capacitance of the pixel capacitance CP varies in a manufacturing process. Is formed to reduce the voltage drop by increasing the capacitance of the picture element as well as to reduce the occurrence of In the pixel capacitance CP, only the pixel electrode EPA is formed on the opposing surface of the pixel electrode substrate, and the opposing electrode EPB is formed on the opposing surface of the opposing electrode substrate. That is, the picture element electrode E
PA is composed of a transparent conductive film formed so as to cover the entire central portion of the picture element region for each picture element on the opposing surface of the picture element electrode substrate. Also, the counter electrode EPB
Is composed of a transparent conductive film formed so as to cover almost the entire opposing surface of the opposing electrode substrate in common for all picture elements. Therefore, between the pixel electrode EPA and the counter electrode EPB, as shown in FIG.
C is interposed, and matrix display is performed by controlling the light transmittance of the liquid crystal layer LC for each picture element. The picture element capacitance CP is composed of a conductive film in which the counter electrode EPA covers almost the entire opposing surface of the counter electrode substrate as described above. Is shown.

The operation of the liquid crystal display device having the above configuration will be described with reference to FIG. Here, VGA [Video Graphics] which is one of the display standards of a personal computer is used.
Array] standard. In this VGA standard,
1 V vertical scanning period TV constituting one field screen
(1/60 second) is a horizontal scanning period TH (3
1.8 μs). Actually, the effective screen is from 1H to 480H and the vertical blanking period TVR is from 481H onward. However, in this description, 4 rows × 4
Since the display devices in the columns are shown, only the 4H horizontal scanning period TH from the first H to the fourth H is set as an effective screen, and the remaining fifth and subsequent H is set as a vertical blanking period TVR.

Since the scanning signals on the scanning signal lines Y1 to Y4 are always at the OFF voltage VOFF, the thin film transistor SW is not turned on every horizontal retrace period THR assigned at the end of the horizontal scanning period TH. It alternates between high and low voltage levels. Also, the scanning signal line Y
The first scanning signal is the first H signal in the vertical scanning period TV.
, The ON voltage which is sufficiently higher than the OFF voltage VOFF
The voltage becomes VON, and the remaining scanning signal lines Y2 to Y4 also become the ON voltage VON in the second to fourth Hs, respectively. Accordingly, in the first to fourth Hs of each vertical scanning period TV, the thin film transistors SW11 to SW44 of each picture element are sequentially turned on for each of the first to fourth rows. However, for example, the period TON during which the scanning signal line Y1 is actually at the ON voltage VON
From time t1 at the start of the first H to time t2 at which the last horizontal retrace period THR of the first H starts,
This is a period slightly shorter than the entire horizontal scanning period TH of the first H. Then, after the time t2, the voltage returns to the OFF voltage VOFF again, and the voltage level switches to a small level by the time t3 when the first H ends.

The common electrode voltage VQ supplied by the common electrode power supply circuit 6 is the same oscillating voltage as the OFF voltage VOFF, which is a regular scanning signal of the scanning signal lines Y1 to Y4, and is relatively high for each horizontal scanning period TH. An oscillating voltage that alternates between a high voltage and a relatively low voltage level. Like the OFF voltage VOFF, the common electrode voltage VQQ has a high voltage level in the first H of the illustrated vertical scanning period TV, but has a low voltage level in the first H of the next vertical scanning period TV. Each time, the level of the high voltage and the low voltage are switched. Further, since the last row return line YR is connected to the common electrode power supply circuit 6 and receives the same common electrode voltage VQ, it has the same signal waveform.

The display signal on the display signal line X is also an oscillating voltage that alternately switches between a high voltage and a low voltage every horizontal scanning period TH. However, the phase of switching between the high voltage and the low voltage is inverted with respect to the OFF voltage VOFF and the counter electrode voltage VQ. The display signal changes in amplitude of the oscillating voltage according to an image to be displayed. Accordingly, in the first vertical scanning period TV shown in the drawing, the thin film transistors SW11 to SW1 in the first row connected to the scanning signal line Y1.
When the switch SW14 is turned on, the picture element capacitors CP11 to CP14 are discharged by the potential difference -VS between the display signal of the low voltage level on each of the display signal lines X1 to X4 and the counter electrode voltage VQ of the high voltage level, and the scanning signal line at the second H When the thin film transistors SW21 to SW24 in the second row connected to Y2 are turned on, the picture element capacitors CP21 to CP24 are connected to the respective display signal lines X1 to X1.
It is charged by the potential difference + VS between the X4 high voltage level display signal and the high voltage level common electrode voltage VQ. Until the next vertical scanning period TV, these pixel capacitors C
Since the display voltage ± VS is stored in P, it is possible to control the light transmittance of the liquid crystal layer of each picture element to perform display according to the display signal. Further, in the first H and the second H of the next vertical scanning period TV, a display voltage ± VS whose polarity is inverted to these picture element capacitors CP is applied. As described above, the AC inversion drive for supplying the pixel capacitance CP with the display signal being sequentially inverted in polarity is performed to prevent the liquid crystal from being deteriorated due to polarization and to generate flicker at the time of display. This is to suppress the situation.

The liquid crystal display device shown in FIG. 6 shows a conventional example in which the last line return line YR in the liquid crystal display device shown in FIG. 3 is connected not to the counter electrode power supply circuit 6 but to the OFF voltage power supply circuit 5. In this liquid crystal display device, since the OFF voltage VOFF supplied by the OFF voltage power supply circuit 5 and the common electrode voltage VQ supplied by the common electrode power supply circuit 6 are the same signal as described above, they perform exactly the same operation. In accordance with the layout of the liquid crystal panel 1, whichever is more convenient will be selected.

[0015]

FIG. 5 exemplifies the voltage waveform of the pixel electrode EPA in the pixel capacitance CP21 and the pixel capacitance CP41. The voltage of the pixel capacitance CP21 is such that the scanning signal line Y2 is in the O state during the second H in each vertical scanning period TV.
Since the voltage becomes the N voltage VON, the voltage level greatly changes each time, and during this time, the voltage level changes slightly according to the common electrode voltage VQ every horizontal scanning period TH. Further, in the pixel capacitance CP41, the scanning signal line Y4 becomes the ON voltage VON at the fourth H in each vertical scanning period TV, so that the voltage level greatly changes each time, and during these, the scanning signal line Y4 changes every horizontal scanning period TH. The voltage level changes slightly according to the counter electrode voltage VQ.

However, in the case of the pixel capacitance CP21, the second electrode ESB of the auxiliary capacitance CS21 is connected to the adjacent scanning signal line Y3.
3H, the second electrode ESB
Rises to the ON voltage VON, and the voltage of the pixel electrode EPA of the pixel capacitor CP21 is also raised by ΔVD1. That is, as shown in FIG. 7, the pixel capacitance CP21 and the auxiliary capacitance CS21
Since it is considered that the N voltage VON and the OFF voltage VOFF are connected in series, the second electrode ESB is turned off.
When the voltage VOFF is attained, the counter electrode EPB also has the same counter electrode voltage VQ as the OFF voltage VOFF. Therefore, the display voltage ± VS having the same absolute value is applied to the pixel capacitor CP21 and the auxiliary capacitor CS21. Each is applied. However, when the second electrode ESB of the auxiliary capacitor CS21 has reached the ON voltage VON, the ON voltage VON and the common electrode voltage VQ (OF
F voltage VOFF), the voltage VON-VOFF is the pixel capacitance CP
Since the voltage is applied to the series circuit of the capacitor 21 and the auxiliary capacitor CS21, in addition to the display voltage ± VS, the pixel capacitor CP21 is inversely proportional to the capacitance ratio between the pixel capacitor CP and the auxiliary capacitor CS as shown in Expression 1. Then, the divided voltage ΔVD1 is weighted, thereby pushing up the voltage of the pixel electrode EPA.

[0017]

(Equation 1)

Each picture element has a thin film transistor SW
Although a floating capacitance exists between the gate and the drain of the pixel, the capacitance is relatively small as compared with the pixel capacitance CP and the auxiliary capacitance CS, and is ignored here. In addition, when the OFF voltage VOFF is a high voltage and when the OFF voltage is a low voltage, the voltage ΔV shown in Expression 1 is used.
Although the value of D1 is different, this difference is small, and hence, in the following description, the same voltage ΔVD1 will be used in any case.

Here, consider the effective value VD1rms of the drive voltage applied to the pixel capacitance CP41. As shown in FIG. 5, the voltage of the pixel electrode EPA changes slightly every horizontal scanning period TH according to the OFF voltage VOFF and the oscillation voltage of the common electrode voltage VQ. Has a waveform that is alternately switched between the display voltages + VS and -VS every vertical scanning period TV without being affected by the oscillation voltage. Therefore, the effective voltage VD1rm
s is obtained as VS by the square mean of the display voltage ± VS over two vertical scanning periods TV, which is one cycle of the AC inversion drive, as shown in Expression 2.

[0020]

(Equation 2)

On the other hand, the drive voltage applied to the picture element capacitance CP21 is the display voltage ± VS for a period other than the period TON during which the scanning signal line Y2 becomes the ON voltage VON in each vertical scanning period TV. However, the period TON has a value obtained by adding the above-mentioned voltage ΔVD1 to the display voltage ± VS. Therefore, the effective voltage VD2rms is, as shown in Equation 3,
It is obtained by a root mean square of a display voltage ± VS over two vertical scanning periods TV and a drive voltage obtained by adding the voltage ΔVD1 to the display voltage ± VS, and is several mV higher than VS which is the effective voltage VD1rms of the pixel capacitor CP41.
Voltage value. Pixel capacitance CP21 and pixel capacitance CP
The absolute value of the driving voltage applied to 41 is represented by two vertical scanning periods TV
The result integrated over is the same value. However, even if the integration result of the absolute value is the same, the effective voltage is different if the voltage change state is different. If such a difference exists in the effective voltage, the pixel capacitance CP21 and the pixel capacitance CP21 are actually changed. Capacity C
A similar difference occurs in the power supplied to P41. Such a situation is common to the other pixel capacitances CP in the second row and the pixel capacitances CP in the first and third rows.

[0022]

(Equation 3)

For this reason, the second electrode ESB of the storage capacitor CS
Is connected to the adjacent scanning signal line Y, in the conventional active matrix type liquid crystal display device, only the effective voltage applied to the picture element capacitance CP in the last row becomes lower than the others by several mV, thereby causing the light transmission of the liquid crystal. There has been a problem that the ratios are different and the display quality is degraded due to uneven gradation. Note that this problem is not limited to the liquid crystal display device, but is common to other display devices that perform display by a driving voltage applied to the pixel capacitance.

Conventionally, in order to avoid the above-mentioned problem, there is a case where the last row is masked to reduce the number of display rows by one. However, in this method, for example, V
When the effective screen is 480 lines in the GA standard, the number of display lines is reduced to 479 lines, which causes a new problem that the entire screen cannot be completely displayed.

An invention has also been made in the past (Japanese Patent Application No. 5-275776) in which a circuit as shown in FIGS. 8 to 10 is provided to separately supply a signal to be supplied to the last line return line YR.

FIG. 8 shows that the scanning signal of the scanning signal line Y4 is transmitted by the timing circuit 11 for one horizontal scanning period TH, for example.
The switching circuit 12 is controlled by a signal delayed by only the last line, and the switching circuit 12 always outputs O to the last line return line YR.
The FF voltage VOFF is output, and the ON voltage VON is output only during one horizontal scanning period TH in the vertical retrace period TVR after scanning the last row. Also, FIG.
The number of rows to be scanned by the scanning signal line drive circuit 2 is increased by one row, and the increased scanning signal is output to the last row retrace line YR. Each of these generates a virtual scanning signal for performing scanning at the fifth H in the vertical blanking period TVR in the above-described example, and supplies this to the last row blanking line YR to thereby drive the pixel capacitors CP41 to CP44. Is set to the same value as the other rows shown in Expression 3.

FIG. 10 shows a configuration in which an oscillating voltage having a slightly larger amplitude than the common electrode voltage VQ is generated and supplied to the last line return line YR. That is, the amplitude of the common electrode voltage VQ is changed to the voltage ΔVB every other horizontal scanning period TH.
Generates an oscillating voltage that is as wide as possible to produce the final line return line YR
Is supplied to the pixel capacitor C via the auxiliary capacitor CS.
The divided voltage ΔVD2 shown in Equation 4 is weighted to P.

[0028]

(Equation 4)

Then, the picture element capacitance CP in the last row in this case is
Is a display voltage ± VS for a half period of one vertical scanning period TV, and a voltage ± ΔVD2 is added to the display voltage ± VS for the other half period, so that the effective voltage VD3rms Becomes the value shown in Expression 5, and becomes a voltage higher than the voltage VS of the original effective voltage VD1rms.

[0030]

(Equation 5)

Therefore, if the voltage .DELTA.VB is determined so that the effective voltage VD3rms coincides with the effective voltage VD1rms shown in Equation 2, the problem that the effective voltages of the pixel capacitors CP in only the last row are different can be solved. it can.

As shown in FIG. 10, the oscillating voltage such as the common electrode voltage VQ is supplied with a pulse signal having a cycle of the horizontal scanning period TH generated by the timing circuit 13 via the buffer circuit 14 through an operational amplifier (operational amplifier). ) Can be generated by amplifying by the first amplifying circuit 15 configured by the negative feedback circuit. The oscillating voltage to be supplied to the last line return line YR can also be generated by amplifying the oscillation voltage by the second amplifying circuit 16 composed of a negative feedback circuit of an operational amplifier. At this time, for example, the gain is changed by adjusting the feedback resistor R1 in the first amplifier circuit 15, and the reference voltage is changed by adjusting the voltage dividing resistors R2 and R3 of the first amplifier circuit 15 and the second amplifier circuit 16. By doing so, it is possible to generate an oscillating voltage in which the high voltage level of the common electrode voltage VQ is increased by the voltage ΔVB as described above.

However, in the inventions of FIGS. 8 to 10, it is necessary to provide a new circuit for generating a drive signal dedicated to the last-row retrace line YR. There is a problem that it increases.

The present invention solves the above-mentioned conventional problem. By connecting the last row retrace line to a scanning signal line other than the last row, an active matrix system which can effectively use the last row is used. It is an object to provide a display device.

[0035]

According to the present invention, there is provided an active matrix type display device which corresponds to a plurality of picture element electrodes arranged in a matrix on a picture element electrode substrate and each row of the matrix picture element electrodes. A plurality of scanning signal lines arranged one by one, a plurality of display signal lines arranged one by one corresponding to each column of the matrix-shaped picture element electrodes,
For each of the pixel electrodes, the pixel electrode is connected between a display signal line corresponding to the column of the pixel electrode and the pixel electrode, and is connected to the scanning signal line corresponding to the row of the pixel electrode. A switching element for controlling conduction or interruption between a pixel electrode and a display signal line, and for each of the pixel electrodes, a first electrode is connected to the pixel electrode, and the pixel electrode is connected to the matrix. The first, except in the row at one end of the shape
A second electrode opposed to the electrode is provided with an auxiliary capacitance element connected to a scanning signal line corresponding to a row adjacent to one side of the matrix with respect to the row of the picture element electrode. An active matrix display device in which a counter electrode is provided, and the picture element electrode substrate and the counter electrode substrate face each other with an electro-optical material interposed therebetween,
The first electrode is connected to each of the picture element electrodes in one row of the matrix, and the second electrode of each auxiliary capacitance element is connected to one of the scanning signal lines other than the scanning signal line corresponding to the one row. It is connected to a scanning signal line, thereby achieving the above object.

Preferably, in the active matrix type display device according to the present invention, the second electrode of each auxiliary capacitance element in which the first electrode is connected to each of the picture element electrodes in one end row of the matrix is a matrix. Connected to a scanning signal line corresponding to the other end of the row. Also, preferably,
The electro-optical material in the active matrix type display device of the present invention is a liquid crystal.

[0037]

In the present invention, when the second electrodes of the auxiliary capacitance elements in the picture elements of each row are sequentially connected to the scanning signal lines corresponding to the rows adjacent to one side of the matrix from the other side of the matrix, In the case of a row at one end, there is no row adjacent to one side, so that the second electrode cannot be connected to the scanning signal line. Therefore, according to the present invention, the second electrode of the auxiliary capacitance element in each picture element of one end row of the matrix is connected to any one of the scan signal lines other than the scan signal line corresponding to the one end row. ing.
Then, each of the pixel electrodes in the row at one end is made to conduct the switching element only once in each vertical scanning period during any horizontal scanning period excluding the period in which the own row is scanned. Is applied via the auxiliary capacitance element.

Therefore, according to the active matrix type display device of the present invention, a scanning signal can be applied to the second electrode of the auxiliary capacitance element even at one end row where there is no adjacent row on one side. Therefore, the effective value of the drive voltage of the picture element electrode can be made the same as the picture element capacitance of the other rows.

When the display device performs line-sequential scanning,
The row at one end of the matrix is the row scanned last or the row scanned first.

According to a second aspect of the present invention, the second electrode of the auxiliary capacitance element in each picture element in one row of the matrix is connected to a scanning signal line corresponding to the other row of the matrix. Is shown. In this case, if line-sequential scanning is performed, immediately after or immediately before the scanning of each row, a voltage for turning on the switching elements is applied to the pixel capacitors of all the rows.

The invention of claim 3 shows a case where a liquid crystal which is most frequently used as an active matrix type display device and needs to perform AC inversion driving is used as an electro-optical material.

[0042]

Embodiments of the present invention will be described below.

FIGS. 1 and 2 show an embodiment of the present invention. FIG. 1 is a block circuit diagram showing the configuration of a liquid crystal display device, and FIG. 2 is a time chart showing the operation of the liquid crystal display device. Components having the same functions as those of the conventional example shown in FIGS. 3 to 7 are denoted by the same reference numerals, and description thereof is omitted.

In this embodiment, a liquid crystal display device using a liquid crystal will be described. However, the present invention can be similarly applied to a case where another electro-optical material is used. Note that, here, a liquid crystal display device of 16 picture elements with 4 rows × 4 columns is shown for simplicity.

As shown in FIG. 1, the liquid crystal display device of this embodiment has a liquid crystal panel 1, an ON voltage power supply circuit 4, an OFF voltage power supply circuit 5, and a counter electrode power supply circuit provided outside the liquid crystal panel 1. 6. The ON voltage power supply circuit 4, the OFF voltage power supply circuit 5, and the counter electrode power supply circuit 6 have the same configuration as that used in the conventional liquid crystal display device shown in FIG.

In the liquid crystal panel 1, a picture element electrode substrate and a counter electrode substrate are arranged to face each other with a gap therebetween, and a liquid crystal is filled between them. On the opposing surface of the picture element electrode substrate, a scanning signal line driving circuit 2 and a display signal line driving circuit 3 having the same configuration as that of the conventional example shown in FIG. 3 as well as scanning signal lines Y1 to Y4 and display signal lines X1 to X4.
Are formed. Also, the configuration of the picture elements is shown in FIGS.
The pixel electrode EPA in the thin film transistor SW, the auxiliary capacitance CS, and the pixel capacitance CP is formed on the opposing surface of the pixel electrode substrate. The counter electrode EPB of the picture element capacitor CP is formed on the counter surface of the counter electrode substrate and is connected to the counter electrode power circuit 6.

The second electrodes ESB of the auxiliary capacitors CS in the picture elements of the first to third rows are respectively connected to the scanning signal lines Y2 to Y4 corresponding to the second to fourth rows adjacent thereto.
Is also the same as the conventional example shown in FIG. However, the second electrode ESB of the storage capacitor CS in each picture element in the fourth row is connected to the scanning signal line Y1 corresponding to the first row via the last row return line YR. The last line return line YR and the scanning signal line Y1 are provided at the farthest positions at both ends of the matrix. Therefore, they may be connected by wiring outside the liquid crystal panel 1 as shown. Further, a new conductive film can be laid on the pixel electrode substrate of the liquid crystal panel 1 for connection. In any case, one liquid crystal panel 1
Since only book connection is performed, the area occupied by the substrate surface due to the trouble of wiring and the laying of the conductive film is insignificant and does not pose a problem.

The operation of the liquid crystal display device having the above configuration will be described with reference to FIG. Here, the case of the VGA standard shown in FIG. 5 is shown, and for simplicity, only the 4H horizontal scanning period TH from the first H to the 4H is set as an effective screen, and the remaining fifth and subsequent Hs are set as a vertical blanking period TVR. I have.

The scanning signals of the scanning signal lines Y1 to Y4, the common electrode voltage VQ supplied by the common electrode power supply circuit 6, and the display signal of the display signal line X are the same as those shown in FIG. However, since the last row return line YR is connected to the scanning signal line Y1 as described above, similarly, only the ON period during the period TON in the first H of each vertical scanning period TV.
The voltage becomes high as the voltage VON.

In FIG. 2, as in FIG.
21 illustrates a voltage waveform of the pixel electrode EPA of the pixel capacitor CP41. Here, the pixel capacitance CP21 is exactly the same as that of FIG.
The voltage is pushed up by ΔVD1. However, since the last row retrace line YR and the scanning signal line Y1 become the ON voltage VON in the first H of each vertical scanning period TV, the picture element capacitance CP41 applies a high voltage to the second electrode ESB of the auxiliary capacitance CS41. Is applied, and the voltage is equal to the voltage ΔV as in the pixel capacitor CP21.
Only D1 can be raised. Therefore, as long as the display voltage VS by the display signal is the same, the effective value of the drive voltage applied to the pixel capacitance CP21 and the pixel capacitance CP41 becomes the same value, and the liquid crystal of the first to third rows and the fourth row is changed. There is no difference in display.

As a result, according to the liquid crystal display device of the present embodiment, the picture elements in the fourth row can be masked or the last row return line can be separately formed only by connecting the last row return line YR and the scanning signal line Y1. A high-quality image can be easily obtained without providing a power supply circuit dedicated to the line YR. In addition,
The last line return line YR can be connected to any of the other scanning signal lines Y2 and Y3 as long as it is not the scanning signal line Y4, and the same effect can be obtained.

[0052]

As described above, according to the active matrix type display device of the present invention, the second electrode of the auxiliary capacitance element is also provided on one end row without a row adjacent to one side of the matrix. Just connect to the scanning signal line of
The effective value of the drive voltage of the pixel capacitor is made the same as the pixel capacitors of the other rows without generating an unnecessary virtual scan signal or providing a dedicated power supply circuit only for the row at one end. This can prevent display quality from deteriorating.

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a block circuit diagram illustrating a configuration of a liquid crystal display device.

FIG. 2, showing an example of the present invention, is a time chart illustrating an operation of the liquid crystal display device.

FIG. 3 shows a conventional example and is a block circuit diagram illustrating a configuration of a liquid crystal display device.

FIG. 4 is an equivalent circuit diagram showing details of picture elements.

FIG. 5 shows a conventional example and is a time chart showing an operation of a liquid crystal display device.

FIG. 6 shows a second conventional example and is a block circuit diagram showing a configuration of a liquid crystal display device.

FIG. 7 is an equivalent circuit diagram for explaining a voltage rise due to the voltage division of the pixel capacitance CP.

FIG. 8 shows a third conventional example, and is a block circuit diagram of a circuit for generating a virtual scanning signal.

FIG. 9 is a block circuit diagram showing a fourth conventional example and showing a case where a virtual scanning signal is generated by a scanning signal line driving circuit.

FIG. 10 shows a fifth conventional example, and is a block circuit diagram of a circuit that generates a signal by changing the amplitude of a common electrode voltage.

[Explanation of symbols]

 Y scanning signal line X display signal line SW thin film transistor CP picture element capacity EPA picture element electrode EPB counter electrode CS auxiliary capacity ESA first electrode ESB second electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 550 G02F 1/1368 G09G 3/36

Claims (3)

(57) [Claims] 1. A plurality of picture element electrodes arranged in a matrix on a picture element electrode substrate, and a plurality of scanning signal lines arranged one by one corresponding to each row of the matrix picture element electrodes. A plurality of display signal lines arranged one by one corresponding to each column of the pixel electrodes in the matrix form; and a display signal line corresponding to the column of the pixel electrodes for each of the pixel electrodes. A switching element that is connected between the pixel electrodes and controls conduction or cutoff between the pixel electrodes and the display signal lines according to a voltage of a scanning signal line corresponding to a row of the pixel electrodes; For each of the pixel electrodes, a first electrode is connected to the pixel electrode, and a second electrode facing the first electrode, except when the pixel electrode is in a row at one end of the matrix. The two electrodes are adjacent to the row of the pixel electrodes on one side of the matrix. And an auxiliary capacitance element connected to a scanning signal line corresponding to a row, and a counter electrode is provided on a counter electrode substrate, and the pixel electrode substrate and the counter electrode substrate are interposed by an electro-optical material. In the active-matrix type display device opposed to each other, a second electrode of each auxiliary capacitance element in which a first electrode is connected to each of the pixel electrodes in a row at one end of a matrix is provided at a row at the one end. An active matrix display device connected to one of the scanning signal lines other than the corresponding scanning signal line. 2. The scanning in which a second electrode of each of the auxiliary capacitance elements, in which a first electrode is connected to each of the picture element electrodes in a row at one end of a matrix, corresponds to a row at the other end of the matrix. 2. The active matrix type display device according to claim 1, wherein the display device is connected to a signal line. 3. The method according to claim 1, wherein the electro-optical material is a liquid crystal.
Or an active matrix display device according to claim 2.