JP2004220021A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device, in which refreshing is not wanted and a power consumption is small by solving problems wherein pixel is too small for an SRAM circuit and an aperture ratio is degraded, if the pixel area is small, when using an active matrix display device using the SRAM, where the number of transistors constitute the SRAM circuit is large. <P>SOLUTION: This display device composites a pixel with a switching element and an EEPROM element. For the EEPROM element a ferroelectric element is used. When displaying a static image writing in for each frame can be eliminated by a holding procedure. The ferroelectric memory can be built-in, without degrading the aperture ratio, because occupied area of the ferroelectric memory is small. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a display device using a thin film transistor (TFT) formed on a transparent substrate such as glass or plastic, and a driving method thereof. Further, the present invention relates to an electronic device using the display device.

  2. Description of the Related Art In recent years, with the progress of communication technology, mobile phones have become widespread. In the future, transmission of moving images and more information transmission are expected. On the other hand, as for personal computers, mobile-friendly products have been produced due to their light weight. A large number of information terminals called PDAs, which began with electronic organizers, have been produced and are becoming popular. Also, due to the development of display devices, most of these portable information devices are equipped with flat panel displays.

  Furthermore, recent technologies are moving toward using an active matrix type display device as the display device to be used. In the active matrix type display device, a TFT is arranged for each pixel, and a screen is controlled by the TFT. Such an active matrix display device has advantages such as higher performance, higher image quality, and compatibility with moving images as compared with a passive matrix display device. Therefore, it is considered that the mainstream of the liquid crystal display device shifts from the passive matrix type to the active matrix type.

  In addition, among active matrix display devices, in recent years, a display device has been commercialized using a thin film transistor using a polycrystalline semiconductor using a polycrystalline semiconductor crystallized at a low temperature. The above low temperature means that the crystallization temperature is 600 ° C. or lower, which is lower than the conventional crystallization temperature of 1000 ° C. or higher. In a TFT using a polycrystalline semiconductor formed at a low temperature, a driving circuit can be integrally formed around a pixel portion as well as a pixel, so that a display device can be downsized and a high definition can be achieved. is there. For this reason, further spread is expected in the future.

  The operation of the pixel portion of an active matrix liquid crystal display device is described below. FIG. 2 shows an example of the configuration of an active matrix liquid crystal display device. One pixel 220 includes a source signal line 203, a gate signal line 205, a capacitor line 219, a pixel TFT 207, a storage capacitor 211, and a liquid crystal 215. However, the capacitance line is not necessarily required as long as it can be used as another wiring. The gate electrode of the pixel TFT 207 is connected to the gate signal line 205, one of the drain region or the source region of the pixel TFT 207 is connected to the source signal line 203, and the other is connected to the storage capacitor 211 and the liquid crystal 215. I have.

  The gate signal lines 205 and 206 are sequentially selected in a line cycle. When the pixel TFTs 207 and 209 are of an N-channel type (Nch), the pixel TFTs 207 and 209 are turned on when the gate signal line 205 is at Hi, and the pixel TFTs 207 and 209 are turned on. When the pixel TFTs 207 and 209 are turned on, the potentials of the source signal lines 203 and 204 are written to the holding capacitors 211 and 213 and the liquid crystals 215 and 217. In the next line period, the adjacent gate signal line 206 becomes active, the pixel TFTs 208 and 210 become Hi, and the potentials of the source signal lines 203 and 204 are written in the storage capacitors 212 and 214 and the liquid crystals 216 and 218 in the same manner. Go. The liquid crystals 215 to 218 are oriented according to the written potential, and change the light transmittance. Thus, the active matrix type liquid crystal display device performs display using the liquid crystal as an optical shutter.

  Further, as shown in FIG. 14, there has been developed a device which has a static RAM (SRAM) provided inside a pixel to perform display (for example, see Patent Document 1).

JP-A-8-286170

In FIG. 14, one pixel 1407 includes an SRAM 1403, switches 1405 and 1406, and a liquid crystal 1404. The source signal line driver circuit 1401 outputs a video signal to the source signal lines 1408 and 1409. When the gate signal line 1410 is selected by the gate signal line driver circuit 1402, a video signal is written to the SRAM 1403 via the source signal lines 1408 and 1409. Based on the data stored in the SRAM 1403, one of the switches 1405 and 1406 operates and a potential of Va or Vb is applied to the liquid crystal 1404. This state is maintained until the next writing to the SRAM is performed.
The display is performed in this manner.

  The conventional active matrix display device has the following problems. As described above, the pixel portion of the conventional active matrix type display device has a dynamic RAM (DRAM) type configuration including a storage capacitor and a switch circuit, and thus requires a periodic refresh operation. FIG. 3 shows the operation waveforms. When the source signal line waveform changes at t1 and t4, the pixel signal waveform is drawn toward the source signal line waveform from that point.

  In the conventional example shown in FIG. 3, since the rewriting is performed at t2 to t3 and t5 to t6, there is no problem in display. However, if the refresh operation is not performed or the refresh period is long, the electric charge accumulated in the storage capacitor becomes Discharge occurs due to the leak current of the switch TFT, and the voltage required for driving the liquid crystal cannot be maintained. Therefore, even in the case where the image data is originally displayed without change, such as a still image, periodic writing is required. As a result, there is a problem that power consumption increases due to the writing operation.

  In an active matrix display device using an SRAM as shown in FIG. 14, when the number of transistors forming the SRAM circuit is large and the pixel area is small, the SRAM circuit cannot fit in the pixel or the aperture ratio is reduced. There was a problem.

  In order to solve the above-described problem, the following measures are used in the display device of the present invention. That is, a non-volatile memory element, for example, a non-volatile memory using a ferroelectric material is provided in the pixel, and the stored content is stored without refreshing. The use of a ferroelectric material eliminates the need for an SRAM, so that the required element area can be reduced.

  The present invention is a display device in which a source signal line, a gate signal line, and pixels are arranged in a matrix, and each pixel has a switching element, a nonvolatile memory element, and a pixel electrode. The switching element has an input terminal electrically connected to the source signal line, an output terminal electrically connected to the nonvolatile memory element and the pixel electrode, and a control terminal electrically connected to the gate signal line.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, wherein one pixel includes a plurality of sub-pixels, and A switching element having an input terminal electrically connected to the source signal line, an output terminal electrically connected to the nonvolatile memory element and the pixel electrode, and a control terminal connected to the switching element. It is electrically connected to the gate signal line.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix. One pixel includes a plurality of sub-pixels. A switching element, a nonvolatile memory element, and a pixel electrode; an input terminal of the switching element is electrically connected to the source signal line; an output terminal of the switching element is electrically connected to the nonvolatile memory element and the pixel electrode; The switching elements in one pixel are electrically connected to the gate signal lines, and are connected to different source signal lines.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, and n source signal lines are arranged for one pixel column. And one pixel is composed of n sub-pixels, each sub-pixel having a switching element, a non-volatile memory element, and a pixel electrode, the switching element having an input terminal electrically connected to a source signal line, and an output A terminal is electrically connected to the nonvolatile memory element and the pixel electrode, a control terminal is electrically connected to the gate signal line, and a switching element in one pixel is one of n different source signal lines. It is connected to the.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix. One pixel includes a plurality of sub-pixels. A switching element, a nonvolatile memory element, and a pixel electrode; an input terminal of the switching element is electrically connected to the source signal line; an output terminal of the switching element is electrically connected to the nonvolatile memory element and the pixel electrode; The switching elements in one pixel are electrically connected to gate signal lines, and are connected to different gate signal lines.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, and n gate signal lines are arranged for one pixel column. And one pixel includes n sub-pixels, each of which has a switching element, a non-volatile memory element, and a pixel electrode. The switching element has an input terminal electrically connected to a source signal line, and an output terminal. A terminal is electrically connected to the nonvolatile memory element and the pixel electrode, a control terminal is electrically connected to the gate signal line, and each of the switching elements in one pixel is one of n different gate signal lines. It is connected to the.

  A display device according to the present invention is a display device in which a source signal line, a gate signal line, and pixels are arranged in a matrix, and each pixel has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode. . The switching element has an input terminal electrically connected to the source signal line, an output terminal electrically connected to the nonvolatile memory element and the driving element, a control terminal electrically connected to the gate signal line, and the driving element is It is electrically connected to the pixel electrode.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, wherein one pixel includes a plurality of sub-pixels, and A switching element having an input terminal electrically connected to the source signal line, an output terminal electrically connected to the nonvolatile memory element and the driving element, and controlling the switching element; The terminal is electrically connected to the gate signal line, and the driving element is electrically connected to the pixel electrode.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix. One pixel includes a plurality of sub-pixels. A switching element, a non-volatile memory element, a driving element, and a pixel electrode; an input terminal of the switching element is electrically connected to the source signal line; an output terminal of the switching element is electrically connected to the non-volatile memory element and the driving element; A control terminal is electrically connected to a gate signal line, a driving element is electrically connected to a pixel electrode, and switching elements in one pixel are respectively connected to different source signal lines.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, and n source signal lines are arranged for one pixel column. And one pixel is composed of n sub-pixels, each of which has a switching element, a non-volatile memory element, a driving element, and a pixel electrode, and an input terminal of the switching element is electrically connected to a source signal line. The output terminal is electrically connected to the nonvolatile memory element and the driving element, the control terminal is electrically connected to the gate signal line, the driving element is electrically connected to the pixel electrode, and the switching in one pixel is performed. The elements are connected to any one of n different source signal lines.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix. One pixel includes a plurality of sub-pixels. A switching element, a non-volatile memory element, a driving element, and a pixel electrode; an input terminal of the switching element is electrically connected to the source signal line; an output terminal of the switching element is electrically connected to the non-volatile memory element and the driving element; A control terminal is electrically connected to a gate signal line, a driving element is electrically connected to a pixel electrode, and switching elements in one pixel are respectively connected to different gate signal lines.

  A display device according to the present invention is a display device in which a plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix, and n gate signal lines are arranged for one pixel column. Each pixel includes n sub-pixels, each sub-pixel having a switching element, a non-volatile memory element, a driving element, and a pixel electrode. The switching element has an input terminal electrically connected to a source signal line. The output terminal is electrically connected to the nonvolatile memory element and the driving element, the control terminal is electrically connected to the gate signal line, the driving element is electrically connected to the pixel electrode, and the switching element in one pixel Are connected to any one of n different gate signal lines.

  In the present invention described above, it is preferable to use a ferroelectric memory as the nonvolatile memory element. Further, a thin film transistor can be used as the switching element.

  In the above invention, a source signal line driver circuit and / or a gate signal line driver circuit can be formed over the same substrate as a pixel. The source signal line driver circuit and / or the gate signal line driver circuit can be formed using unipolar transistors.

  In a conventional display device, there is a problem that refresh is required for a pixel at a constant cycle, writing is required even when a still image is output, and power consumption is large. Further, in a display device using an SRAM, since a large number of TFTs are required in a pixel, there is a problem that the aperture ratio is reduced and a necessary element is not included in the pixel.

  According to the present invention, since a nonvolatile memory element is built in a pixel, a refresh operation at the time of displaying a still image is unnecessary, and the image can be held with a small number of elements, so that display can be performed without significantly lowering the aperture ratio. I was able to.

  FIG. 1 shows the configuration of the present invention. FIG. 1 is an example showing a 3-bit gradation. Here, the description will be made with three bits, but the present invention is not limited to three bits. One pixel 152 includes three switching elements and three nonvolatile memory elements. On / off of the switching element is controlled by the gate signal line. One end of the nonvolatile memory element is connected to each switching element, and the other end is connected to the common electrode 151. The switching element has an input terminal, an output terminal, and a control terminal, the input terminal is electrically connected to a source signal line, and the output terminal is electrically connected to a liquid crystal element through a nonvolatile memory element and a pixel electrode (not shown). And the control terminal is electrically connected to the gate signal line.

  Digital video signals are output from the source signal line driving circuit 101 to the source signal lines 103 to 108. When the gate signal line drive circuit 102 selects the gate signal lines 109 to 111, the switching elements 115 to 117 and 121 to 123 are turned on, and the digital video signals of the source signal lines 103 to 108 are transmitted to the nonvolatile memory elements 127 to 129 and 133. Write to 135. When the gate signal line driving circuit 102 releases the selection of the gate signal lines 109 to 111, the switching elements 115 to 117 and 121 to 123 are turned off. However, since the states are stored in the nonvolatile memory elements 127 to 129 and 133 to 135, the liquid crystals 139 to 141 and 145 to 147 can perform display in a state where writing has been performed.

  Next, when the gate signal line drive circuit 102 selects the gate signal lines 112 to 114, the switching elements 118 to 120 and 124 to 126 are turned on, and the digital video signals of the source signal lines 103 to 108 are transmitted to the nonvolatile memory elements 130 to 132, 136-138. When the gate signal line driving circuit 102 releases the selection of the gate signal lines 112 to 114, the switching elements 118 to 120 and 124 to 126 are turned off. However, since the states are stored in the nonvolatile memory elements 130 to 132 and 136 to 138, the liquid crystals 142 to 144 and 148 to 150 can perform display in a state where writing has been performed.

  In the present invention, since the holding is performed digitally, the gray scale is displayed using the area gray scale. That is, in the case of performing 3-bit display, the gray scale can be expressed by setting the area of the pixel electrode to 4: 2: 1 and storing a necessary state according to the required gray scale.

When a ferroelectric material such as PZT (lead zirconate titanate, Pb [Zr _x , Ti _1-x ] O ₃ ) is used for the nonvolatile memory element, the state is maintained even when the power is turned off. When a still image is displayed, the power of the display device can be turned off, and power consumption can be reduced. Thus, the present invention can eliminate the need for the refresh operation, which is a conventional problem, and achieve low power consumption. Further, the ferroelectric material is not limited to PZT and may be another material.

  Further, according to the present invention, unlike a display device using an SRAM, a large number of transistors are not required in a pixel, and the present invention can be used without a small pixel or a significant decrease in aperture ratio. Although the above description has been made using liquid crystal as an example, an electrophoretic element or the like other than liquid crystal may be used.

  The source signal line driver circuit, the gate signal line driver circuit, or other circuits used in the present invention may be formed integrally with the pixel on the same substrate, or may be formed on another substrate and formed on a COG (Chip On Glass) or The mounting may be performed using a technology such as TAB (Tape Automated Bonding).

  FIG. 4 shows an embodiment of the present invention. In this embodiment, the switching element is configured by a TFT. FIG. 4 is an example showing 3-bit gradation. Here, the description will be made with three bits, but the present invention is not limited to three bits. One pixel 452 includes three TFTs and three nonvolatile memory elements. On / off of the TFT is controlled by a gate signal line. The non-volatile memory element has one end connected to a liquid crystal element via each TFT and a pixel electrode (not shown), and the other end connected to a common electrode 451.

  Digital video signals are output from the source signal line driver circuit 401 to the source signal lines 403 to 408. When the gate signal line driving circuit 402 selects the gate signal lines 409 to 411, the TFTs 415 to 417 and 421 to 423 are turned on, and the digital video signals of the source signal lines 403 to 408 are transferred to the nonvolatile memory elements 427 to 429 and 433 to 435. Write to. When the gate signal line driving circuit 402 releases the selection of the gate signal lines 409 to 411, the TFTs 415 to 417 and 421 to 423 are turned off. However, since the state is stored in the nonvolatile memory elements 427 to 429 and 433 to 435, the liquid crystal 439 to 441 and 445 to 447 can perform display in a state where writing has been performed.

  Next, when the gate signal line drive circuit 402 selects the gate signal lines 412 to 414, the TFTs 418 to 420 and 424 to 426 are turned on, and the digital video signals of the source signal lines 403 to 408 are transferred to the nonvolatile memory elements 430 to 432, Write to 436 to 438. When the gate signal line driving circuit 402 releases the selection of the gate signal lines 412 to 414, the TFTs 418 to 420 and 424 to 426 are turned off. However, since the state is stored in the nonvolatile memory elements 430 to 432 and 436 to 438, the liquid crystal 442 to 444 and 448 to 450 can perform display in a state in which writing has been performed.

  In the present invention, since the holding is performed digitally, the gray scale is displayed using the area gray scale. That is, in the case of performing 3-bit display, the gray scale can be expressed by setting the area of the pixel electrode to 4: 2: 1 and storing a necessary state according to the required gray scale.

  When a ferroelectric material such as PZT is used for the nonvolatile memory element, the state is maintained even when the power is turned off. Therefore, when a still image is displayed, the power of the display device can be turned off, and power consumption is reduced. It is possible. Thus, the present invention can eliminate the need for the refresh operation, which is a conventional problem, and achieve low power consumption.

  Further, according to the present invention, unlike a display device using an SRAM, a large number of transistors are not required in a pixel, and the present invention can be used without a small pixel or a significant decrease in aperture ratio.

  FIG. 5 shows an embodiment of the present invention. This embodiment is different from the first embodiment in that one source signal line is provided for one pixel column. FIG. 4 is an example showing 3-bit gradation. Here, the description will be made with three bits, but the present invention is not limited to three bits. One pixel 548 includes three TFTs and three nonvolatile memory elements. On / off of the TFT is controlled by a gate signal line. The non-volatile memory element has one end connected to a liquid crystal element via each TFT and a pixel electrode (not shown), and the other end connected to a common electrode 547. The operation will be described below.

  A digital video signal is output from the source signal line driving circuit 501 to the source signal lines 503 and 504. When the gate signal line driving circuit 502 selects the gate signal line 505, the TFTs 511 and 517 are turned on, and the digital video signals of the source signal lines 503 and 504 are written to the nonvolatile memory elements 523 and 529. When the gate signal line driving circuit 502 releases the selection of the gate signal line 505, the TFTs 511 and 517 are turned off. However, since the state is stored in the nonvolatile memory elements 523 and 529, the liquid crystal 535 and 541 can perform display in a state where writing has been performed.

  Next, when the gate signal line driver circuit 502 selects the gate signal line 506, the TFTs 512 and 518 are turned on, and the digital video signals of the source signal lines 503 and 504 are written to the nonvolatile memory elements 524 and 530. When the gate signal line driving circuit 502 releases the selection of the gate signal line 506, the TFTs 512 and 518 are turned off. However, since the state is stored in the nonvolatile memory elements 524 and 530, the liquid crystal 536 and 542 can perform display in a state where writing has been performed.

  Next, when the gate signal line driver circuit 502 selects the gate signal line 507, the TFTs 513 and 519 are turned on, and the digital video signals of the source signal lines 503 and 504 are written to the nonvolatile memory elements 525 and 531. When the gate signal line driving circuit 502 releases the selection of the gate signal line 507, the TFTs 513 and 519 are turned off. However, since the state is stored in the nonvolatile memory elements 525 and 531, the liquid crystal 537 and 543 can perform display in a state where writing has been performed. Thus, the data writing of one pixel 548 is completed. These writings are performed during one horizontal line period.

  Subsequently, the same writing is performed for the pixels in the next row. The gate signal lines 508, 509, and 510 are sequentially selected, and accordingly, the TFTs 514, 520, 515, 521, 516, and 522 are sequentially turned on, and the data on the source signal lines 503 and 504 are stored in the nonvolatile memory elements 538, 544, 539, 545, 540, and 546 are written. Display is performed in this manner. In this embodiment, since the number of source signal lines can be reduced, it is possible to contribute to an improvement in aperture ratio.

  FIG. 6 shows an embodiment of a source signal line driving circuit corresponding to the pixel configuration shown in the first embodiment. The source signal line driver circuit in FIG. 6 includes a shift register 601, a first latch circuit 614, and a second latch circuit 615. The operation will be described below.

  When the output pulse of the shift register 601 is input to the latch circuits 602 to 604, the digital video signal of the video signal line 614 is stored in the latch circuits 602 to 604. Next, when the output pulse of the shift register 601 is input to the latch circuits 608 to 610, the digital video signal of the video signal line 614 is stored in the latch circuits 608 to 610. Similarly, the output pulse of the shift register is sequentially scanned, and the video signal for one line is stored in the first latch circuit 614. Before the video of the next line starts, a latch pulse is input to the latch circuits 605 to 607 and 611 to 613 through the latch signal line 615, and the data of the first latch circuit 614 is stored in the second latch circuit 615. Then, data is output to the source signal line. Thus, the source signal line driving circuit operates.

  FIG. 7 shows an embodiment of a source signal line drive circuit having a configuration different from that of the first embodiment. This source signal line driving circuit corresponds to the pixel configuration of the second embodiment. With the output pulse of the shift register 701, the data of the video signal line 714 is sequentially stored in the latch circuits 702 to 704 and 708 to 710. After the data of one line is stored, the data is latched by the latch pulse of the latch signal line 715. Data is transferred to the circuits 705 to 707 and 711 to 713.

  Up to this point, the operation is the same as that of the third embodiment. Thereafter, the outputs of the latch circuits 705 to 707 are switched by the switch 716, and each of the outputs is output to the source line for one third of one line period. By doing so, the number of source signal lines can be reduced. That is, it is possible to use the signal of the source signal line in a time division manner. Here, it is divided into three, but the division is not limited to three. Similarly, the outputs of the latch circuits 711 to 713 can be switched by the switch 717 and output to the source signal line.

  FIG. 8 illustrates an example in which a shift register is formed using unipolar TFTs. When the signal line driver circuit or another circuit is a single-polarity circuit, cost of the display device can be reduced. FIG. 8 shows an example of Nch, but the unipolarity may be either Nch only or P-channel type (Pch). By using a unipolar process, the number of masks can be reduced.

  In FIG. 8, a start pulse is input to a scan direction changeover switch 802, and is input to a shift register 801 via a switching TFT 811. The shift register is a set-reset type shift register using a bootstrap. Hereinafter, the operation of the shift register 801 will be described.

  The start pulse is input to the gate of the TFT 803 and the gate of the TFT 806. When the TFT 806 turns on, the gate of the TFT 804 goes low and the TFT 804 turns off. Further, since the gate of the TFT 810 is also low, the TFT 810 is also turned off. Since the gate of the TFT 803 rises to the power supply potential, the gate of the TFT 809 first rises to the power supply −Vgs. Since the initial potential of the output 1 is low, the TFT 809 increases the source potential while charging the output 1 and the capacitor 808. When the gate of the TFT 809 rises to the power supply -Vgs, the TFT 809 is still on. , Output 1 continues to rise. Since the gate of the TFT 809 has no discharge path, it rises in accordance with the source and continues to rise even if the power is exceeded.

  When the drain and the source of the TFT 809 have the same potential, the current stops flowing to the output, and the potential of the TFT 809 stops rising there. Thus, the output 1 can output a high potential equal to the power supply potential. At this time, the potential of CLb is set to high. When CLb falls to low, the charge of the capacitor 808 passes through CLb via the TFT 809, and the output 1 falls to low. The output 1 pulse is transmitted to the next stage shift register. The above is the operation of the circuit of this embodiment. This embodiment can be used in combination with another embodiment of the present invention.

  FIG. 9 is a plan view of the pixel shown in the first embodiment. It includes source signal lines 901 to 903, gate signal lines 904 to 906, TFTs 907 to 909, nonvolatile memory elements 910 to 912, common electrodes 913 to 915, and pixel electrodes 916 to 918. This embodiment is an example of three bits, but is not limited to three bits. As shown in FIG. 9, the non-volatile memory elements 910 to 912 have a small occupied area, so that a memory circuit can be incorporated without reducing the aperture ratio.

Further, by setting the areas of the pixel electrodes 916, 917, and 918 to 1: 2: 4, a 3-bit area gray scale can be realized. Similarly, in the case of n bits, n sub-pixels are provided, and the area ratio of each sub pixel is set to 1 to 2 to the power of n-1.

  A manufacturing process of the display device of the present invention will be described. Here, a method for simultaneously manufacturing a switching TFT forming a pixel portion, a TFT forming a driving circuit or another logic circuit, and a capacitor using a ferroelectric material forming a nonvolatile latch circuit on the same substrate. Will be described in detail. 10 to 13 are cross-sectional views illustrating the manufacturing process.

  First, in FIG. 10A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a SUS substrate, or the like can be used as the substrate 1000. A substrate made of a flexible synthetic resin such as plastic generally has a lower heat-resistant temperature than the above substrate, but any substrate can be used as long as it can withstand the processing temperature in the manufacturing process. It is.

Base films 1001 and 1002 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed over a substrate 1000. For example, a silicon oxynitride film 1001 formed from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method is formed to have a thickness of 10 to 200 nm (preferably 50 to 100 nm), and is similarly formed from SiH ₄ and N ₂ O. A silicon oxynitride hydride film 1002 is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, the base film is shown as a two-layer structure, but may be formed as a single-layer film of the insulating film or a structure in which two or more layers are laminated. In the case where diffusion of impurities is not a problem, such as a quartz substrate, it is not always necessary to provide them.

  The island-shaped semiconductor layers 1003 to 1005 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed by a laser crystallization method or a known thermal crystallization method (FIG. 10B). The island-shaped semiconductor layers 1003 to 1005 are formed to have a thickness of 25 to 100 nm (preferably 30 to 60 nm). Note that the island-shaped semiconductor layers 1003 to 1005 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used. In the case of using these lasers, a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated to a semiconductor film is preferably used. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ). When a YAG laser is used, the second harmonic is used to set the pulse oscillation frequency to 1 to 10 kHz and the laser energy density to 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the overlapping rate (overlap rate) of the linear laser light at this time is set to 80 to 98%.

Next, a gate insulating film 1006 which covers the island-shaped semiconductor layers 1003 to 1005 is formed (FIG. 10C). The gate insulating film 1006 is formed using a plasma CVD method or a sputtering method with a thickness of 40 to 150 nm and containing silicon. In this embodiment, a silicon oxynitride film with a thickness of 120 nm is formed. Needless to say, the gate insulating film 1006 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by plasma CVD, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., the high frequency (13.56 MHz), the power density It can be formed by discharging at 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as an insulating film by subsequent thermal annealing at 400 to 500 ° C.

  Next, as illustrated in FIG. 11A, gate electrodes 1100 to 1102 are formed over the gate insulating film 1006. The gate electrodes 1100 to 1102 may be formed using tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy containing the above elements as a main component, polycrystalline silicon, or the like. First, a conductive layer is formed over the surface, and the conductive layer is etched using a resist mask (not illustrated), whereby gate electrodes 1100 to 1102 are formed.

  After that, an N-type impurity element is doped. Thus, N-type low-concentration impurity regions 1103 to 1108 are formed in the semiconductor active layer.

  Next, a resist mask (not shown) is formed so as to cover the gate electrode 1102, an n-type impurity element is added in a self-aligned manner with the gate electrode 1101 and the resist mask as a mask, and the gate electrode 1101 is used as a mask. A p-type impurity element is added in a self-aligned manner.

  Thus, the high-concentration n-type impurity regions 1111, 1112, 1113, and 1114 functioning as the source and drain regions of the n-channel TFT and the high-concentration p-type impurity regions 1109 and 1110 functioning as the source and drain regions of the p-channel TFT To form Phosphorus (P) or arsenic (As) is used for the impurity element imparting n-type, and boron (B) is used for the impurity element imparting p-type.

  After that, activation of the n-type and p-type impurity elements is performed. As the activating means, furnace annealing, laser annealing, lamp annealing, or a method combining these may be used. The thermal annealing is performed at 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.

  Then, as shown in FIG. 11C, a first interlayer insulating film 1115 of a silicon nitride film or a silicon oxynitride film is formed over the gate electrodes 1100 to 1112.

  As described above, the switching TFT forming the pixel portion and the TFT forming the driving circuit and other logic circuits are formed on the same substrate. Next, a capacitor is formed on the first interlayer insulating film 1112 using a ferroelectric material.

First, a lower electrode layer 1201 is formed (FIG. 12A). The formation method may be selected from CVD, sputtering, ion beam sputtering, laser ablation, and the like. As a material of the lower electrode layer 1201, Pt / IrO ₂ , Pt / Ta / SiO _2, or the like can be used. Since the electrical characteristics of the ferroelectric thin film strongly depend on the crystal orientation, it is particularly preferable to use Pt, whose orientation is easily controlled, on the surface of the lower electrode. After forming the metal film, unnecessary portions are processed by plasma etching or the like to form the lower electrode layer 1201.

Next, a ferroelectric layer 1202 is formed over the lower electrode layer 1201 (FIG. 12B). As the ferroelectric, a lead-containing perovskite such as PZT and PbTiO ₃ , a bismuth layered compound such as Bi ₄ Ti ₃ O ₁₂ , and an ilmenite compound such as LiNbO ₃ and LiTaO ₃ can be used. Of these, ferroelectrics using lead-containing perovskites, particularly PZT, are preferable because they exhibit ferroelectric properties over a wide composition range.

  The method for forming the ferroelectric layer 1202 may be selected from a CVD method, a sputtering method, an ion beam sputtering method, a laser ablation method, and the like. In particular, the CVD method is preferable because it has high controllability of film composition and crystallinity, and is excellent in large area and mass production. When formed by the CVD method, the conditions of the material are that it has a relatively low temperature, has a large vapor pressure, is stable for a long time, and that the deposition rate is determined by the supply amount of the raw material within the deposition temperature range. Although the nucleation reaction does not occur, PZT is also excellent in these respects.

  The process of forming the ferroelectric layer by the CVD method may follow a known procedure. For example, a ferroelectric layer of PZT can be formed at a pressure of 660 Pa and a substrate temperature of 500 to 650 degrees.

Next, an upper electrode layer 1203 is formed over the ferroelectric layer 1202 (FIG. 12C). A formation method can be selected from a CVD method, a sputtering method, an ion beam sputtering method, a laser ablation method, and the like, similarly to the lower electrode 1201. As the material for the upper electrode layer 1203, Ir / IrO ₂ or the like can be used in addition to the material used for the lower electrode layer 1201.

  Next, as shown in FIG. 13A, a second interlayer insulating film 1307 made of a silicon nitride film or a silicon oxynitride film is formed, and then a contact hole is formed. Wirings 1300 to 1306 are formed. Note that the form of electrical connection between the wirings 1300 to 1306 and the TFT is not limited to this embodiment.

  Finally, a protective layer 1308 is formed over the second interlayer insulating film 1307 as shown in FIG. As a material of the protective layer 1308, a photocurable or thermosetting organic resin material such as polyimide or acrylic resin can be used.

Through these procedures, a TFT using a pixel portion, a TFT forming a driving circuit and other logic circuits, and a capacitor using a ferroelectric material forming a nonvolatile latch circuit are simultaneously formed on the same substrate. can do.

  In this embodiment, the case where a structure having an LDD region that does not overlap with a gate electrode is formed as a switching TFT forming a pixel, and a single drain structure is formed as a TFT forming a driving circuit and a logic circuit is shown. However, the present embodiment is not limited to this structure. If necessary, a TFT structure suitable for a use such as a GOLD structure or another LDD structure may be manufactured according to a known method.

  FIG. 16 shows an embodiment in which the conventional display method and the display method of the present invention are combined. To output a still image, a digital video signal is output from the source signal line driver circuit 1601 to the source signal lines 1604 to 1606. At this time, it is assumed that the switches 1619 to 1621 have selected the nonvolatile memory. When the gate signal line driver circuit 1602 selects the gate signal lines 1625 to 1627, the switching elements 1610 to 1612 are turned on, and the video signals are written to the nonvolatile memories 1613 to 1615 and the liquid crystals 1622 to 1624.

  To display a moving image, an analog video signal is output from the source line driver circuit 1603 to the source signal lines 1604 to 1606. At this time, it is assumed that the switches 1619 to 1621 have selected the holding capacitors 1616 to 1618. When the gate signal line driver circuit 1602 selects the gate signal lines 1625 to 1627, the switching elements 1610 to 1612 are turned on, and the analog video signal is written to the holding capacitors 1616 to 1618 and the liquid crystal 1622 to 1624. Display can be performed in this manner.

  FIG. 18 is an embodiment of the circuit of FIG. The gate line 1801 is selected when an image is displayed. When the gate line 1801 is selected, the transistor 1803 is turned on. When the image is continuously displayed, the gate signal line 1802 is selected. When the gate signal line 1802 is selected, the transistor 1804 is turned on. FIG. 19 is a cross-sectional view of a pixel including the nonvolatile memory 1613 and the storage capacitor 1616.

  FIG. 17 shows an embodiment of the present invention. FIG. 17 shows an example of an EL display device having a 3-bit gradation. Here, the description will be made with three bits, but the present invention is not limited to three bits. In this embodiment, a switching element and a driving element are used, but in the following description, they are described as a switching TFT and a driving TFT. However, the switching elements and the driving elements are not limited to TFTs.

  One pixel 1752 is constituted by three switching TFTs 1715, 1716, 1717, three nonvolatile memory elements 1727, 1728, 1729, three driving TFTs 1753, 1754, 1755, and three EL elements 1739, 1740, 1741. On / off of the switching TFT is controlled by a gate signal line. One end of the nonvolatile memory element is connected to each switching TFT, and the other end is connected to the common electrode 151. One of a drain and a source of the switching TFT is electrically connected to a source signal line, another of the drain and the source is electrically connected to a gate of the nonvolatile memory element and the driving TFT, and a gate is a gate signal line. Is electrically connected to The source of the driving TFT is electrically connected to power supply lines 1765 and 1766, and the drain is electrically connected to an EL element via a pixel electrode (not shown).

  Digital video signals are output from the source signal line driver circuit 1701 to the source signal lines 1703 to 1708. When the gate signal line driver circuit 1702 selects the gate signal lines 1709 to 1711, the switching TFTs 1715 to 1717 and 1721 to 1723 are turned on, and the digital video signals of the source signal lines 1703 to 1708 are transferred to the nonvolatile memory elements 1727 to 1729 and 1733 to 1733. Write to 1735. When the gate signal line driving circuit 1702 releases the selection of the gate signal lines 1709 to 1711, the switching TFTs 1715 to 1717 and 1721 to 1723 are turned off. However, since the states are stored in the nonvolatile memory elements 1727 to 1729 and 1733 to 1735, the gates of the driving TFTs 1753 to 1755 and 1759 to 1761 are in a state where writing has been performed. The elements 1739 to 1741 and 1745 to 1747 can be driven to perform display.

  Next, when the gate signal line driving circuit 1702 selects the gate signal lines 1712 to 1714, the switching TFTs 1718 to 1720 and 1724 to 1726 are turned on, and the digital video signals of the source signal lines 1703 to 1708 are transferred to the nonvolatile memory elements 1730 to 1732. , 1736-1738. When the gate signal line driver circuit 1702 releases the selection of the gate signal lines 1712 to 1714, the switching TFTs 1718 to 1720 and 1724 to 1726 are turned off. However, since the states are stored in the nonvolatile memory elements 1730 to 1732 and 1736 to 1738, the driving TFTs 1756 to 1758 and 1762 to 1764 are in a state where writing has been performed. To 1744 and 1748 to 1750 can be driven to perform display.

  In this embodiment, three source signal lines are arranged for one pixel column. However, as shown in the second embodiment, one source signal line is arranged for one pixel column, and three gate signal lines are arranged. Good as a book.

In the present invention, since the holding is performed digitally, the gray scale is displayed using the area gray scale. That is, in the case of performing 3-bit display, the gray scale can be expressed by setting the area of the pixel electrode to 4: 2: 1 and storing a necessary state according to the required gray scale. As described above, the present invention is not limited to three bits.
In the above, the driving TFT may be operated in the saturation region and the EL element may be driven at a constant current, or the driving TFT may be operated in the linear region and the EL element may be driven at a constant voltage.

  When a ferroelectric material such as PZT is used for the nonvolatile memory element, the state is maintained even when the power is turned off. Therefore, when a still image is displayed, the power of the display device can be turned off, and power consumption can be reduced. It is possible to plan. Thus, the present invention can eliminate the need for the refresh operation, which is a conventional problem, and achieve low power consumption. Further, the ferroelectric material is not limited to PZT and may be another material.

  Further, according to the present invention, unlike a display device using an SRAM, a large number of transistors are not required in a pixel, and the present invention can be used without a small pixel or a significant decrease in aperture ratio.

  The source signal line driver circuit, the gate signal line driver circuit, or other circuits used in the present invention may be formed over the same substrate as the pixel, or may be formed over a different substrate and use a technique such as COG or TAB. You may implement using.

  The display device manufactured as described above can be used as a display portion of various electronic devices. Hereinafter, electronic devices in which a display device formed by using the present invention is incorporated as a display medium will be described.

  Examples of such electronic devices include a video camera, a digital camera, a head-mounted display (goggle-type display), a game machine, a car navigation, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, and the like). . One example is shown in FIG.

  FIG. 15A illustrates a digital camera, which includes a main body 3101, a display portion 3102, an image receiving portion 3103, operation keys 3104, an external connection port 3105, a shutter 3106, and the like. The display device of the present invention can be used for the display portion 3102 of a camera.

  FIG. 15B illustrates a laptop computer including a main body 3201, a housing 3202, a display portion 3203, a keyboard 3204, an external connection port 3205, a pointing mouse 3206, and the like. The display device of the present invention can be used for the display portion 3203.

  FIG. 15C illustrates a portable information terminal, which includes a main body 3301, a display portion 3302, a switch 3303, operation keys 3304, an infrared port 3305, and the like. The display device of the present invention can be used for the display portion 3302.

  FIG. 15D illustrates an image reproducing device (specifically, a DVD reproducing device) including a recording medium, which includes a main body 3401, a housing 3402, a recording medium (CD, LD, DVD, or the like) reading unit 3405, and an operation switch 3406. , A display unit (a) 3403, a display unit (b) 3404, and the like. The display unit A mainly displays image information, and the display unit B mainly displays character information. The display device of the present invention may be used for the display units (a) and (b) of an image reproducing apparatus having a recording medium. Can be. Note that the present invention can be applied to a CD playback device, a game machine, and the like as an image playback device provided with a recording medium.

  FIG. 15E illustrates a foldable portable display device, in which a display portion 3502 using the present invention can be attached to a main body 3501.

  FIG. 15F illustrates a wristwatch-type display device, which includes a belt 3601, a display portion 3602, operation switches 3603, an audio output portion 3604, and the like. The display device of the present invention can be used for the display portion 3602.

  FIG. 15G illustrates a mobile phone. A main body 3701 includes a housing 3702, a display portion 3703, a sound input portion 3704, an antenna 3705, operation keys 3706, an external connection port 3707, and the like. The display device of the present invention can be used for the display portion 3703.

  As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using a configuration including any combination of the first to ninth embodiments.

FIG. 2 is a diagram illustrating a configuration of a display device of the present invention. FIG. 13 illustrates a configuration of a conventional display device. FIG. 7 is a diagram showing operation waveforms of a pixel portion of a conventional display device. FIG. 2 is a diagram showing an embodiment of the display device of the present invention. FIG. 2 is a diagram showing an embodiment of the display device of the present invention. FIG. 3 is a block diagram of a source signal line driver circuit of the display device of the present invention. FIG. 3 is a block diagram of a source signal line driver circuit of the display device of the present invention. FIG. 4 is a diagram illustrating a signal line driver circuit using a unipolar TFT. FIG. 2 is a plan view of a pixel of the present invention. The figure which shows the structure cross section of this invention. The figure which shows the structure cross section of this invention. The figure which shows the structure cross section of this invention. The figure which shows the structure cross section of this invention. FIG. 13 illustrates a pixel of a display device using a conventional SRAM. FIG. 13 is a diagram of an electronic device using the display device of the present invention. The figure of the example which combined the present invention and the DRAM type pixel. Embodiment in which the present invention is applied to an EL display device The figure which shows the example which showed FIG. 16 in detail. The figure which shows the cross section of this invention.

Claims (18)

A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
The pixel has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A display device, wherein a control terminal is electrically connected to the gate signal line. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
The sub-pixel has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A display device, wherein a control terminal is electrically connected to the gate signal line. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A control terminal is electrically connected to the gate signal line;
A display device, wherein switching elements in one pixel are respectively connected to different source signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
N source signal lines are arranged for one pixel column,
One pixel is composed of n sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A control terminal is electrically connected to the gate signal line;
A display device, wherein a switching element in one pixel is connected to one of n different source signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A control terminal is electrically connected to the gate signal line;
A display device, wherein switching elements in one pixel are respectively connected to different gate signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
N gate signal lines are arranged for one pixel column,
One pixel is composed of n sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the pixel electrode,
A control terminal is electrically connected to the gate signal line;
A display device, wherein a switching element in one pixel is connected to any one of n different gate signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
The pixel has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The display device, wherein the driving element is electrically connected to the pixel electrode. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
The sub-pixel has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The display device, wherein the driving element is electrically connected to the pixel electrode. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The display device, wherein the driving element is electrically connected to the pixel electrode, and switching elements in one pixel are respectively connected to different source signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
N source signal lines are arranged for one pixel column,
One pixel is composed of n sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The driving element is electrically connected to the pixel electrode,
A display device, wherein a switching element in one pixel is connected to one of n different source signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
One pixel is composed of a plurality of sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The driving element is electrically connected to the pixel electrode,
A display device, wherein switching elements in one pixel are respectively connected to different gate signal lines. A plurality of source signal lines, a plurality of gate signal lines, and a plurality of pixels are arranged in a matrix,
N gate signal lines are arranged for one pixel column,
One pixel is composed of n sub-pixels,
Each of the sub-pixels has a switching element, a nonvolatile memory element, a driving element, and a pixel electrode,
The switching element has an input terminal electrically connected to the source signal line,
An output terminal is electrically connected to the nonvolatile memory element and the driving element,
A control terminal is electrically connected to the gate signal line;
The driving element is electrically connected to the pixel electrode,
A display device, wherein a switching element in one pixel is connected to one of n different gate signal lines.   14. The display device according to claim 1, wherein the nonvolatile memory element is a ferroelectric memory.   The display device according to any one of claims 1 to 13, wherein the switching element is a thin film transistor. In any one of claims 1 to 14,
A display device, wherein a source signal line driver circuit is formed over the same substrate as a pixel. In any one of claims 1 to 14,
A display device, wherein a gate signal line driver circuit is formed over the same substrate as a pixel. In Claim 15 or Claim 16,
A display device, wherein the source signal line driver circuit or the gate signal line driver circuit is formed using a transistor of a single polarity. An electronic apparatus using the display device according to any one of claims 1 to 17.

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