JP4943177B2 - Liquid crystal display device, electronic device - Google Patents

Description

  The present invention relates to a driving circuit for a semiconductor display device (hereinafter referred to as a display device) and a display device using the driving circuit, and more particularly to a driving circuit and driving for an active matrix display device having a thin film transistor formed on an insulator. The present invention relates to an active matrix display device using a circuit. In particular, the present invention relates to an active matrix liquid crystal display device using a digital video signal as a video source, and an active matrix liquid crystal display device using the drive circuit.

  In recent years, a display device in which a semiconductor thin film is formed over an insulator, particularly a glass substrate, in particular, an active matrix display device using a thin film transistor (hereinafter referred to as TFT) has become widespread. An active matrix display device using TFTs has hundreds of thousands to millions of TFTs arranged in a matrix, and displays an image by controlling the charge of each pixel.

  Furthermore, as a recent technology, in addition to the pixel TFT constituting the pixel, a technology related to a polysilicon TFT in which a drive circuit is simultaneously formed using a TFT in the peripheral portion of the pixel portion has been developed. Along with this, the liquid crystal display device has become an indispensable device for display units of mobile devices, which have greatly contributed to power consumption, and whose application fields have been rapidly expanding in recent years.

  FIG. 13 shows a schematic diagram of a normal digital liquid crystal display device. A pixel portion 1308 is arranged in the center. A source signal line driver circuit 1301 for controlling the source signal line is disposed on the upper side of the pixel portion. The source signal line driver circuit 1301 includes a first latch circuit 1304, a second latch circuit 1305, a D / A conversion circuit 1306, an analog switch 1307, and the like. On the left and right sides of the pixel portion, gate signal line driving circuits 1302 for controlling the gate signal lines are arranged. In FIG. 13, the gate signal line driver circuit 1302 is disposed on both the left and right sides of the pixel portion, but may be disposed on one side. However, the two-sided arrangement is desirable from the viewpoint of driving efficiency and driving reliability.

  The source signal line driver circuit 1301 has a configuration as shown in FIG. The driving circuit shown as an example in FIG. 14 is a source signal line driving circuit corresponding to a display of horizontal resolution of 1024 pixels and 3-bit digital gradation, and includes a shift register circuit (SR) 1401 and a first latch circuit (LAT1). 1402, a second latch circuit (LAT2) 1403, a D / A conversion circuit (D / A) 1404, and the like. Although not shown in FIG. 14, a buffer circuit, a level shift circuit, or the like may be arranged as necessary.

  The operation will be briefly described with reference to FIGS. 13 and 14. First, a clock signal (S-CLK, S-CLKb) and a start pulse (S-SP) are input to a shift register circuit 1303 (indicated as SR in FIG. 14), and sampling pulses are sequentially output. Subsequently, the sampling pulse is input to the first latch circuit 1304 (denoted as LAT1 in FIG. 14), and similarly holds the digital video signal (Digital Data) input to the first latch circuit 1304. This period is called a dot data sampling period. Here, D1 is the most significant bit (MSB: Most Significant Bit), and D3 is the least significant bit (LSB: Least Significant Bit). When the holding of the digital video signal for one horizontal period is completed in the first latch circuit 1304, the digital video signal held in the first latch circuit 1304 during the blanking period is a latch signal (Latch Pulse). Are simultaneously transferred to the second latch circuit 1305 (indicated as LAT2 in FIG. 14). A period during which the digital video signal is transferred from the first latch circuit to the second latch circuit is referred to as a line data latch period.

  Thereafter, the shift register circuit 1303 operates again, and the holding of the digital video signal for the next horizontal period is started. At the same time, the digital video signal held in the second latch circuit 1305 is converted into an analog video signal by a D / A conversion circuit 1306 (denoted as DAC in FIG. 14). The analog digital video signal is written to the pixel via the source signal line. By repeating this operation, an image is displayed.

  In a general active matrix liquid crystal display device, the screen display is updated about 60 times per second in order to smoothly display a moving image. That is, it is necessary to supply a digital video signal for each frame and write to the pixel each time. Even if the video is a still image, the same signal must be continuously supplied for each frame, so that the drive circuit needs to continuously process the same digital video signal.

  There is a method in which a digital video signal of a still image is once written in an external storage circuit, and thereafter, the digital video signal is supplied from the external storage circuit to the liquid crystal display device for each frame. The circuit and the drive circuit need to continue to operate.

  Particularly in mobile devices, low power consumption is highly desired. In addition, in this mobile device, although it is mostly used in the still image mode, the drive circuit continues to operate even when displaying a still image as described above. This is a drag on power consumption.

  In view of the above-described problems, an object of the present invention is to reduce power consumption of a driving circuit when a still image is displayed by using a novel circuit.

  In order to solve the above-described problems, the present invention uses the following means.

  A plurality of storage circuits are arranged in the pixel, and a digital video signal is stored for each pixel. In the case of a still image, once writing is performed, the information written to the pixels thereafter is the same. Therefore, by reading the signal stored in the storage circuit without inputting the signal every frame, Can be displayed continuously. In other words, when displaying a still image, it is possible to stop the source signal line drive circuit after performing a signal processing operation for at least one frame, thereby greatly reducing power consumption. Is possible.

  The configuration of the liquid crystal display device of the present invention will be described below.

  The liquid crystal display device of the present invention is a liquid crystal display device having a plurality of pixels, wherein each of the plurality of pixels has a plurality of memory circuits.

  In the liquid crystal display device according to the present invention, in the liquid crystal display device having a plurality of pixels, each of the plurality of pixels has a digital video signal of n bits (n is a natural number, 2 ≦ n) for m frames (m is a natural number, 1 ≦ m) It is characterized by having n × m memory circuits for storing.

  The liquid crystal display device of the present invention is a liquid crystal display device having a plurality of pixels, each of the plurality of pixels including a source signal line, n (n is a natural number, 2 ≦ n) write gate signal lines, and n N × m number of gate signal lines for reading, n number of writing transistors, n number of reading transistors, and n-bit digital video signals for m frames (m is a natural number, 1 ≦ m). Storage circuit selection unit, n write storage circuit selection units, n read storage circuit selection units, and liquid crystal elements, and each of the n write transistor gate electrodes has the n number of gate electrodes. Are electrically connected to any one of the different write gate signal lines, one of the source region and the drain region is electrically connected to the source signal line, and the other is connected to the n write signals. Each of the n write memory circuit selectors is electrically connected to any one of the different signal input units, and each of the n write memory circuit selectors has m signal output units, The signal output units are electrically connected to the signal input units of the m different memory circuits, and the n read memory circuit selection units have m signal input units, respectively. The signal input portions of the n read transistors are electrically connected to the signal output portions of the different m memory circuits, and the gate electrodes of the n read transistors are respectively connected to the n read gate signal lines. Each of the source regions and the drain regions is electrically connected to any one of the different ones, and one of the source region and the drain region is electrically connected to any one of the different ones of the read storage circuit selection units. The other is electrically connected to one electrode of the liquid crystal element.

  The liquid crystal display device of the present invention is a liquid crystal display device having a plurality of pixels, and each of the plurality of pixels includes n (n is a natural number, 2 ≦ n) source signal lines, write gate signal lines, n N × m number of gate signal lines for reading, n number of writing transistors, n number of reading transistors, and n-bit digital video signals for m frames (m is a natural number, 1 ≦ m). Memory circuit selector, n write memory circuit selectors, n read memory circuit selectors, and a liquid crystal element, and the gate electrodes of the n write transistors are respectively for the write transistors. Electrically connected to the gate signal line, each of the source region and the drain region is electrically connected to a different one of the n source signal lines, and the other is the n number of the other. Each of the write memory circuit selection units is electrically connected to any one of the different signal input units, and each of the n write storage circuit selection units has m signal output units, The signal output units are electrically connected to signal input units of m different memory circuits, respectively, and the n read memory circuit selection units each include m signal input units, The signal input units are electrically connected to the signal output units of the m different memory circuits, and the gate electrodes of the n read transistors are respectively connected to the n read gate signal lines. Are electrically connected to any one of the different ones, and the source region and the drain region are electrically connected to any one of the n different signal output units of the read memory circuit selection unit. The other is electrically connected to one electrode of the liquid crystal element.

  The liquid crystal display device according to the present invention is the liquid crystal display device according to any one of claims 3 and 4, wherein the write memory circuit selection unit selects any one of the m memory circuits, The digital video signal is written to the memory circuit by conducting with one of the source region and the drain region of the transistor for reading, and the memory circuit selection unit for reading is connected to the memory circuit in which the digital video signal is stored. One of them is selected, and the stored digital video is read out by conducting with one of the source region and the drain region of the reading transistor.

  According to a third aspect of the present invention, there is provided a liquid crystal display device according to claim 3, wherein the shift register sequentially outputs sampling pulses according to the clock signal and the start pulse, and n bits (n is a natural number, 2 ≦ n) according to the sampling pulses. A first latch circuit for holding a digital video signal; a second latch circuit for transferring the n-bit digital video signal held in the first latch circuit; and a transfer to the second latch circuit. And a bit signal selection switch for sequentially selecting the n-bit digital video signal one bit at a time and outputting it to the source signal line.

  According to a fourth aspect of the present invention, there is provided a liquid crystal display device according to claim 4, wherein the shift register sequentially outputs sampling pulses according to the clock signal and the start pulse, and n bits (n is a natural number, 2 ≦ n) according to the sampling pulse. Among the digital video signals, a first latch circuit that holds the 1-bit digital video signal, and the 1-bit digital video signal that is held in the first latch circuit are transferred to the source signal line. And a second latch circuit for outputting the one-bit digital video signal.

  According to a fourth aspect of the present invention, there is provided a liquid crystal display device according to claim 4, wherein the shift register sequentially outputs sampling pulses according to the clock signal and the start pulse, and n bits (n is a natural number, 2 ≦ n) according to the sampling pulse. The digital video signal includes a first latch circuit that holds the 1-bit digital video signal and outputs the 1-bit digital video signal to the source signal line.

  The liquid crystal display device of the present invention is characterized in that, in any one of claims 1 to 8, the memory circuit is a static memory (SRAM).

  The liquid crystal display device of the present invention is characterized in that, in any one of claims 1 to 8, the memory circuit is a ferroelectric memory (FeRAM).

  The liquid crystal display device of the present invention is characterized in that, in any one of claims 1 to 8, the memory circuit is a dynamic memory (DRAM).

  The liquid crystal display device of the present invention according to any one of claims 1 to 11 is characterized in that the memory circuit is formed on a glass substrate.

  The liquid crystal display device of the present invention according to any one of claims 1 to 11 is characterized in that the memory circuit is formed on a plastic substrate.

  The liquid crystal display device of the present invention according to any one of claims 1 to 11 is characterized in that the memory circuit is formed on a stainless steel substrate.

  The liquid crystal display device of the present invention is characterized in that, in any one of claims 1 to 11, the memory circuit is formed on a single crystal wafer.

  According to another aspect of the present invention, there is provided a driving method for a liquid crystal display device that displays an image using a digital video signal of n bits (n is a natural number, 2 ≦ n). A line driver circuit, a gate signal line driver circuit, and a plurality of pixels; in the source signal line driver circuit, a sampling pulse is output from a shift register and input to a latch circuit; in the latch circuit, The digital video signal is held in accordance with the sampling pulse, the held digital video signal is written to a source signal line, and a gate signal line selection pulse is output in the gate signal line driving circuit. A gate signal line is selected, and in each of the plurality of pixels, a source is selected in a row in which the gate signal line is selected. And writing to the memory circuit n bits of the digital video signal input from the scan signal line, it is characterized by performing the reading of the n bit digital video signals stored in the storage circuit.

  The driving method of the liquid crystal display device of the present invention is a driving method of a liquid crystal display device that displays an image using an n-bit (n is a natural number, 2 ≦ n) digital video signal. A line driver circuit and a plurality of pixels. In the source signal line driver circuit, a sampling pulse is output from a shift register and input to a latch circuit. In the latch circuit, the digital signal is output in accordance with the sampling pulse. The video signal is held, the held digital video signal is written to the source signal line, and the gate signal line driving circuit outputs a gate signal line selection pulse to set the gate signal line to 1 The n-bit digital video signal is sequentially written from the first row in the plurality of pixels. It is characterized in.

  The driving method of the liquid crystal display device of the present invention is a driving method of a liquid crystal display device that displays an image using an n-bit (n is a natural number, 2 ≦ n) digital video signal. A line driver circuit and a plurality of pixels. In the source signal line driver circuit, a sampling pulse is output from a shift register and input to a latch circuit. In the latch circuit, the digital signal is output in accordance with the sampling pulse. The video signal is held, the held digital video signal is written to the source signal line, and the gate signal line driving circuit specifies a gate signal line selection pulse and an arbitrary row of the gate signal line In the plurality of pixels, in any row where the gate signal line is selected, It is characterized by writing the bits of the digital video signal.

  The method for driving a liquid crystal display device according to the present invention is the liquid crystal display device according to any one of claims 16 to 18, wherein the n-bit digital video signal stored in the storage circuit is repeatedly read during a still image display period. Then, the source signal line driving circuit is stopped by displaying a still image.

  By storing digital video signals using a plurality of storage circuits arranged inside each pixel, the digital video signals stored in the storage circuit are repeatedly used in each frame period when displaying a still image. When continuously displaying still images, the source signal line driver circuit can be stopped. Therefore, it can greatly contribute to the reduction in power consumption of the entire liquid crystal display device.

  FIG. 2 illustrates a configuration of a source signal line driver circuit and some pixels in a display device using a pixel having a plurality of memory circuits. This circuit corresponds to a 3-bit digital gradation signal, and includes a shift register circuit 201, a first latch circuit 202, a second latch circuit 203, a bit signal selection switch 204, and a pixel 205. Reference numeral 210 denotes a gate signal line to which a gate signal line selection signal is directly supplied from the gate signal line driving circuit or from the outside, and will be described later together with the description of the pixel.

  FIG. 1 shows the configuration of the pixel 205 in FIG. 2 in detail. This pixel corresponds to 3-bit digital gradation and has a liquid crystal element (LC), a storage capacitor (Cs), memory circuits (A1 to A3 and B1 to B3), and the like. 101 is a source signal line, 102 to 104 are write gate signal lines, 105 to 107 are read gate signal lines, 108 to 110 are write TFTs, 111 to 113 are read TFTs, and 114 is a first write line. The memory circuit selection unit, 115 is a first read memory circuit selection unit, 116 is a second write memory circuit selection unit, 117 is a second read memory circuit selection unit, and 118 is a third write memory circuit. The selection unit 119 is a third read memory circuit selection unit.

  The memory circuits (A1 to A3 and B1 to B3) included in the pixels shown in FIG. 1 can each store a 1-bit digital video signal. Here, one set of A1 to A3 and one set of B1 to B3 are stored. Used to store 3-bit digital video signals. That is, the pixel shown in FIG. 1 can store two frames of 3-bit digital video signals.

  FIG. 3 is a timing chart in the display device of the present invention shown in FIG. The display device is intended for 3-bit digital gradation, VGA. The driving method will be described with reference to FIGS. In addition, as for each number, the thing of FIGS. 1-3 is used as it is (drawing number is omitted).

  Reference is made to FIGS. 2 and 3A and 3B. In FIG. 3A, each frame period is described as α, β, γ, and δ. First, circuit operation in the frame period α will be described.

  As in the case of a conventional digital driving circuit, a clock signal (S-CLK, S-CLKb) and a start pulse (S-SP) are input to the shift register circuit 201, and sampling pulses are sequentially output. Subsequently, the sampling pulse is input to the first latch circuit 202 (LAT1), and each digital video signal (Digital Data) input to the first latch circuit 202 is held. The dot data sampling period for one horizontal period is each period indicated by 1 to 480 in FIG. The digital video signal is 3 bits, D1 is MSB (Most Significant Bit) and D3 is LSB (Least Significant Bit). When the holding of the digital video signal for one horizontal period is completed in the first latch circuit 202, the digital video signal held in the first latch circuit 202 during the blanking period is a latch signal (Latch Pulse). Are transferred all at once to the second latch circuit 203 (LAT2).

  Subsequently, in accordance with the sampling pulse output from the shift register circuit 201 again, a digital video signal holding operation for the next horizontal period is performed.

  On the other hand, the digital video signal transferred to the second latch circuit 203 is written in a memory circuit arranged in the pixel. As shown in FIG. 3B, the dot data sampling period of the next column is divided into three, I, II, and III, and the digital video signal held in the second latch circuit is output to the source signal line. At this time, the bit signal selection switch 204 is selectively connected so that the signal of each bit is sequentially output to the source signal line.

  In the period I, a pulse is input to the writing gate signal line 102, the writing TFT 108 is turned on, the memory circuit selection unit 114 selects the memory circuit A1, and a digital video signal is written to the memory circuit A1. Subsequently, in period II, a pulse is input to the writing gate signal line 103, the writing TFT 109 is turned on, the memory circuit selection unit 116 selects the memory circuit A2, and a digital video signal is written to the memory circuit A2. . Lastly, in period III, a pulse is input to the write gate signal line 104, the write TFT 110 is turned on, the memory circuit selection unit 118 selects the memory circuit A3, and a digital video signal is written to the memory circuit A3. .

  This completes the processing of the digital video signal for one horizontal period. The period shown in FIG. 3B is a period indicated by * in FIG. By performing the above operation up to the final stage, a digital video signal for one frame is written in the memory circuit A.

By the way, in the display device of the present invention, 3-bit digital gradation is expressed by a time gradation method. The time gray scale method is different from the normal method in which the brightness is controlled by the voltage applied to the pixel, and only two types of voltage are applied to the pixel to turn it on and off (white and black on display). And a gradation is obtained by utilizing the difference in display time. When performing n-bit gradation expression in the time gradation method, the display period is divided into n periods, and the ratio of the lengths of the periods is 2 ^n-1 : 2 ^n-2 :. : 2 ⁰ and a power of two as by either the pixel to the oN state at any time, produce differences in the length of the display period, performs a representation of gradation have. Here, the pixel being in the ON state means a state where a voltage is applied, and the OFF state means a state where no voltage is applied. Hereinafter, such a state is expressed as ON and OFF.

  In addition, the display can be performed even if the display period is displayed by gradation other than the power of 2.

  Based on the above, the operation in the frame period β will be described. When writing to the memory circuit in the final stage is completed, the first frame is displayed. FIG. 3C illustrates a 3-bit time gray scale method. Now, the digital video signal is stored in the storage circuits A1 to A3 for each bit. Ts1 is a display period based on the first bit data, Ts2 is a display period based on the second bit data, Ts3 is a display period based on the third bit data, and the length of each display period is Ts1: Ts2: Ts3 = 4 : 2: 1.

  Here, since it is 3 bits, 8 levels from 0 to 7 can be obtained. When display is not performed in any period of Ts1 to Ts3, brightness 0 is obtained, and brightness is obtained 7 when display is performed using all periods. For example, when it is desired to display the luminance 5, the pixel may be turned on at Ts1 and Ts3 and displayed.

  This will be specifically described with reference to the drawings. In Ts1, a pulse is input to the readout gate signal line 105, the readout TFT 111 is turned on, the storage circuit selection unit 115 selects the storage circuit A1, and the pixel is determined according to the digital video signal stored in the storage circuit A1. Is driven. Subsequently, at Ts2, a pulse is input to the readout gate signal line 106, the readout TFT 112 is turned on, the storage circuit selection unit 117 selects the storage circuit A2, and the digital video signal stored in the storage circuit A2 Accordingly, the pixel is driven. Finally, at Ts3, a pulse is input to the readout gate signal line 107, the readout TFT 113 is turned on, the storage circuit selection unit 119 selects the storage circuit A3, and the digital video signal stored in the storage circuit A3 A voltage is applied to the pixel.

  Here, in the case of a liquid crystal display device, there are a normally white mode and a normally black mode. In both cases, white and black are reversed when the pixels are turned on and off, and thus the above description and luminance may be reversed.

  As described above, display for one frame period is performed. On the other hand, on the drive circuit side, processing of the digital video signal in the next frame period is simultaneously performed. The procedure up to the transfer of the digital video signal to the second latch circuit is the same as described above. In the subsequent writing period to the memory circuit, a memory circuit different from the memory circuit storing the digital video signal in the previous frame period is used.

  In the period I, a pulse is input to the writing gate signal line 102, the writing TFT 108 is turned on, the memory circuit selection unit 114 selects the memory circuit B1, and a digital video signal is written to the memory circuit B1. Subsequently, in period II, a pulse is input to the writing gate signal line 103, the writing TFT 109 is turned on, the memory circuit selection unit 116 selects the memory circuit B2, and a digital video signal is written to the memory circuit B2. . Lastly, in period III, a pulse is input to the write gate signal line 104, the write TFT 110 is turned on, the memory circuit selection unit 118 selects the memory circuit B3, and a digital video signal is written to the memory circuit B3. .

  Subsequently, in the frame period γ, the second frame is displayed according to the digital video signal stored in the storage circuits B1 to B3. At the same time, processing of the digital video signal in the next frame period is started. This digital video signal is stored again in the storage circuits A1 to A3 where the display of the first frame has been completed.

  Thereafter, the display of the digital video signal stored in the storage circuits A1 to A3 is performed in the frame period δ, and at the same time, the processing of the digital video signal in the next frame period is started. This digital video signal is stored again in the storage circuits B1 to B3 that have finished displaying the second frame.

  By repeating the above operation, video display is continuously performed. Here, when displaying a still image, after the digital video signal is once stored in the storage circuits A1 to A3 in the first operation, the digital video signal stored in the storage circuits A1 to A3 in each frame period is stored. Read it out repeatedly. Therefore, the driving of the source signal line driving circuit can be stopped during the period when the still image is displayed.

  Further, writing of a digital video signal to the memory circuit or reading of the digital video signal from the memory circuit can be performed in units of one gate signal line. That is, a display method such as selecting a gate signal line only in a row requiring screen rewriting, operating the source signal line driver circuit only for a short period, and rewriting only a part of the screen can be employed.

  In the present embodiment, the storage circuits A1 to A3 and B1 to B3 are provided in one pixel, and a function of storing a 3-bit digital video signal for two frames is provided. It is not limited to this number. That is, in order to store n-bit digital video signals for m frames, it is only necessary to have n × m storage circuits in one pixel.

  By the above method, the digital video signal is stored using the memory circuit mounted in the pixel, so that the digital video signal stored in the memory circuit is repeated in each frame period when the still image is displayed. It is possible to continuously display still images without driving the source signal line driving circuit. Therefore, it can greatly contribute to the reduction in power consumption of the liquid crystal display device.

  The source signal line driver circuit does not necessarily have to be integrally formed on the insulator because of the problem of the layout of the latch circuit and the like that increases with the number of bits, and part or all of the source signal line driver circuit is configured externally. Also good.

  Furthermore, in the source signal line driver circuit shown in this embodiment, a latch circuit corresponding to the number of bits is arranged, but it is also possible to arrange and operate only one bit. In this case, digital video signals from upper bits to lower bits may be input to the latch circuit in series.

  Examples of the present invention will be described below.

  In this example, a memory circuit selection portion in the circuit shown in the embodiment is specifically configured using a transistor and the operation thereof will be described.

  4A is the same as the pixel shown in FIG. 1, and is an example in which the memory circuit selection units 114 to 119 are actually configured by circuits. In the figure, the same reference numerals as those in FIG. 1 are assigned to the same parts as those in FIG. Each of the memory circuits A1 to A3 and B1 to B3 is provided with write selection TFTs 401, 403, 405, 407, 409, and 411 and read selection TFTs 402, 404, 406, 408, 410, and 412 to select the memory circuit. Control is performed by signal lines 413 and 414.

  FIG. 4B illustrates an example of a memory circuit. A portion indicated by a dotted line frame 450 is a memory circuit (portions indicated by A1 to A3 and B1 to B3 in FIG. 4A), 451 is a write selection TFT, and 452 is a read selection TFT. Although the memory circuit shown here uses a static memory (Static RAM: SRAM) using two inverters connected in a loop, the memory circuit is not limited to this configuration. Here, in the case where an SRAM is used for the memory circuit, the pixel may have a structure that does not particularly have a storage capacitor (Cs).

  The circuit shown in FIG. 4A in this embodiment can be driven according to the timing chart shown in FIG. 3 in the embodiment. The circuit operation will be described with reference to FIGS. 3 and 4A in addition to the actual driving method of the memory circuit selection unit. Note that the numbers in FIG. 3 and FIG. 4A are used as they are (the figure numbers are omitted).

  Reference is made to FIGS. In FIG. 3A, each frame period is described as α, β, γ, and δ. First, circuit operation in the frame period α will be described.

  Since the driving method from the shift register circuit to the second latch circuit is the same as that shown in the embodiment, it follows.

  First, a pulse is input to the memory circuit selection signal line 413, and the write selection TFTs 401, 405, and 409 are turned on, and writing into the memory circuits A1 to A3 becomes possible. In the period I, a pulse is input to the writing gate signal line 102, the TFT 108 is turned on, and a digital video signal is written to the memory circuit A1. Subsequently, in a period II, a pulse is input to the writing gate signal line 103, the TFT 109 is turned on, and a digital video signal is written to the memory circuit A2. Lastly, in period III, a pulse is input to the write gate signal line 104, the TFT 110 is turned on, and a digital video signal is written to the memory circuit A3.

  This completes the processing of the digital video signal for one horizontal period. The period shown in FIG. 3B is a period indicated by * in FIG. By performing the above operation up to the final stage, a digital video signal for one frame is written in the memory circuits A1 to A3.

  Subsequently, the operation in the frame period β will be described. When writing to the memory circuit in the final stage is completed, the first frame is displayed. FIG. 3C illustrates a 3-bit time gray scale method. Now, the digital video signal is stored in the storage circuits A1 to A3 for each bit. Ts1 is a display period based on the first bit data, Ts2 is a display period based on the second bit data, Ts3 is a display period based on the third bit data, and the length of each display period is Ts1: Ts2: Ts3 = 4 : 2: 1.

  However, the display can be performed even if the display period is displayed by gradation other than a power of 2.

  Here, since it is 3 bits, 8 levels from 0 to 7 can be obtained. When display is not performed in any period of Ts1 to Ts3, brightness 0 is obtained, and brightness is obtained 7 when display is performed using all periods. For example, when it is desired to display the luminance 5, the pixel may be turned on at Ts1 and Ts3 and displayed.

  This will be specifically described with reference to the drawings. When the display period is started after the writing operation to the memory circuit is completed, the pulse input to the memory circuit selection signal line 413 is completed, and at the same time, the pulse is input to the memory circuit selection signal line 414 to write TFT 401 for writing. , 405, and 409 are in a non-conducting state, and the reading TFTs 402, 406, and 410 are in a conducting state, so that reading from the memory circuits A1 to A3 is possible. At Ts1, a pulse is input to the readout gate signal line 105, the TFT 111 is turned on, and the pixel is driven in accordance with the digital video signal stored in the memory circuit A1. Subsequently, at Ts2, a pulse is input to the readout gate signal line 106, the TFT 112 is turned on, and the pixel is driven in accordance with the digital video signal stored in the memory circuit A2. Finally, at Ts3, a pulse is input to the readout gate signal line 107, the TFT 113 is turned on, and a voltage is applied to the pixel by the digital video signal stored in the memory circuit A3.

  As described above, display for one frame period is performed. On the other hand, on the drive circuit side, processing of the digital video signal in the next frame period is simultaneously performed. The procedure up to the transfer of the digital video signal to the second latch circuit is the same as described above. In the subsequent writing period to the memory circuit, the memory circuits B1 to B3 are used.

  Note that the writing TFTs 401, 405, and 409 to the storage circuits A1 to A3 are conductive during the period in which signals are written to the storage circuits A1 to A3, but at the same time, the reading TFTs 404 and 408 from the storage circuits B1 to B3 are conductive. 412 is also conducting. Similarly, when the reading TFTs 402, 406, and 410 from the memory circuits A1 to A3 are turned on, the writing TFTs 403, 407, and 411 to the memory circuits B1 to B3 are also turned on at the same time. In a certain frame period, writing and reading are alternately performed.

  In the period I, a pulse is input to the writing gate signal line 102, the TFT 108 is turned on, and a digital video signal is written to the memory circuit B1. Subsequently, in a period II, a pulse is input to the writing gate signal line 103, the TFT 109 is turned on, and a digital video signal is written to the memory circuit B2. Lastly, in period III, a pulse is input to the write gate signal line 104, the TFT 110 is turned on, and a digital video signal is written to the memory circuit B3.

  Subsequently, in the frame period γ, the second frame is displayed according to the digital video signal stored in the storage circuits B1 to B3. At the same time, processing of the digital video signal in the next frame period is started. This digital video signal is stored again in the storage circuits A1 to A3 where the display of the first frame has been completed.

  Thereafter, the display of the digital video signal stored in the storage circuits A1 to A3 is performed in the frame period δ, and at the same time, the processing of the digital video signal in the next frame period is started. This digital video signal is stored again in the storage circuits B1 to B3 that have finished displaying the second frame.

  The video is displayed by repeating the above procedure. When displaying a still image, when the writing of the digital video signal of a certain frame to the memory circuit is completed, the source signal line driver circuit is stopped and the signal written to the same memory circuit is transmitted every frame. To read and display. With such a method, power consumption during display of a still image can be greatly reduced.

  In this embodiment, an example is described in which the second latch circuit of the source signal line driver circuit is omitted by performing writing to the memory circuit of the pixel portion in a dot sequential manner.

  FIG. 5 shows a configuration of a source signal line driver circuit and some pixels in a liquid crystal display device using a pixel having a memory circuit. This circuit corresponds to a 3-bit digital gradation signal and includes a shift register circuit 501, a latch circuit 502, and a pixel 503. 510 is a signal directly supplied from the gate signal line driving circuit or from the outside, and will be described later together with the description of the pixel.

  FIG. 20 is a detailed diagram of the circuit configuration of the pixel 503 shown in FIG. Similar to the first embodiment, it corresponds to 3-bit digital gradation, and includes a liquid crystal element (LC), a storage capacitor (Cs), storage circuits (A1 to A3 and B1 to B3), and the like. FIG. 6 shows a configuration in which the write memory circuit selectors 2014, 2016, and 2018 and the read memory circuit selectors 2015, 2017, and 2019 are configured according to the first embodiment. Reference numeral 601 denotes a first bit (MSB) signal source signal line, 602 denotes a second bit signal source signal line, 603 denotes a third bit (LSB) signal source signal line, 604 denotes a write gate signal line, and 605 to 607. Are read gate signal lines, 608 to 610 are write TFTs, and 611 to 613 are read TFTs. The memory circuit selection unit is configured using write selection TFTs 614, 616, 618, 620, 622, 624, read selection TFTs 615, 617, 619, 621, 623, 625, and the like. Reference numerals 626 and 627 denote memory circuit selection signal lines.

  FIG. 7 is a timing chart relating to driving of the circuit shown in this embodiment. This will be described with reference to FIGS.

  The operations from the shift register circuit 501 to the latch circuit (LAT1) 502 are performed in the same manner as in the first embodiment and the first embodiment. As shown in FIG. 7B, when the latch operation in the first stage is completed, writing to the pixel storage circuit is started immediately. A pulse is input to the writing gate signal line 604, the writing TFTs 608 to 610 are turned on, and further, a pulse is input to the memory circuit selection signal line 626, and the writing selection TFTs 614, 618, 622 are turned on, and the memory circuit A1. Writing to A3 becomes possible. The digital video signals for each bit held in the latch circuit 502 are simultaneously written via the three source signal lines 601 to 603.

  When the digital video signal held in the latch circuit in the first stage is written in the memory circuit, the digital video signal is held in the latch circuit in accordance with the sampling pulse that continues in the next stage. In this manner, writing to the storage circuit is sequentially performed.

  The above is performed within one horizontal period (period indicated by ** in FIG. 7A), and the number of gate signal lines is repeated, and the digital video signal for one frame in the frame period α is stored in the storage circuit. When the writing is completed, the display period of the first frame indicated by the frame period β is started. The pulse input to the write gate signal line 604 is stopped, and the pulse input to the memory circuit selection signal line 626 is stopped. Instead, the pulse is input to the memory circuit selection signal line 627 and read selection is performed. The TFTs 615, 619, and 623 are turned on, and reading from the memory circuits A1 to A3 is possible.

  Subsequently, according to the time gray scale method described in Embodiment 1, as shown in FIG. 7C, in the display period Ts1, a pulse is input to the read gate signal line 605, and the read TFT 611 is turned on to store data. Display is performed by the digital video signal written in the circuit A1. Subsequently, at Ts2, a pulse is input to the readout gate signal line 606, the readout TFT 612 is turned on, and display is performed by the digital video signal written in the memory circuit A2. Similarly, at Ts3, the readout gate is displayed. A pulse is input to the signal line 607, the readout TFT 613 is turned on, and display is performed by a digital video signal written in the memory circuit A3.

  Thus, the display period of the first frame is completed. In the frame period β, the digital video signal in the next frame is processed at the same time. The procedure up to the holding of the digital video signal in the latch circuit 502 is the same as described above. In the subsequent writing period to the memory circuit, the memory circuits B1 to B3 are used.

  Note that the writing TFTs 614, 618, and 622 to the storage circuits A1 to A3 are conductive during a period in which signals are written to the storage circuits A1 to A3. , 625 are also conducting. Similarly, when the reading TFTs 615, 619, and 623 from the storage circuits A1 to A3 are turned on, the writing TFTs 616, 620, and 624 to the storage circuits B1 to B3 are also turned on at the same time. In a certain frame period, writing and reading are alternately performed.

  Write operations and read operations to the memory circuits B1 to B3 are the same as those of the memory circuits A1 to A3. When writing to the memory circuits B1 to B3 is completed, the frame period γ is entered, and the display period of the second frame is started. Further, in this frame period, processing of the digital video signal in the next frame is performed. The procedure up to the holding of the digital video signal in the latch circuit 502 is the same as described above. In the subsequent writing period to the memory circuit, the memory circuits A1 to A3 are used again.

  Thereafter, the display of the digital video signal stored in the storage circuits A1 to A3 is performed in the frame period δ, and at the same time, the processing of the digital video signal in the next frame period is started. This digital video signal is stored again in the storage circuits B1 to B3 that have finished displaying the second frame.

  The video is displayed by repeating the above procedure. When displaying a still image, when the writing of the digital video signal of a certain frame to the memory circuit is completed, the source signal line driver circuit is stopped and the signal written to the same memory circuit is transmitted every frame. To read and display. With such a method, power consumption during display of a still image can be greatly reduced. Furthermore, compared with the circuit shown in the first embodiment, the number of latch circuits can be halved, which can contribute to the miniaturization of the entire apparatus by saving the circuit layout.

  In the present embodiment, the circuit configuration of the liquid crystal display device in which the second latch circuit is omitted as described in the second embodiment is applied, and a method of writing to the memory circuit in the pixel by line sequential driving is used. An example of a liquid crystal display device will be described.

  FIG. 17 shows a circuit configuration example of the source signal line driver circuit of the liquid crystal display device shown in this embodiment. This circuit corresponds to a 3-bit digital gradation signal, and includes a shift register circuit 1701, a latch circuit 1702, a switch circuit 1703, and a pixel 1704. Reference numeral 1710 denotes a signal supplied directly from the gate signal line driving circuit or from the outside. Since the circuit configuration of the pixel may be the same as that of the second embodiment, reference is directly made to FIG.

  FIG. 18 is a timing chart relating to driving of the circuit shown in this embodiment. This will be described with reference to FIGS. 6, 17 and 18.

  The operations until the sampling pulse is output from the shift register circuit 1701 and the digital video signal is held in accordance with the sampling pulse in the latch circuit 1702 are the same as those in the first and second embodiments. In this embodiment, since the switch circuit 1703 is provided between the latch circuit 1702 and the memory circuit in the pixel 1704, even when the digital video signal is held in the latch circuit, the memory circuit is immediately supplied. Writing does not start. The switch circuit 1703 remains closed until the end of the dot data sampling period, and the digital video signal continues to be held in the latch circuit during that time.

  As shown in FIG. 18B, when the holding of the digital video signal for one horizontal period is completed, a latch signal (Latch Pulse) is input during the subsequent blanking period, and the switch circuit 1703 is opened all at once. Digital video signals held in the circuit 1702 are written to the storage circuit in the pixel 1704 all at once. The operation in the pixel 1704 related to the writing operation at this time and the operation in the pixel 1704 related to the re-reading operation of the display in the next frame period may be the same as those in the second embodiment. Omitted.

  With the above method, line-sequential writing driving can be easily performed even in the source signal line driving circuit in which the latch circuit is omitted.

  In this embodiment, TFTs of a pixel portion and a driver circuit portion (a source signal line side driver circuit, a gate signal line side driver circuit, and a pixel selection signal line side driver circuit) provided around the pixel portion of the display device of the present invention are manufactured at the same time. How to do will be described. However, in order to simplify the description, a CMOS circuit which is a basic unit is illustrated in the drive circuit portion.

First, as shown in FIG. 10A, a silicon oxide film on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass, A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, a silicon oxynitride film 5002a made of SiH ₄ , NH ₃ , and N ₂ O is formed by plasma CVD method to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly, SiH ₄ and N _A silicon oxynitride silicon film 5002b formed from ₂ O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

  The island-shaped semiconductor layers 5003 to 5006 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The island-like semiconductor layers 5003 to 5006 are formed with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 [kHz], and the laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ]. / cm ² ]). Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 Perform as ~ 98 [%].

Next, a gate insulating film 5007 is formed to cover the island-shaped semiconductor layers 5003 to 5006. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to obtain a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], and a high frequency (13.56). [MHz]), and can be formed by discharging at a power density of 0.5 to 0.8 [W / cm ² ]. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

  Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed with Ta to a thickness of 50 to 100 [nm], and the second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

  The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. From this, in the case of the sputtering method, by using a W target having a purity of 99.9999 [%] and further forming a W film with sufficient consideration so that impurities are not mixed in from the gas phase during film formation, A resistivity of 9 to 20 [μΩcm] can be realized.

  Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a desirable example of a combination other than this embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN), the second conductive film 5009 is W, and the first conductive film 5008 is nitrided. Examples include a combination of tantalum (TaN) and the second conductive film 5009 made of Al, a combination of the first conductive film 5008 made of tantalum nitride (TaN) and the second conductive film 5009 made of Cu, and the like. It is done.

Next, a resist mask 5010 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and a coil type electrode of 500 [W] is applied at a pressure of 1 [Pa]. RF (13.56 [MHz]) power is applied to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the overetching process. become. Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched and thinned by about 20 to 50 [nm].
(Fig. 10 (A))

Then, an impurity element imparting N-type is added by performing a first doping process. As a doping method, an ion doping method or an ion implantation method may be used. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [keV]. As an impurity element imparting N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5016 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5017 to 5020 are formed in a self-aligning manner. An impurity element imparting N-type conductivity is added to the first impurity regions 5017 to 5020 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ]. (Fig. 10 (B))

Next, as shown in FIG. 10C, a second etching process is performed without removing the resist mask. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, second shape conductive layers 5021 to 5026 (first conductive layers 5021a to 5026a and second conductive layers 5021b to 5026b) are formed by the second etching process. At this time, in the gate insulating film 5007, regions that are not covered with the second shape conductive layers 5021 to 5026 are further etched by about 20 to 50 [nm] to form thin regions.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the impurity amount imparting N-type is doped as a condition of a high acceleration voltage by lowering the dose than the first doping treatment. For example, the acceleration voltage is set to 70 to 120 [keV] and the dose is 1 × 10 ¹³ [atoms / cm ² ], and the inside of the first impurity region formed in the island-shaped semiconductor layer in FIG. Then, a new impurity region is formed. Doping is performed using the second shape conductive layers 5021 to 5026 as masks against the impurity elements, so that the impurity elements are also added to the semiconductor layers in the regions below the first conductive layers 5021a to 5026a. Thus, second impurity regions 5027 to 5031 are formed. The concentration of phosphorus (P) added to the second impurity regions 5027 to 5031 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 5021a to 5026a. Note that in the semiconductor layer overlapping the tapered portions of the first conductive layers 5021a to 5026a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 5021a to 5026a, the semiconductor layers are almost The concentration is similar.

Subsequently, a third etching process is performed as shown in FIG. CHF ₆ is used as an etching gas and a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 5021a to 5026a are partially etched, and the region where the first conductive layer overlaps with the semiconductor layer is reduced. The third shape conductive layers 5032 to 5037 (first conductive layers 5032a to 5037a and second conductive layers 5032b to 5037b) are formed by the third etching treatment. At this time, in the gate insulating film 5007, a region which is not covered with the third shape conductive layers 5032 to 5037 is further etched and thinned by about 20 to 50 [nm].

  By the third etching process, in the second impurity regions 5027 to 5031, the second impurity regions 5027 a to 5031 a overlapping with the first conductive layers 5032 a to 5037 a, the first impurity regions, and the second impurity regions The third impurity regions 5027b to 5031b are formed.

Then, as shown in FIG. 11C, fourth impurity regions 5039 to 5044 having a conductivity type opposite to the first conductivity type are formed in the island-shaped semiconductor layer 5004 forming the P-channel TFT. Using the third shape conductive layer 5033b as a mask for the impurity element, an impurity region is formed in a self-aligning manner. At this time, the island-shaped semiconductor layers 5003 and 5005, the storage capacitor portion 5006, and the wiring portion 5034 that form the N-channel TFT are covered with the resist mask 5038 over the entire surface. Phosphorus is added to the impurity regions 5039 to 5044 at different concentrations. The impurity regions 5039 to 5044 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / cm ³ ].

  Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5032, 5033, 5035, and 5036 overlapping with the island-shaped semiconductor layers function as gate electrodes. Reference numeral 5034 functions as an island-shaped source signal line. 5037 functions as a capacitor wiring.

  After the resist mask 5038 is removed, a step of activating the impurity element added to each island-shaped semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.

  Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, the first interlayer insulating film 5045 is formed from a silicon oxynitride film with a thickness of 100 to 200 [nm]. A second interlayer insulating film 5046 made of an organic insulating material is formed thereon. Next, an etching process for forming a contact hole is performed.

  Then, source wirings 5047 and 5048 for forming a contact with the source region of the island-shaped semiconductor layer and a drain wiring 5049 for forming a contact with the drain region are formed in the driver circuit portion. In the pixel portion, connection electrodes 5050 and pixel electrodes 5051 and 5052 are formed (FIG. 12A). With the connection electrode 5050, the source signal line 5034 is electrically connected to the pixel TFT. Note that the pixel electrode 5052 and the storage capacitor belong to adjacent pixels.

  As described above, the driver circuit portion including the N-channel TFT and the P-channel TFT and the pixel portion including the pixel TFT and the storage capacitor can be formed over the same substrate. In this specification, such a substrate is called an active matrix substrate.

  In this embodiment, the end portions of the pixel electrodes are arranged so as to overlap the signal lines and the scanning lines so that the gaps between the pixel electrodes can be shielded without using a black matrix.

  Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing the active matrix substrate is 5 (island semiconductor layer pattern, first wiring pattern (scanning line, signal line, capacitive wiring), P The mask pattern of the channel region, the contact hole pattern, and the second wiring pattern (including the pixel electrode and the connection electrode) can be used. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

  Subsequently, after obtaining an active matrix substrate in the state of FIG. 12B, an alignment film 5053 is formed over the active matrix substrate and a rubbing process is performed.

  On the other hand, a counter substrate 5054 is prepared. Color filter layers 5055 to 5057 and an overcoat layer 5058 are formed on the counter substrate 5054. The color filter layer is formed by overlapping a red color filter layer 5055 and a blue color filter layer 5056 above the TFT to serve as a light shielding film. Since at least the TFT and between the connection electrode and the pixel electrode need to be shielded from light, it is preferable to arrange the red color filter and the blue color filter so as to shield the positions thereof.

  In addition, a red color filter layer 5055, a blue color filter layer 5056, and a green color filter layer 5057 are overlapped with the connection electrode 5050 to form a spacer. Each color filter is made of acrylic resin mixed with a pigment and is formed with a thickness of 1 to 3 [μm]. This can be formed in a predetermined pattern using a photosensitive material and a mask. The height of the spacer can be set to 2 to 7 [μm], preferably 4 to 6 [μm] in consideration of the thickness of the overcoat layer 5058 of 1 to 4 [μm]. A gap is formed when the substrate and the counter substrate are bonded together. The overcoat layer 5058 is formed of a photo-curing or thermosetting organic resin material, and for example, polyimide or acrylic resin is used.

  The arrangement of the spacers may be arbitrarily determined. For example, as shown in FIG. 12B, the spacers may be arranged on the counter substrate 5054 so as to be positioned on the connection electrodes. In addition, a spacer may be provided over the counter substrate 5054 so as to be aligned with the TFT of the driver circuit portion. This spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source wiring and the drain wiring.

  After the overcoat layer 5058 is formed, the counter electrode 5059 is formed by patterning, and after the alignment film 5060 is formed, a rubbing process is performed.

  Then, the active matrix substrate on which the pixel portion and the driver circuit portion are formed and the counter substrate are attached to each other with a sealant 5062. A filler is mixed in the sealant 5062, and two substrates are bonded to each other with a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 5061 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 5061. Thus, the active matrix liquid crystal display device shown in FIG. 12B is completed.

  Note that the TFT in the active matrix liquid crystal display device produced by the above process has a top gate structure, but this embodiment can be easily applied to a TFT having a bottom gate structure and other structures. obtain.

  In this embodiment, the glass substrate is used. However, the present invention is not limited to the glass substrate, and can be implemented by using a substrate other than the glass substrate, such as a plastic substrate, a stainless steel substrate, and a single crystal wafer. is there.

  In the display device of the present invention, a time gray scale method is used as a gray scale expressing means. Therefore, when a liquid crystal element is used for a pixel, a quicker response speed is required as compared with a normal analog gray scale method. Therefore, it is desirable to use a ferroelectric liquid crystal (FLC). . In this embodiment, an example of manufacturing a substrate in the case where a ferroelectric liquid crystal is used for a liquid crystal element in the display device manufacturing process introduced in Embodiment 4 will be described. FIG. 9 is used for the description.

  In accordance with Embodiment 4, an active matrix substrate (similar to FIG. 12A) and a counter substrate 5054 shown in FIG. 9A are formed.

  Alignment films 5101 and 5102 are formed on the active matrix substrate and the counter substrate. An alignment film RN1286 manufactured by Nissan Chemical Industries, Ltd. was formed, pre-baked at 90 ° C. for 5 minutes, and then post-baked at 250 [° C.] for 1 hour. The film thickness after post-baking was 40 [nm]. The alignment film may be formed by flexographic printing or spinner coating. Since RN1286 has poor adhesion to the sealant, the alignment film is removed at the position where the sealant is disposed. Further, an alignment film is not formed on the alignment film on the contact pad that electrically connects the active matrix substrate and the counter substrate and the lead wire that connects the flexible printed circuit board (FPC).

  The alignment films 5101 and 5102 are rubbed. At this time, the rubbing direction when the counter substrate 5054 and the active matrix substrate are bonded to each other is set to be parallel. For rubbing treatment, YA-20R manufactured by Yoshikawa Chemical Co., Ltd. was used as a rubbing cloth. Using a rubbing apparatus manufactured by Joyo Engineering Co., Ltd., the amount of indentation was 0.25 [mm], the roll rotation speed was 100 [rpm], the stage speed was 10 [mm / sec.], And the rubbing was performed once. The diameter of the rubbing roll is 130 [mm]. After rubbing, the alignment film was cleaned by irradiating the substrate surface with a water flow.

  Next, a sealant 5103 was formed. The sealing agent can be formed into a pattern in which an injection port for a liquid crystal material is provided at one place and can be injected under vacuum.

A sealant was formed on the counter substrate using a seal dispenser manufactured by Hitachi Chemical. As the sealing agent, XN-21S manufactured by Mitsui Chemicals, Inc. was used. The sealing agent was calcined at 90 [° C.] for 30 minutes and then gradually cooled in the next 15 minutes.

It has been found that the sealing agent XN-21S can only obtain a cell gap of 2.3 to 2.6 [μm] even if hot pressing is performed. Therefore, in order to form a cell gap of 1.0 [μm], it is preferable to provide a sealant by providing a region where the thickness of the laminated film is 1.5 [μm] or thinner than that of the pixel portion. In this embodiment, a sealing material 5103 is disposed in a region where the first interlayer insulating film 5045 and the second interlayer insulating film 5046 are removed by etching.

  At the same time as forming the sealant, a conductive spacer (not shown) is formed.

  Spacers (not shown) are formed on the counter substrate or the active matrix substrate. The spacer may be sprinkled with spherical beads. Alternatively, photosensitive resin may be patterned in a dot shape or a stripe shape in the display region. The spacer prevents the liquid crystal material from having alignment defects.

  In the reflective liquid crystal display device, the cell gap is preferably 0.5 to 1.5 [μm] because of retardation. In this embodiment, the cell gap is set to 1.0 [μm] in the pixel portion.

Thereafter, the markers on the counter substrate and the active matrix substrate were aligned by a bonding apparatus manufactured by Newtom, and bonded.

Next, while applying a pressure of 0.3 to 1.0 [kgf / cm ² ] in a direction perpendicular to the substrate plane and over the entire surface of the substrate, heat curing is performed in a clean oven at 160 ° C. for 3 hours, The sealant is cured and the counter substrate and the active matrix substrate are bonded.

  A pair of substrates formed by bonding the counter substrate and the active matrix substrate is separated.

  As the liquid crystal material 5104, a ferroelectric liquid crystal exhibiting bistability, an antiferroelectric liquid crystal exhibiting tristability, or the like is used.

The liquid crystal material is heated to the isotropic phase and injected. Then, it was gradually cooled to room temperature at 0.1 [° C./min.].

As a sealant, an ultraviolet curable resin (not shown) is applied by a small dispenser so as to cover the injection port.

  Thereafter, a flexible printed wiring board (not shown) is bonded with an anisotropic conductive film (not shown) to complete an active matrix liquid crystal display device.

  If the pixel electrode of the active matrix substrate is a transparent conductive film, a transmissive liquid crystal display device can also be manufactured by the process of this embodiment. In the transmissive liquid crystal display device, the cell gap is desirably set to 1.0 to 2.5 [μm] for the purpose of suppressing retardation and the spiral structure of the ferroelectric liquid crystal.

  Since the liquid crystal display device of the present invention has a plurality of memory circuits in its pixel portion, the number of elements constituting one pixel is larger than that of a normal pixel. Therefore, in the case of a transmissive liquid crystal display device, it is considered that the luminance is insufficient due to a decrease in the aperture ratio. Therefore, the present invention is preferably applied to a reflective liquid crystal display device. In this embodiment, an example of a creation process is shown.

  In accordance with Embodiment 4, an active matrix substrate (similar to FIG. 12A) shown in FIG. Subsequently, after forming a resin film as the third interlayer insulating film 5201, a contact hole is opened in the pixel electrode portion, and a reflective electrode 5202 is formed. As the reflective electrode 5202, it is desirable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component, or a laminated film thereof.

  On the other hand, a counter substrate 5054 is prepared. In this embodiment, a counter electrode 5205 is formed on the counter substrate 5054 by patterning. The counter electrode 5205 is formed as a transparent conductive film. As the transparent conductive film, a material made of a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used.

  Although not particularly shown, a color filter layer is formed when a color liquid crystal display device is produced. At this time, it is preferable that adjacent color filter layers of different colors are formed so as to double as a light shielding film of the TFT portion.

  After that, alignment films 5203 and 5204 are formed on the active matrix substrate and the counter substrate, and a rubbing process is performed.

  Then, the active matrix substrate on which the pixel portion and the driver circuit portion are formed and the counter substrate are attached to each other with a sealant 5206. A filler is mixed in the sealant 5206, and two substrates are bonded to each other with a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 5207 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 5207. In this way, the reflective liquid crystal display device shown in FIG. 19B is completed.

  In this embodiment, not only the glass substrate but also a plastic substrate, a stainless steel substrate, a single crystal wafer, or the like other than the glass substrate can be used.

  In addition, the present invention can be easily applied to a case where a half-transmission type display device in which half of the pixels are reflective electrodes and the remaining half is a transparent electrode.

  In the pixel portion of the liquid crystal display device of the present invention shown in Embodiments 1 to 3, a static memory (Static RAM: SRAM) is used as a storage circuit, but the storage circuit is only SRAM. It is not limited to. Other examples of the memory circuit applicable to the pixel portion of the liquid crystal display device of the present invention include a dynamic memory (Dynamic RAM: DRAM). In this embodiment, an example in which a circuit is configured using these memory circuits will be introduced.

  FIG. 8A shows an example in which a DRAM is used for the memory circuits A1 to A3 and B1 to B3 arranged in the pixel. The basic configuration is the same as that of the circuit shown in the first embodiment. Regarding the DRAM used for the memory circuits A1 to A3 and B1 to B3, a DRAM having a general configuration may be used. In the present embodiment, a simple configuration and an inverter and a capacitor are used.

  The operation of the source signal line driving circuit is the same as that in the first embodiment. Here, unlike an SRAM, a DRAM includes refresh TFTs 801 to 803 because rewriting to a memory circuit (hereinafter, this operation is referred to as “refresh”) is necessary every certain period. In refresh, at a certain timing of a period during which a still image is displayed (a period during which digital video signals stored in the storage circuit are repeatedly read out and displayed), the refresh TFTs 801 to 803 are turned on, respectively, in the pixel portion. The charge is fed back to the memory circuit side.

  Further, although not particularly illustrated, the pixel portion of the liquid crystal display device of the present invention can be configured using a ferroelectric memory (Ferroelectric RAM: FeRAM) as another type of storage circuit. FeRAM is a non-volatile memory having a writing speed equivalent to that of SRAM and DRAM, and can further reduce power consumption of the liquid crystal display device of the present invention by utilizing the characteristics such as low writing voltage. In addition, the configuration can be made with a flash memory or the like.

  An active matrix display device using a drive circuit created by applying the present invention has various uses. In this embodiment, a semiconductor device incorporating a display device using a driver circuit created by applying the present invention will be described.

  Examples of such display devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, televisions, and the like. Examples of these are shown in FIGS. 15 and 16.

  FIG. 15A illustrates a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, and an antenna 2606. The present invention can be applied to the display portion 2604.

  FIG. 15B illustrates a video camera, which includes a main body 2611, a display portion 2612, an audio input portion 2613, operation switches 2614, a battery 2615, and an image receiving portion 2616. The present invention can be applied to the display portion 2612.

  FIG. 15C illustrates a mobile computer or a portable information terminal, which includes a main body 2621, a camera portion 2622, an image receiving portion 2623, operation switches 2624, and a display portion 2625. The present invention can be applied to the display portion 2625.

  FIG. 15D illustrates a head mounted display which includes a main body 2631, a display portion 2632, and an arm portion 2633. The present invention can be applied to the display portion 2632.

  FIG. 15E illustrates a television set including a main body 2641, a speaker 2642, a display portion 2643, a receiving device 2644, an amplifying device 2645, and the like. The present invention can be applied to the display portion 2643.

  FIG. 15F illustrates a portable book which includes a main body 2651, a display portion 2652, a storage medium 2653, an operation switch 2654, and an antenna 2655, and is stored on a mini disc (MD) or a DVD (Digital Versatile Disc). Data and data received by the antenna are displayed. The present invention can be applied to the display portion 2652.

  FIG. 16A illustrates a personal computer, which includes a main body 2701, an image input portion 2702, a display portion 2703, and a keyboard 2704. The present invention can be applied to the display portion 2703.

  FIG. 16B shows a player that uses a recording medium in which a program is recorded, and includes a main body 2711, a display portion 2712, a speaker portion 2713, a recording medium 2714, and an operation switch 2715. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2712.

  FIG. 16C illustrates a digital camera which includes a main body 2721, a display portion 2722, an eyepiece portion 2723, an operation switch 2724, and an image receiving portion (not shown). The present invention can be applied to the display portion 2722.

  FIG. 16D illustrates a one-eye head-mounted display which includes a display portion 2731 and a band portion 2732. The present invention can be applied to the display portion 2731.

The circuit diagram of the pixel of the present invention which has a plurality of memory circuits inside. FIG. 11 illustrates a circuit configuration example of a source signal line driver circuit for performing display using a pixel of the present invention. FIG. 10 is a timing chart for performing display using the pixel of the present invention. FIG. 3 is a detailed circuit diagram of a pixel of the present invention having a plurality of memory circuits therein. FIG. 10 is a diagram showing a circuit configuration example of a source signal line driver circuit that does not have a second latch circuit. FIG. 6 is a detailed circuit diagram of a pixel driven by the source signal line driving circuit of FIG. 5. FIG. 7 is a timing chart for performing display using the circuits described in FIGS. 5 and 6. FIG. 3 is a detailed circuit diagram of a pixel of the present invention when a dynamic memory is used as a memory circuit. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device including a pixel of the present invention. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device including a pixel of the present invention. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device including a pixel of the present invention. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device including a pixel of the present invention. The figure which shows simply the whole circuit structure of the conventional liquid crystal display device. The figure which shows the circuit structural example of the source signal line drive circuit of the conventional liquid crystal display device. FIG. 14 illustrates an example of an electronic device to which a display device including a pixel of the present invention can be applied. FIG. 14 illustrates an example of an electronic device to which a display device including a pixel of the present invention can be applied. FIG. 10 is a diagram showing a circuit configuration example of a source signal line driver circuit that does not have a second latch circuit. FIG. 18 is a diagram illustrating a timing chart for performing display using the circuit described in FIG. 17. The figure which shows the example of a creation process of a reflection type liquid crystal display device. FIG. 6 is a circuit diagram of a pixel driven by the source signal line driver circuit of FIG. 5.

Claims (7)

In a liquid crystal display device using a digital video signal of n bits (n is a natural number of 2 or more),
Each of the plurality of pixels of the liquid crystal display device is
A first transistor;
A first selector electrically connected to one of a source or a drain of the first transistor;
M storage circuits for storing the digital video signal for m frames (m is a natural number of 2 or more), each electrically connected to the first selection unit;
A second selection unit electrically connected to each of the m memory circuits;
N sets of second transistors in which one of the source and the drain is electrically connected to the second selection unit,
The gates of the n first transistors are electrically connected to different first gate signal lines,
The other of the sources or drains of the n first transistors is electrically connected to a common source signal line,
The gates of the n second transistors are electrically connected to different second gate signal lines,
The other of the sources or drains of the n second transistors is electrically connected to a common liquid crystal element,
The digital video signal for one frame is stored in each of the n sets of storage circuits for each bit,
An n-bit gradation expression by a time gradation method is performed by associating each of the bits with the length of a display period. In a liquid crystal display device using a digital video signal of n bits (n is a natural number of 2 or more),
A plurality of pixels provided on the same substrate, a source signal line driver circuit and a gate signal line driver circuit;
Each of the plurality of pixels is
A first transistor;
A first selector electrically connected to one of a source or a drain of the first transistor;
M storage circuits for storing the digital video signal for m frames (m is a natural number of 2 or more), each electrically connected to the first selection unit;
A second selection unit electrically connected to each of the m memory circuits;
N sets of second transistors in which one of the source and the drain is electrically connected to the second selection unit,
The gates of the n first transistors are electrically connected to different first gate signal lines,
The other of the sources or drains of the n first transistors is electrically connected to a common source signal line,
The gates of the n second transistors are electrically connected to different second gate signal lines,
The other of the sources or drains of the n second transistors is electrically connected to a common liquid crystal element,
The digital video signal for one frame is stored in each of the n sets of storage circuits for each bit,
By making each of the bits correspond to the length of the display period, n-bit gradation expression by a time gradation method is performed,
The source signal line driver circuit is electrically connected to the source signal line;
The liquid crystal display device, wherein the gate signal line driver circuit is electrically connected to the first gate signal line and the second gate signal line. In a liquid crystal display device using a digital video signal of n bits (n is a natural number of 2 or more),
Each of the plurality of pixels of the liquid crystal display device is
A first transistor;
A first selector electrically connected to one of a source or a drain of the first transistor;
M storage circuits for storing the digital video signal for m frames (m is a natural number of 2 or more), each electrically connected to the first selection unit;
A second selection unit electrically connected to each of the m memory circuits;
N sets of second transistors in which one of the source and the drain is electrically connected to the second selection unit,
The gates of the n first transistors are electrically connected to a common first gate signal line,
The other of the sources or drains of the n first transistors is electrically connected to a different source signal line,
The gates of the n second transistors are electrically connected to different second gate signal lines,
The other of the sources or drains of the n second transistors is electrically connected to a common liquid crystal element,
The digital video signal for one frame is stored in each of the n sets of storage circuits for each bit,
An n-bit gradation expression by a time gradation method is performed by associating each of the bits with the length of a display period. In a liquid crystal display device using a digital video signal of n bits (n is a natural number of 2 or more),
A plurality of pixels provided on the same substrate, a source signal line driver circuit and a gate signal line driver circuit;
Each of the plurality of pixels is
A first transistor;
A first selector electrically connected to one of a source or a drain of the first transistor;
M storage circuits for storing the digital video signal for m frames (m is a natural number of 2 or more), each electrically connected to the first selection unit;
A second selection unit electrically connected to each of the m memory circuits;
N sets of second transistors in which one of the source and the drain is electrically connected to the second selection unit,
The gates of the n first transistors are electrically connected to a common first gate signal line,
The other of the sources or drains of the n first transistors is electrically connected to a different source signal line,
The gates of the n second transistors are electrically connected to different second gate signal lines,
The other of the sources or drains of the n second transistors is electrically connected to a common liquid crystal element,
The digital video signal for one frame is stored in each of the n sets of storage circuits for each bit,
By making each of the bits correspond to the length of the display period, n-bit gradation expression by a time gradation method is performed,
The source signal line driver circuit is electrically connected to the source signal line;
The liquid crystal display device, wherein the gate signal line driver circuit is electrically connected to the first gate signal line and the second gate signal line. In claim 2 or claim 4 ,
The liquid crystal display device, wherein the substrate is a glass substrate, a plastic substrate, or a stainless steel substrate. In any one of Claims 1 thru | or 5 ,
The liquid crystal display device, wherein the memory circuit is a static memory (SRAM), a ferroelectric memory (FeRAM), or a dynamic memory (DRAM). The electronic device using the said liquid crystal display device as described in any one of Claims 1 thru | or 6 .

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