JP5121386B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and is particularly applicable to a liquid crystal display device using a so-called intra-pixel selector method. According to the present invention, in a plurality of liquid crystal cells assigned to one selector by the intra-pixel selector method, the capacity between the pixel electrode and the scanning line of the corresponding gate signal increases as the liquid crystal cell later sets the pixel electrode potential. By doing so, application of a DC electric field to the liquid crystal is prevented between a plurality of liquid crystal cells assigned to one selector.

  Conventionally, in a liquid crystal display device, a display unit is formed by arranging pixels in a matrix, and a vertical driving unit and a horizontal driving unit are provided around the display unit. The liquid crystal display device sequentially connects each pixel to a signal line under the control of a vertical drive unit via a scanning line, and sets the gradation of each pixel by a horizontal drive unit, thereby displaying a desired image on the display unit. .

  This type of liquid crystal display device is also provided with a method of setting the gradation of each pixel by a so-called intra-pixel selector method. Here, the intra-pixel selector method is a method in which a selector is provided in a display unit in units of a plurality of pixels, and gradations of a plurality of liquid crystal cells constituting the plurality of pixels are sequentially set by the selector.

  Here, FIG. 18 is a connection diagram showing a basic unit of the liquid crystal display device by this intra-pixel selector method. The basic unit 1 is a structural unit of a display unit using the intra-pixel selector method. In the liquid crystal display device, the basic unit 1 is arranged in a matrix to form a display unit. In the example of FIG. 18, the basic unit 1 is provided with one selector 3 for three sub-pixels including red, green, and blue liquid crystal cells 2R, 2G, and 2B. In the basic unit 1, the red, green, and blue liquid crystal cells 2R, 2G, and 2B have a common electrode commonly connected to a signal line, and the signal line is connected to a drive power source for the common electrode (not shown). CsR, CsG, and CsB are storage capacitors, one end of which is connected to the pixel electrodes of the liquid crystal cells 2R, 2G, and 2B, respectively, and the other end is supplied with a precharge drive signal CS. The red, green, and blue liquid crystal cells 2R, 2G, and 2B are connected to the NMOS transistor Q2 through NMOS transistors Q1R, Q1G, and Q1B whose pixel electrodes are turned on and off by gate signals GATE, GATEG, and GATEB, respectively. Is turned on / off by the blue gate signal GATEB to connect the transistors Q1R, Q1G, Q1B to the signal line SIG.

  In the basic unit 1, as shown in FIG. 19, the voltage of the signal line SIG is set to a voltage corresponding to the gray scales of the red, green, and blue liquid crystal cells 2R, 2G, and 2B in a time division manner by the horizontal drive unit. (FIG. 19A). In FIG. 19, voltages corresponding to the gradations of the liquid crystal cells 2R, 2G, and 2B are indicated by reference characters R, G, and B. The basic unit 1 is sequentially set to the OFF state after the transistors Q1R, Q1G, Q1B, and Q2 are set to the ON state by the gate signals GATER, GATEG, and GATEB in conjunction with the setting of the voltage of the signal line SIG. (FIG. 19 (B1), (B2), (B3)). That is, the transistors Q1R, Q1G, Q1B, and Q2 are turned on and connected to the red liquid crystal cell 2R while the voltage of the signal line SIG is set to the voltage R corresponding to the gradation of the red liquid crystal cell 2R. The transistor Q1R thus switched is turned off, thereby setting the voltage VR of the pixel electrode of the red liquid crystal cell 2R to the voltage R of the signal line SIG (FIG. 19 (C1)). Subsequently, the transistor Q1G connected to the green liquid crystal cell 2G is switched to an off state during the period in which the voltage of the signal line SIG is set to the voltage G corresponding to the gray level of the green liquid crystal cell 2G. The voltage VG of the 2G pixel electrode is set to the voltage G of the signal line SIG (FIG. 19 (C2)). Subsequently, the transistor Q1B connected to the blue liquid crystal cell 2B is switched off together with the transistor Q2 during the period when the voltage of the signal line SIG is set to the voltage B corresponding to the gradation of the blue liquid crystal cell 2B. The voltage VB of the pixel electrode of the blue liquid crystal cell 2B is set to the voltage B of the signal line SIG (FIG. 19 (C3)).

  Regarding such a liquid crystal display device, Japanese Patent Laid-Open No. 9-243959 discloses a configuration in which a memory is provided for each pixel, and each pixel is driven according to the recording of this memory. Hereinafter, this method is called a memory method. According to this memory system, once the gradation of each pixel is set, the gradation setting process for each pixel can be omitted, so that power consumption can be reduced.

  In the basic unit 1 of the intra-pixel selector system shown in FIG. 19, as shown in FIG. 20, there is a capacitance between the scanning lines of the gate signals GATE, GATEG, and GATEB and the pixel electrodes of the liquid crystal cells 2R, 2G, and 2B. Cg is generated. Here, CgRR, CgRG, and CgRB are capacitances between the pixel electrode of the red liquid crystal cell 2R and the scanning lines of the gate signals GATER, GATEG, and GATEB, respectively. CgGR, CgGG, and CgGB are capacitances between the pixel electrode of the green liquid crystal cell 2G and the scanning lines of the gate signals GATER, GATEG, and GATEB, respectively. CgBR, CgBG, and CgBB are capacitances between the pixel electrode of the blue liquid crystal cell 2B and the scanning lines of the gate signals GATER, GATEG, and GATEB, respectively.

  As a result, in the basic unit 1, when the signal level of the gate signals GATE, GATEG, and GATEB changes due to the gate coupling by these capacitors Cg, the potentials VR, VG of the pixel electrodes set in the respective liquid crystal cells 2R, 2G, 2B. , VB changes.

  In the basic unit 1, as shown in FIG. 21 in comparison with FIG. 19, first, the transistor Q1R is turned off by the red gate signal GATER to set the gradation of the red liquid crystal cell 2R, and then the green color is sequentially changed. The gray levels of the green liquid crystal cell 2G and the blue liquid crystal cell 2B are set by turning off the transistors Q1G and Q1B by the gate signals GATEG and GATEB for blue and the red liquid crystal cell 2R. Each time the signal levels of the blue and blue gate signals GATE, GATEG, and GATEB fall, the potential VR of the pixel electrode falls. In the green liquid crystal cell 2G, the potential VG of the pixel electrode sequentially falls due to the fall of the signal levels of the green and blue gate signals GATEG and GATEB. In the blue liquid crystal cell 2B, the potential VB of the pixel electrode falls due to the fall of the signal level of the blue gate signal GATEB.

  As a result, in the basic unit 1, the potential VR, the potential VG, and the potential VB set to the pixel electrode through the signal line SIG are changed, and the change amounts ΔVR, ΔVG, and ΔVB are the red liquid crystal cell 2R and the green liquid crystal cell 2G. The blue liquid crystal cell 2B becomes smaller in this order. The change amounts ΔVR, ΔVG, ΔVB of the potential VR, the potential VG, and the potential VB of the pixel electrode are generated by driving with the gate signals GATER, GATEG, and GATEB, and thus are caused by field inversion, frame inversion, line inversion, and the like. Even when the driving of each signal line SIG is switched, it is held at a substantially constant value.

As a result, the intra-pixel selector method has a problem in that a DC electric field is applied to the liquid crystal between a plurality of liquid crystal cells to which one selector is assigned. If a direct current electric field is continuously applied to the liquid crystal in this way, the liquid crystal deteriorates in the liquid crystal display device.
Japanese Patent Laid-Open No. 9-243995

  The present invention has been made in consideration of the above points, and intends to propose a liquid crystal display device capable of preventing application of a DC electric field to liquid crystal when each liquid crystal cell is driven by an in-pixel selector method. Is.

In order to solve the above problems, the invention of claim 1 is applied to a liquid crystal display device that displays a desired image by a display unit formed by sequentially arranging basic units . The basic unit is provided for each color constituting one pixel, and is provided corresponding to each of a plurality of liquid crystal cells including a common electrode and a pixel electrode and applying an electric field to the liquid crystal, and corresponding to each of the plurality of liquid crystal cells. A storage capacitor connected to the pixel electrode of the liquid crystal cell, a signal line for supplying a gray scale signal for each color constituting each pixel in a time division manner for each basic unit, and a plurality of liquid crystals A scanning line corresponding to each cell, formed between the pixel electrode of the liquid crystal cell and the pixel electrode of the adjacent liquid crystal cell in plan view, provided for each basic unit, one end connected to the signal line, A first transistor that connects the basic unit and a signal line during an output period of a gradation signal to the basic unit, and a pixel electrode of the liquid crystal cell and the first transistor corresponding to each of the plurality of liquid crystal cells; liquid The on / off operation is performed in response to an input signal from the scanning line corresponding to the crystal cell, and the pixel electrodes of the liquid crystal cell are connected to the signal line all at the same time as the output period of the grayscale signal is started. A second transistor for releasing the connection between the liquid crystal cell and the signal line at the end of the output period of the tone value and setting the gradation of the liquid crystal cell , and based on the gradation signal, in out, as the liquid crystal cell to set the gradation by the color gradation value per order is later in the tone signal, as the capacitance between the run査線the corresponding pixel electrode of the liquid crystal cell is increased Is set.

According to the configuration of the first aspect of the invention, the liquid crystal cell in which the change in the pixel electrode voltage due to the gate coupling is smaller in which the gradation is set by the gradation value for each color in the order in the gradation signal and the pixel coupling voltage is smaller the increased capacitance between the scanning line of Ruge over preparative signal to correspond to the electrode, it is possible to increase the change of the pixel electrode voltage by the gate coupling. Accordingly, in the plurality of liquid crystal cells assigned to one selector, the difference in voltage change of the pixel electrode can be reduced, and application of a DC electric field to the liquid crystal in the plurality of liquid crystal cells can be prevented.

  According to the present invention, when each liquid crystal cell is driven by the intra-pixel selector method, application of a DC electric field to the liquid crystal can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment 1 FIG. 2 is a block diagram showing a liquid crystal display device of Embodiment 1 of the present invention. This liquid crystal display device 11 is a liquid crystal display device using an intra-pixel selector system, and a display unit 12 is formed by arranging pixels of liquid crystal cells in a matrix, and this is driven by a horizontal drive unit 13 and a vertical drive unit 14. A desired image is displayed on the display unit 12. The display unit 12 is formed by arranging predetermined basic units in a matrix, so that pixels by liquid crystal cells are arranged in a matrix.

  Here, FIG. 1 is a connection diagram showing a basic unit forming the display unit 12 in comparison with FIG. In FIG. 1, the same components as those in FIG. 18 are denoted by the corresponding reference numerals, and redundant description is omitted. In this basic unit 16, the pixel electrode and gate signals GATEG and GATEB, respectively, except for the red liquid crystal cell 2R having the largest variations ΔVR, ΔVG, and ΔVB of the pixel electrode potential VR, potential VG, and potential VB described above with reference to FIG. The pixel electrode potential correcting capacitors CG and CB are provided between the scanning lines. The basic unit 16 has the same configuration as the basic unit 1 of FIG. 18 except that the configuration relating to the pixel electrode potential correction capacitors CG and CB is different. Therefore, in this basic unit 16, the gradation of each of the liquid crystal cells 2R, 2G, 2B is sequentially set in the same manner as described in FIG.

Here, in the configuration shown in FIG. 1, the falling voltage ΔVR of the potential VR of the pixel electrode of the red liquid crystal cell 2R due to the fall of the gate signal GATER of the red liquid crystal cell 2R is the capacitance between the pixel electrode of the liquid crystal cell 2R and the ground. And a voltage obtained by dividing the voltage change of the gate signal GATER by the capacitance CgRR between the pixel electrode and the scanning line of the gate signal GATER. Therefore, this voltage change amount ΔVRR can be expressed by the following equation. Here, CtotalR is the total capacity of the capacity between the pixel electrode of the red liquid crystal cell 2R and all other parts. ΔVg is a voltage change amount of the gate signals GATER, GATEG, and GATEB.

  Further, in this red liquid crystal cell 2R, the fall amount ΔVRG of the potential VR of the pixel electrode due to the fall of the gate signal GATEG of the green liquid crystal cell 2G is similar to the capacitance between the pixel electrode of the liquid crystal cell 2R and the ground. In addition, the voltage change of the gate signal GATEG can be expressed by a voltage divided by the capacitance CgRG between the scanning lines of the gate signal GATEG. Further, in this red liquid crystal cell 2R, the fall amount ΔVRB of the potential VR of the pixel electrode due to the fall of the gate signal GATEB of the blue liquid crystal cell 2B is also similar to the capacitance between the pixel electrode of the liquid crystal cell 2R and the ground. The voltage change of the gate signal GATEB can be represented by a voltage divided by the capacitance CgRB between the electrode and the scanning line of the gate signal GATEB. Therefore, these voltage changes ΔVRG and ΔVRB can be expressed by the following equations. Here, CtotalG is the total capacitance of the capacitance between the pixel electrode of the green liquid crystal cell 2G and all other parts, and CtotalB is the sum of the pixel electrode of the blue liquid crystal cell 2B and all other parts. It is the total capacity of the capacity between.

  Therefore, the voltage drop amount ΔVR of the pixel electrode potential VR in the red liquid crystal cell 2R described above with reference to FIG. 21 can be expressed by the following equation.

  Similarly, the change amounts ΔVG and ΔVB of the pixel electrode potentials VG and VB in the green liquid crystal cell 2G and the blue liquid crystal cell 2B can be expressed by the following equations, respectively.

  When the pixel electrode potential correction capacitors CG and CB are excluded, the capacitors CgRR, CgGG, and CgBB between the pixel electrodes of the liquid crystal cells 2R, 2G, and 2B and the scanning lines of the corresponding gate signals GATER, GATEG, and GATEB. Can be made substantially equal by making the layouts of the transistors Q1R, Q1G, Q1B, etc. the same between the liquid crystal cells 2R, 2G, 2B. Therefore, when this equal capacity is set to CE, the capacity CgRR, CgGG, and CgBB can be expressed by CE, CE + CG, and CE + CB, respectively.

  Here, when CgRR and CgGG in the expressions (4) and (5) are respectively set as CE and CE + CG, and ΔVR = ΔVG, the following relational expression can be obtained.

  Since CtotalR≈CtotalG, the following relational expression can be obtained by rearranging the expression (7).

  The pixel electrode potential correcting capacitor CG has a capacitor CgRG between the pixel electrode of the red liquid crystal cell 2R and the green gate signal GATEG and the pixel electrode of the red liquid crystal cell 2R so as to satisfy the relational expression (8). And a capacitance obtained by subtracting the capacitance CgGB between the pixel electrode of the green liquid crystal cell 2G and the blue gate signal GATEB from the combined capacitance of the capacitance CgRB between the blue gate signal GATEB and the blue gate signal GATEB.

  Similarly, if CgRR and CgGB in the equations (4) and (6) are CE and CE + CB, respectively, and ΔVR = ΔVB, the following relational expression can be obtained.

  If this equation (9) is rearranged with CtotalG≈CtotalB, the following relational expression can be obtained.

  The pixel electrode potential correction capacitor CB has a capacitance CgRG between the pixel electrode of the red liquid crystal cell 2R and the green gate signal GATEG and the pixel electrode of the red liquid crystal cell 2R so as to satisfy the relational expression (10). And the combined capacity of the capacity CgRB between the blue gate signal GATEB.

  The pixel electrode potential correction capacitors CG and CB are set so as to satisfy the relational expressions (8) and (10). As shown in FIG. 3 in comparison with FIG. Is set so that the voltage drops ΔVR, ΔVG, ΔVB of the pixel electrode potentials VR, VG, VB due to gate coupling in the red liquid crystal cell 2R, the green liquid crystal cell 2G, and the blue liquid crystal cell 2B are substantially equal, thereby Application of a DC electric field to the liquid crystal in the red, green, and blue liquid crystal cells 2R, 2G, and 2B can be prevented.

  FIG. 4 is a plan view showing the layout of the basic unit 16. The display unit 12 is sequentially provided with scanning lines for the gate signals GATE, GATEG, and GATEB at a constant pitch T1. In the basic unit 16, pixel electrodes 17R, 17G, and 17B for red, green, and blue are sequentially provided between adjacent scanning lines, and corresponding storage capacitors CsR, CsG, and CsB are provided. The basic unit 16 has a red liquid crystal so that the pixel electrodes 17G and 17B of the green liquid crystal cell 2G and the blue liquid crystal cell 2B overlap the scanning lines of the green and blue gate signals GATEG and GATEB by predetermined amounts TG and TB, respectively. Compared to the pixel electrode 17R of the cell 2R, the pixel electrode 17G of the green liquid crystal cell 2G and the pixel electrode 17B of the blue liquid crystal cell 2B are formed larger in the direction along the signal line SIG. Electrode potential correction capacitors CG and CB are created. The liquid crystal cells 2R, 2G, and 2B are formed by the same layout except for the layout related to the pixel electrodes 17R, 17G, and 17B and the transistor Q2.

(2) Operation of Embodiment 1 In the above configuration, in the liquid crystal display device 11 (FIG. 2), the liquid crystal provided in the display unit 12 by driving the display unit 12 by the horizontal driving unit 13 and the vertical driving unit 14. The gradation of each pixel is set by the cell, whereby a desired image can be displayed on the display unit 12.

  In the display unit 12 (FIG. 1), the pixel electrode potentials VR, VG, and VB of the adjacent red, green, and blue liquid crystal cells 2R, 2G, and 2B are passed through a selector including transistors Q1R, Q1G, Q1B, and Q2. The voltage of the signal line SIG is sequentially set, whereby the gradation of each pixel is set by the intra-pixel selector method and a desired image is displayed.

  However, in the in-pixel selector method, the signal levels of the red gate signal GATAR, the green gate signal GATEG, and the blue gate signal GATEB are switched to sequentially turn on / off the transistors Q1R, Q1G, Q1B, and Q2, and sequentially to one selector. By connecting the pixel electrodes of the assigned liquid crystal cells 2R, 2G, and 2B to the signal line SIG and setting the gradations of the plurality of liquid crystal cells 2R, 2G, and 2B, the potentials VR, VG, and VG of the pixel electrodes are set. Will be reduced by gate coupling (FIG. 20). In addition, the decrease in the potentials VR, VG, and VG of the pixel electrode is the liquid crystal cell in which the potentials VR, VG, and VG of the pixel electrode are first set among the liquid crystal cells 2R, 2G, and 2B assigned to the one selector. As a result, if no measures are taken, a direct current potential difference is generated in the pixel electrode between the plurality of liquid crystal cells 2R, 2G, and 2B assigned to the one selector, and the liquid crystal is A DC electric field is applied.

Therefore, in the liquid crystal display device 11 of this embodiment, the basic unit 16 scans the gate signals GATEG and GATEB corresponding to the pixel electrodes of the liquid crystal cells 2G and 2B, the pixel electrodes of the liquid crystal cells 2G and 2B, which later set the pixel electrode potential. The pixel electrode potential correcting capacitors CG and CB are provided so that the capacitors CgGG and CgBB between them are increased. As a result, in each basic unit 16, the liquid crystal cells 2G and 2B for setting the pixel electrode potential later, the potential of the pixel electrode is greatly lowered by the gate coupling (FIG. 3). The liquid crystal cell assigned to one selector A DC potential difference is not generated in the pixel electrode between 2R, 2G, and 2B, and application of a DC electric field to the liquid crystal is prevented.

  In the liquid crystal display device 11, the pixel electrode potential correcting capacitors CG and CB are created by overlapping the corresponding pixel electrodes and the scanning lines (FIG. 4). Application of a direct current electric field can be prevented.

(3) Effects of Embodiment 1 According to the above configuration, in a plurality of liquid crystal cells assigned to one selector by the intra-pixel selector method, the liquid crystal cell that sets the pixel electrode potential later, the gate corresponding to the pixel electrode By setting so as to increase the capacity between the signal scanning lines, it is possible to prevent the application of a DC electric field to the liquid crystal between the plurality of liquid crystal cells assigned to one selector. Therefore, the reliability of the liquid crystal display device can be improved as compared with the prior art.

  In addition, by creating an increase in capacitance between the pixel electrode and the scanning line for the corresponding gate signal by overlapping the corresponding pixel electrode and the scanning line, it is possible to apply a DC electric field to the liquid crystal with a simple configuration. Can be prevented.

  FIG. 5 is a plan view showing the layout of the basic unit in the liquid crystal display device according to Embodiment 2 of the present invention. The liquid crystal display device of this embodiment is configured in the same way as the liquid crystal display device of the embodiment 1 except that the basic unit 26 according to the layout of FIG. 5 is applied instead of the basic unit 16 according to the layout of FIG. The In this basic unit 26, instead of the pixel electrodes 17R, 17G, and 17B of the liquid crystal cells 2R, 2G, and 2G, wiring patterns 27R and 27G that connect the transistors Q1R, Q1G, and Q1B to the pixel electrodes 17R, 17G, and 17B, respectively. , 27B are overlapped with the corresponding scanning lines to create a pixel electrode potential correction capacitor.

  Therefore, in FIG. 5, in the red liquid crystal cell 2R, the wiring pattern 27R that connects the transistor Q1R to the pixel electrode 17R is formed without any overlap with the corresponding scanning line. On the other hand, in the green liquid crystal cell 2G, the wiring pattern 27G that connects the transistor Q1G to the pixel electrode 17G is created so as to overlap with the corresponding scanning line by a certain area, and the pixel electrode potential correction of the green liquid crystal cell 2G is performed. A capacity CG is created. Further, in the blue liquid crystal cell 2B, the wiring pattern 27B that connects the transistor Q1B to the pixel electrode 17B is formed so as to overlap with the corresponding scanning line in a larger area, and for correcting the pixel electrode potential of the blue liquid crystal cell 2B. A capacity CB is created.

  As in this embodiment, the same effect as that of the first embodiment can be obtained by creating a pixel electrode potential correction capacitor by overlapping the wiring pattern connecting each transistor constituting the selector with the corresponding scanning line. Can be obtained.

  FIG. 6 is a plan view showing the layout of the basic unit in the liquid crystal display device according to Embodiment 3 of the present invention. The liquid crystal display device of this embodiment is configured in the same manner as the liquid crystal display device of the embodiment 2 except that the basic unit 36 according to the layout of FIG. 6 is applied instead of the basic unit 26 according to the layout of FIG. The

  In the basic unit 36 of this embodiment, the aperture ratios of the red liquid crystal cell 2R, the green liquid crystal cell 2G, and the blue liquid crystal cell 2B are set in consideration of the transmittance of the color filter, and the red liquid crystal cell is secured in order to secure this aperture ratio. The areas of the pixel electrodes 17R, 17G, and 17B of the 2R, green liquid crystal cell 2G, and blue liquid crystal cell 2B are set. More specifically, the aperture ratio of the red liquid crystal cell 2R and the blue liquid crystal cell 2B is set to an equal value, and the aperture ratio of the green liquid crystal cell 2G is larger than the aperture ratio of the red liquid crystal cell 2R and the blue liquid crystal cell 2B. Set to a large value. As a result, in the basic unit 36, the pixel electrodes 17R and 17B in the red liquid crystal cell 2R and the blue liquid crystal cell 2B are set to have the same area, whereas the pixel electrode 17G of the green liquid crystal cell 2G has the red liquid crystal cell 2R, The pixel electrode of the blue liquid crystal cell 2B is set to have a larger area than 17R and 17B.

  Corresponding to the setting of the aperture ratio, the liquid crystal cells 2G, 2R, and 2B are arranged in the order of the green liquid crystal cell 2G, the red liquid crystal cell 2R, and the blue liquid crystal cell 2B. The brightness is optimized.

  On the other hand, a general-purpose integrated unit is applied to the horizontal drive unit and the vertical drive unit that drive the display unit by the basic unit 36, and the liquid crystal cells 2G, 2R are arranged in the same order as in the first and second embodiments. 2B gradation is set. In place of the overlap between the wiring patterns 27G and 27B and the scanning lines, as described above with respect to the first embodiment, a pixel electrode potential correcting capacitor is created by overlapping the pixel electrodes 17G and 17B and the scanning lines. Also good.

  Even if the arrangement order of the liquid crystal cells is different from the gradation setting order as in this embodiment, the same effect as in the above-described embodiment can be obtained.

  By the way, the fluctuation of the potential of the pixel electrode may be negligible due to the gate coupling by the adjacent liquid crystal cell due to the layout of the substrate on which the pixel electrode is arranged, the amplitude of the gate signals GATE, GATEG, and GATEB being reduced.

  In this case, when the gradation of each liquid crystal cell is set in the order of arrangement of the basic units, the voltage of the pixel electrode in the red and green liquid crystal cells 2R and 2G as shown in FIG. 7 in comparison with FIG. The drops ΔVR and ΔVG are substantially equal. On the other hand, according to the arrangement of the liquid crystal cells and the gradation setting order according to the configuration of the third embodiment, as shown in FIG. 8, the voltage drops ΔVG and ΔVB of the pixel electrodes in the liquid crystal cells 2G and 2B arranged at both ends are Almost equal. In comparison with FIG. 20, FIG. 9 shows the parasitic capacitance that affects the fluctuation of the pixel electrode potential in the case of the arrangement of the liquid crystal cell and the gradation setting order according to the configuration of the third embodiment.

  Therefore, in this embodiment, in the configuration of the above-described first to third embodiments, the pixel electrode potential correcting capacitor is arranged ignoring the influence of gate coupling by the adjacent liquid crystal cell. If the gate coupling by the adjacent liquid crystal cell is ignored here, the equation (7) can be expressed by the following equation.

  Therefore, since CtotalR≈CtotalG, the following relational expression can be obtained by rearranging the expression (11).

  Here, when the wiring patterns in the respective liquid crystal cells are laid out in the same manner, the relational expression CgRG≈CgGB is established, whereby the pixel electrode potential correcting capacitance CG according to the expression (12) becomes zero. Similarly, if the gate coupling by the adjacent liquid crystal cell is ignored here, the equation (9) can be expressed by the following equation.

  If this equation (13) is rearranged with CtotalG≈CtotalB, the following relational expression can be obtained.

  Thus, in the configuration of the first or second embodiment, when the pixel electrode potential correcting capacitor is disposed ignoring the influence of the gate coupling by the adjacent liquid crystal cell, the liquid crystal for setting the pixel electrode potential at the end is arranged. It can be seen that the pixel electrode potential correcting capacitor CB need only be provided in the cell 2B. Thereby, in this case, the configuration of the display panel can be simplified.

  On the other hand, in the configuration based on the arrangement of the liquid crystal cells and the gradation setting order according to the above-described third embodiment, when the pixel electrode potential correcting capacitor is arranged ignoring the influence of the gate coupling by the adjacent liquid crystal cell. Therefore, it is required that the pixel electrode potential correcting capacitors CG and CB having substantially the same capacity should be disposed in the green liquid crystal cell 2G and the blue liquid crystal cell 2B disposed at both ends by analyzing the variation in the pixel electrode potential.

  According to this embodiment, even when the influence of the gate coupling by the adjacent liquid crystal cell can be ignored, the same effects as those of the above embodiments can be obtained.

  FIG. 10 is a block diagram showing a liquid crystal display device according to Embodiment 5 of the present invention. The liquid crystal display device 41 displays, for example, a moving image or a still image based on video data output from a tuner unit, an external device, or the like (not shown) on the display unit 42 by an analog drive method, and displays various menu images and the like by a memory method. This is displayed by the unit 42. Here, the analog driving method is a method of connecting to the pixel electrode signal line of each liquid crystal cell and setting the pixel electrode potential to the potential of the signal line, and is the driving method of the above-described first to fourth embodiments.

  In the liquid crystal display device 41, an interface (I / F) 43 inputs image data SDI based on serial data sequentially indicating the gradation of each pixel and various timing signals synchronized with the image data SDI. Here, the image data SDI is image data displayed on the display unit 42 by an analog driving method. The interface 43 receives binary image data DV to be displayed on the display unit 42 from the controller 44 by a memory method, and outputs the input image data SDI, DV and various timing signals to each unit according to the control of the controller 44. .

  The timing generator (TG) 45 generates various timing signals necessary for the memory method and the analog driving method under the control of the controller 44 and outputs them to the horizontal driving unit 46 and the vertical driving unit 47. Further, the drive power supply VCOM for the common electrode of the liquid crystal cell is generated and output to the display unit 42. In this embodiment, the display unit 42 may be any of a reflective type, a transmissive type, and a combined type of a reflective type and a transmissive type.

  The horizontal drive unit 46 switches the operation between an analog drive method and a memory method under the control of the controller 44. In the analog drive method, the image data SDI input from the interface 43 is sequentially distributed to each signal line SIG to perform digital-analog conversion processing. Then, the drive signal Ssig of each signal line SIG is generated by field inversion, frame inversion, line inversion, and the like. The horizontal drive unit 46 outputs the drive signal Ssig to each signal line SIG of the display unit 42 in the analog drive method.

  In the memory system, the horizontal drive unit 46 outputs a drive signal Sdv corresponding to the logical value of the binary image data DV output from the controller 44 to the corresponding signal line SIG, and then outputs a predetermined drive signal XCS. Output to line.

  The vertical drive unit 47 switches operation between the analog drive method and the memory method under the control of the controller 44 and outputs a predetermined drive signal to the scanning lines of the display unit 42.

  The display unit 42 operates in accordance with various signals output from the horizontal drive unit 46 and the vertical drive unit 47, and displays an image based on the image data SDI or DV. Here, FIG. 11 is a connection diagram showing a basic unit of the display unit 42. In the basic unit 51 of FIG. 11, the same components as those of the basic unit 16 of the first embodiment are denoted by the corresponding reference numerals, and redundant description is omitted.

  Here, in the analog drive system, the basic unit 51 connects each liquid crystal cell 2R, 2G, 2B to the signal line SIG via the selector 3 and the NMOS transistor Q3, and adjusts the gradation of each liquid crystal cell 2R, 2G, 2B. Set sequentially. In the memory system, after the setting of the signal line SIG is recorded in the memory unit 52, the setting of the signal line SIG recorded in the memory unit 52 is changed to the liquid crystal cells 2R, 2G, 2B by the selector 3 and the NMOS transistors Q3 and Q4. The gradations of these liquid crystal cells 2R, 2G, 2B are sequentially set.

  In the basic unit 51, the gradation settings of the liquid crystal cells 2R, 2G, and 2B by the selector 3 are executed in the same order as described above with respect to the first and second embodiments, thereby the green and blue liquid crystal cells 2G and 2B. In addition, pixel electrode potential correction capacitors CG and CB are provided. The pixel electrode potential correcting capacitors CG and CB are set to be the same as those described in the first and second embodiments. It should be noted that the gradation of the liquid crystal cells 2R, 2G, and 2B is set in the order described above for the third embodiment, and the pixel electrode potential correction capacitor is provided by applying the method of the third embodiment. Also good.

  That is, in the display unit 42, the basic units shown in FIG. 11 are arranged in a matrix so that the red, green, and blue liquid crystal cells 2R, 2G, and 2B are sequentially and continuously arranged. 2B are arranged in a matrix.

  In the basic unit 51, the storage capacitors CsR, CsG, and CsB of the red, green, and blue liquid crystal cells 2R, 2G, and 2B are supplied with a drive signal CS related to precharge processing at one end and correspond to the other ends, respectively. Connected to the pixel electrodes of the liquid crystal cells 2R, 2G, and 2B. In the liquid crystal cells 2R, 2G, and 2B, a driving power source VCOM whose signal level is switched in conjunction with the driving signal CS is supplied to the common electrode.

  In the basic unit 51, the memory unit 52 includes an SRAM (CMOS (SRAM)) composed of a CMOS inverter composed of an NMOS transistor Q5 and a PMOS transistor Q6 each having a common gate and drain, and a CMOS inverter composed of the same NMOS transistor Q7 and PMOS transistor Q8. Static Random Access Memory), which outputs an output RAM corresponding to the logic level of the signal line SIG and an inverted output at a logic level opposite to this output RAM to the transistors Q3 and Q4, respectively, and complements these transistors Q3 and Q4. On / off control. The memory unit 52 is connected to the signal line SIG via the NMOS transistor Q11 that is turned on by the gate signal GATED.

  As shown in FIGS. 12 and 13, in the case of the analog driving method, the basic unit 51 has the memory unit 52 in advance so as to set the transistor Q3 to the on state by the horizontal driving unit 46 and the vertical driving unit 47. After the setting (FIGS. 12D to 12E), the setting of the gate signals GATER, GATEG, and GATEB is sequentially switched (FIGS. 12B1 to B3), as shown in FIG. The liquid crystal cells 2R, 2G, and 2B are sequentially connected to the signal line SIG. Here, FIG. 13 is a diagram showing the configuration of the basic unit 51 in a simplified manner by comparison with FIG. 11 for explaining the connection between the signal line SIG and the liquid crystal cells 2R, 2G, and 2B.

  Further, in the case where the basic unit 51 is based on the analog drive method, the horizontal drive unit 46 applies the drive signal Ssig of the signal line SIG to the gradation voltages R, G, and B indicating the gradations of the liquid crystal cells 2R, 2G, and 2B, respectively. The gate signals GATER, GATEG, and GATEB are sequentially switched so as to correspond to the setting of the signal line SIG (FIG. 12A) (FIGS. 12B1 to 12B3). Thereby, in the basic unit 51, the pixel electrode potentials VR, VG, VB of the liquid crystal cells 2R, 2G, 2B are set to the gradation voltages R, G, B by the drive signal Ssig. Thus, the basic unit 51 sets the gradation of the liquid crystal cells 2R, 2G, and 2B by an analog driving method.

  On the other hand, as shown in FIGS. 14 and 15, when the memory unit 52 is set in advance in the analog drive method and written in the memory method, the basic unit 51 uses the gate signals GATER, GATEG, and GATEB to generate transistors Q1R, Q1G, Q1B and Q2 are set to an off state (FIGS. 14 (B1) to (B3) and (C1) to (C3)), and the power supply voltage VRAM of the memory unit 52 is temporarily set to the voltage VDD corresponding to the H level of the signal line SIG. The transistor Q11 is turned on by the gate signal GATED and the memory unit 52 is connected to the signal line SIG (FIG. 14E). Thus, in the basic unit 51, the logic level of the drive signal Sdv output to the signal line SIG is set in the memory unit 52 (FIG. 14F). After that, in the basic unit 51, the power supply voltage VRAM is raised to the voltage VDD2 corresponding to the driving voltage of the liquid crystal cells 2R, 2G, and 2B (FIGS. 14D and 14F), and the transistors Q3 and Q4 are turned on / off. Set to be controllable. Here, FIG. 15 is a diagram showing the configuration of the basic unit 51 shown in FIG. 11 in a simplified manner for explaining the operation of the memory unit 52.

  In the basic unit 51, when the memory unit 52 is set in advance in the analog drive system, the signal line SIG is set to the H level by the horizontal drive unit 46 and these series of operations are executed, thereby setting the transistor Q3 to the on state. Set to do. On the other hand, at the time of writing by the memory method, the signal line SIG is set to the logical value of the image data DV by the horizontal driving unit 46, and thereby the logical value of the image data DV is set to the memory unit 52. When this logical value is H level, the memory unit 52 is set so as to set the transistor Q3 to the on state, whereas when this logical value is L level, the transistor Q4 is set to the on state. The memory unit 52 is set.

  Here, at the time of display by the memory system, as shown in FIGS. 16 and 17, the basic unit 51 receives the inverted signal XCS of the drive signal CS whose signal level is complementarily switched from the horizontal drive unit 46 to the drive signal CS. Is supplied to the signal line SIG (FIGS. 16A and 16B). Further, gate signals GATER, GATEG, and GATEB are supplied from the horizontal drive unit 46 so as to turn on all the transistors Q1R, Q1G, Q1B, and Q2 (FIG. 16 (C1) to (C3)). In the basic unit 51, the transistor Q3 or Q4 is selectively turned on according to the logical value set in the memory unit 52, whereby the inverted signal XCS or the drive signal CS is selectively transferred to the liquid crystal cells 2R, 2G, It is supplied to the 2B pixel electrode (FIGS. 16D1 to 16D3). Accordingly, the liquid crystal cells 2R, 2G, and 2B are set to a black gradation or a white gradation corresponding to the logical value of the image data DV set in the memory unit 52. Here, FIG. 17 is a diagram showing the configuration of the basic unit 51 shown in FIG. 11 in a simplified manner for explaining the display by this memory system.

  According to this embodiment, the same effect as that of the above-described embodiment can be obtained even when the memory method is used, and even when the memory method and the analog driving method are switched.

  In the above-described embodiment, the case where the pixel electrode potential correction capacitor is created by changing the size of the pixel electrode or by changing the shape of the wiring pattern to the pixel electrode has been described. For example, when creating a pixel electrode potential correction capacitor by shifting the position of the scanning line and setting an overlap amount with the pixel electrode, a separate electrode is created separately to create a pixel electrode potential correction capacitor. Various methods can be widely applied as a method of creating a pixel electrode potential correcting capacitor.

  In the above-described embodiment, the case where three liquid crystal cells of red, green, and blue are assigned to one selector has been described. However, the present invention is not limited to this. For example, two consecutive liquid crystal cells are assigned to one selector. In the case of assignment, the present invention can be widely applied to the case where four or more liquid crystal cells are assigned to one selector.

  The present invention can be applied to a liquid crystal display device using a so-called intra-pixel selector method.

It is a connection diagram which shows the basic unit of the liquid crystal display device of Example 1 of this invention. It is a block diagram which shows the liquid crystal display device of Example 1 of this invention. It is a time chart with which it uses for description of operation | movement of the basic unit of FIG. It is a top view which shows the layout of the basic unit of FIG. It is a top view which shows the layout of the basic unit of the liquid crystal display device of Example 2 of this invention. It is a top view which shows the layout of the basic unit of the liquid crystal display device of Example 3 of this invention. It is a time chart with which it uses for description of the influence of the gate coupling in the liquid crystal display device of Example 4 of this invention. 8 is a time chart for explaining the influence of gate coupling according to an example different from FIG. 7. It is a connection diagram with which it uses for description of the influence of the gate coupling in the liquid crystal display device of Example 4 of this invention. It is a block diagram which shows the liquid crystal display device of Example 5 of this invention. It is a connection diagram which shows the basic unit in the liquid crystal display device of Example 5 of this invention. 12 is a time chart for explaining the operation of the basic unit in FIG. 11 in the analog drive system. FIG. 12 is a connection diagram for explaining the operation of the basic unit of FIG. 11 in the analog drive system. 12 is a time chart for explaining an operation when setting a memory unit of the basic unit in FIG. 11; FIG. 12 is a connection diagram for explaining an operation when setting a memory unit of the basic unit in FIG. 11. 12 is a time chart for explaining the operation of the basic unit of FIG. 11 according to the memory system. It is a connection diagram with which it uses for description of the operation | movement by the memory system of the basic unit of FIG. It is a connection diagram which shows the basic unit of the liquid crystal display device by the selector system in a pixel. It is a time chart with which it uses for description of operation | movement of the basic unit of FIG. FIG. 19 is a connection diagram for explaining a parasitic capacitance in the basic unit of FIG. 18. It is a time chart with which it uses for description of the gate coupling in the basic unit of FIG.

Explanation of symbols

1, 16, 26, 36, 51... Basic unit, 2R, 2G, 2B... Liquid crystal cell, 3... Selector, 11, 41. Liquid crystal display device, 12, 42. 17B: Pixel electrode, 52: Memory system, CB, CG: Pixel electrode potential correction capacitor, Q1 to Q11: Transistor

Claims (6)

In a liquid crystal display device that displays a desired image on a display unit formed by sequentially arranging basic units,
The basic unit is
A plurality of liquid crystal cells which are provided for each color constituting one pixel and which have a common electrode and a pixel electrode and apply an electric field to the liquid crystal;
A storage capacitor provided corresponding to each of the plurality of liquid crystal cells and connected to the corresponding pixel electrode of the liquid crystal cell;
For each basic unit, a signal line for supplying a gradation signal for outputting time-division gradation values for each color constituting the one pixel;
A scanning line corresponding to each of the plurality of liquid crystal cells and formed between a pixel electrode of the liquid crystal cell and a pixel electrode of the liquid crystal cell adjacent in a plan view;
A first transistor provided for each basic unit, having one end connected to the signal line, and connecting the basic unit and the signal line during an output period of the gradation signal to the basic unit;
Corresponding to each of the plurality of liquid crystal cells, it is provided between the pixel electrode of the liquid crystal cell and the first transistor, and is turned on / off by an input signal from a scanning line corresponding to the liquid crystal cell . The pixel electrodes of the liquid crystal cells are connected to the signal lines all at once with the start of the output period, and at the end of the output period of the color-specific gradation value corresponding to the corresponding liquid crystal cells, the liquid crystal cells and the signal lines releasing the connection, the second transistor to set the tone of the liquid crystal cell,
Have
Based on the gradation signal, among the plurality of liquid crystal cells, as the liquid crystal cell to set the tone by the Color tone values after the order in the gradation signal, and the pixel electrode of the liquid crystal cell capacitance between the corresponding front Kihashi査線is set to increase,
Liquid crystal display device. Increase of the capacity, Ru is formed by overlapping the scanning line and the pixel electrode,
The liquid crystal display device according to claim 1. Increase of the capacity, Ru is formed by overlapping the scanning line and the wiring pattern to the pixel electrode,
The liquid crystal display device according to claim 1. In the basic unit, the liquid crystal cells having the same wiring pattern are arranged as a red liquid crystal cell corresponding to red, a green liquid crystal cell corresponding to green, and a blue liquid crystal cell corresponding to blue,
The increase in the capacitance is such that the output order of the gradation values for each color is first according to the voltage drop amount of the pixel electrode potential of the liquid crystal cell. A correction capacitor is provided between the pixel electrode of the liquid crystal cell other than the liquid crystal cell and the scanning line corresponding to the liquid crystal cell.
  The liquid crystal display device according to claim 1. When the gradation signal outputs the gradation value for each color in the order of red, green, and blue,
The correction capacitance between the pixel electrode of the green liquid crystal cell and the scanning line corresponding to the green liquid crystal cell is the pixel electrode of the red liquid crystal cell and the green liquid crystal cell in a state before setting the correction capacitance. And the capacitance between the pixel electrode of the red liquid crystal cell and the capacitance between the scan line corresponding to the blue liquid crystal cell, and the pixel electrode of the green liquid crystal cell and the blue The capacity is set by subtracting the capacity between the scanning line corresponding to the liquid crystal cell,
  The correction capacitor between the pixel electrode of the blue liquid crystal cell and the scanning line corresponding to the blue liquid crystal cell has the pixel electrode of the red liquid crystal cell and the green liquid crystal cell in a state before setting the correction capacitor. Is set to a combined capacitance of the capacitance between the scanning line corresponding to the pixel electrode of the red liquid crystal cell and the capacitance between the scanning line corresponding to the blue liquid crystal cell,
  The liquid crystal display device according to claim 4. The gradation signal outputs the gradation values for each color in the order of red, green, and blue, and the red liquid crystal cell, the green liquid crystal cell, and the blue liquid crystal cell are arranged in this order, and the influence of the liquid crystal cells that are not adjacent to each other is affected. When not considering
The increase in capacitance is caused by the pixel electrode of the red liquid crystal cell and the green liquid crystal in a state before the correction capacitor is set between the pixel electrode of the blue liquid crystal cell and the scanning line corresponding to the blue liquid crystal cell. Performing by setting the capacity between the scanning line corresponding to the cell as the correction capacity,
  The liquid crystal display device according to claim 4.

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