JP4270310B2 - Active matrix display device drive circuit, drive method, and active matrix display device - Google Patents

Description

  The present invention relates to a driving circuit and a driving method of an active matrix display device of a type in which two adjacent pixels share one signal line, and an active matrix display device using such a driving circuit.

  In recent years, active matrix display devices using thin film transistors (TFTs) as switching elements have been developed.

  This active matrix display device includes a scanning line driving circuit (hereinafter referred to as a gate driver) that generates a scanning signal for sequentially scanning a plurality of pixels arranged in a matrix for each row. The gate driver has a lower operating frequency than a signal line driver circuit (hereinafter referred to as a source driver) that supplies a video signal to each pixel. For this reason, even if the TFT and the gate driver are formed at the same time in the same process as that for forming the TFT corresponding to each pixel, the gate driver can satisfy the specifications. is there.

  Each pixel in the active matrix display device has a pixel electrode connected to the TFT and a common electrode to which a common voltage Vcom is applied. In the active matrix display device, the polarity of the video signal Vsig from the source driver is set to the frame of the common voltage Vcom in order to prevent the deterioration phenomenon of the liquid crystal that is generated by applying a unidirectional electric field for a long time. Inversion driving is generally performed to invert every line, line, or dot.

  By the way, in the implementation of the active matrix display device, the gate driver, the source driver, and the like are arranged around a display panel (display screen) in which a large number of pixels are arranged. A wiring for electrically connecting a scanning line (hereinafter referred to as a gate line) and a signal line (hereinafter referred to as a source line) in the display screen to the gate driver and the source driver is provided on the display screen. Both sides are connected by being routed outside. At this time, it is strongly desired to reduce the wiring area of these wirings, that is, to reduce the area other than the display panel (narrow frame) from the viewpoint of miniaturization of information equipment incorporating the active matrix display device. Yes.

  For this reason, in particular, the area occupied by the source lines can be reduced in response to the demand for narrowing the frame in the vertical direction of the display panel. Therefore, a pixel connection configuration in which the number of source lines is halved is considered. (For example, FIG. 5 of patent document 1).

  FIG. 19 is a schematic diagram of an example of pixel connection in a display screen, which is considered as a technique for achieving such a narrow frame. In this case, one source line is shared by two adjacent pixels 200. In this case, the TFTs 202 of the two pixels 200 are connected to different gate lines. For example, in FIG. 19, the TFT 202 of the red (R) pixel 200 in the upper left is connected to the gate line G1 and the source line S1, and the TFT 202 of the green (G) pixel 200 adjacent to the right is connected to the gate line G2 and the source. Connected to line S1.

  FIG. 20 shows the output order of the combination of the video signals Vsig according to the information to be displayed output to the plurality of source lines S1, S2, S3,. It is a figure which shows the timing chart which consists of selection order of G2, G3, .... As shown in the figure, since there are twice as many gate lines as the number of rows of pixels, the plurality of gate lines G1, G2, G3,... Are 1 in every 1/2 horizontal period (1 / 2H) in that order. One gate line is selected (becomes H signal). Then, a combination of video signals Vsig to be written to each of the pixels 200 corresponding to the selected gate line is output to a plurality of source lines S1, S2, S3,. For example, during the ½ horizontal period when the gate line G1 is selected, the combination of the video signal Vsig “S-1” is output to the plurality of source lines S1, S2, S3,. The combination of the video signal Vsig “S-2” is output to the plurality of source lines S1, S2, S3,... During the ½ horizontal period when G2 is selected.

FIG. 21 is a diagram illustrating the order in which the video signal Vsig is written to each pixel 200. In the pixel connection, the writing of the video signal Vsig to each pixel 200 is performed in the order of the gate lines as shown in FIG. 20, so that it is as shown in FIG.
JP 2004-185006 A

  In the pixel connection for halving the number of source lines as described above, there are places where there is a source line between pixels and places where there is no source line. There is a large parasitic capacitance. FIG. 22 is a diagram showing an equivalent circuit at this time. A voltage leak occurs between the pixels in which the inter-pixel parasitic capacitance 204 exists, whereby the potential of the pixel 200 written earlier is affected by the potential of the pixel 200 written later. This change in potential appears as display unevenness on the screen. Since the pixel writing order is fixed as shown in FIG. 21, display unevenness due to the occurrence of this leak always occurs at the same location.

FIG. 23 is a diagram showing an example of this display unevenness. This figure shows only the G pixel 200 for easy understanding. Here, the scanning order of the gate lines is G1 → G2 → G3 →... → G8. Further, in FIG. 23, the same is true for the potential of the pixel 200 previously written in the black-colored pixels 200 of other colors. (Details will be described later.)
Hereinafter, the pixel potential fluctuation will be described in more detail. FIG. 24 is a diagram showing the configuration of each pixel when the display panel is a TFT LCD. Each pixel 200 has a liquid crystal (not shown) between a pixel electrode connected to the source line via a TFT 202 connected to the gate line and a common electrode (not shown) to which a common voltage Vcom is applied. It is sandwiched and configured. A corresponding display is realized by holding charges in the liquid crystal capacitor Clc for a field period (a frame period in the case of the non-interlace method). In order to prevent current leakage through the liquid crystal capacitor Clc and the TFT, an auxiliary capacitor Cs is provided in parallel with the liquid crystal capacitor Clc.

  FIG. 25A is a diagram showing a scanning timing chart of the gate lines G1 to G4 by the gate driver in FIG. 24. FIG. 25B shows a common voltage Vcom every 1/2 horizontal period (1 / 2H). In the case of performing horizontal line inversion driving for inverting the polarity of the green pixel F, the green pixel F (hereinafter referred to as the G-first pixel) connected to the source line S3 in FIG. For example, it is a diagram showing a pixel potential waveform of a red pixel L (hereinafter referred to as a pixel after R) connected to the source line S2.

  Hereinafter, a case of a normally white mode liquid crystal display device in which the transmittance is lowered (darkened) as the voltage applied to the pixel is increased will be described. In FIG. 25B, the amplitude of the common voltage Vcom is 5.0 V, the write voltage (video signal Vsig) of the pixel F ahead of G is 2.0 V (halftone) with respect to the common voltage Vcom, In this example, the writing voltage (video signal Vsig) of the pixel L is set to 4.0 V (black, dark) with respect to the common voltage Vcom. In addition, since the influence of the pull-in voltage (feedthrough voltage) ΔV generated when the TFT 202 is turned from on to off can be canceled by adjusting the common voltage Vcom (shifting Vcom downward by ΔV), FIG. This is not described in the waveform (the same applies to other pixel potential waveform diagrams described below).

As shown in FIG. 25A, in each field, two gate lines are selected in a ½ horizontal period, and the selected two gate lines are sequentially scanned in each horizontal period. Then, as shown in FIG. 25B, the TFT 202 connected to the selected gate line is turned on, and the video signal Vsig applied from the source line is written to the corresponding pixel 200. Accordingly, the write timing of G-first pixel F is, _{W G} becomes in FIG. 25 (B), the writing timing of the pixel L after R becomes _{W R.} The pixel potential written at these write timings is maintained until it is rewritten in the next field.

  FIG. 25B shows a pixel potential waveform in an ideal state when the inter-pixel parasitic capacitance 204 is zero. However, as described above, the inter-pixel parasitic capacitance 204 exists in a place where there is no source line. FIG. 26A is a diagram showing a pixel potential waveform under the same voltage condition as FIG. 25B when the inter-pixel parasitic capacitance 204 is taken into consideration. In FIG. 26B, the amplitude of the common voltage Vcom when the inter-pixel parasitic capacitance 204 is taken into account is 5.0 V, the write voltage of the pixel F ahead of the G is 2.0 V with respect to the common voltage Vcom, It is a figure which shows a pixel potential waveform when the writing voltage of the pixel L is 1.0 V (white, light) with respect to the common voltage Vcom.

That is, as shown in FIGS. 26A and 26B, in the pixel F ahead of G, the pixel potential written by the selection of the gate line G1 is changed to the pixel L after R by the selection of the gate line G2. Is written, Vc is shifted in a direction away from the common voltage Vcom (direction of darkening). The magnitude of this Vc is
Vc = (Vsig (Fn−1) + Vsig (Fn)) × Cpp / (Cs + Clc + Cpp) × α (1)
It can be expressed as In this equation (1), Vsig (Fn) is the write voltage of the pixel L after R in the current field, and Vsig (Fn−1) is the write voltage of the pixel L after R in the previous field. Therefore, in the case of FIG. 26A, Vsig (Fn-1) + Vsig (Fn) = 8.0V, and in the case of FIG. 26B, Vsig (Fn-1) + Vsig (Fn) = 2.0V. Become. Cpp is the capacitance value of the inter-pixel parasitic capacitance 204, Cs is the capacitance value of the auxiliary capacitance Cs, Clc is the capacitance value of the liquid crystal capacitance Clc, and α is a proportional coefficient, which is a value determined by the panel structure and the like.

  Thus, as Vsig (Fn−1) + Vsig (Fn) is larger, the potential variation value Vc is larger and does not depend on the amplitude of Vcom.

  The above is the case of horizontal line inversion driving in which the polarity of the common voltage Vcom is different between pixels adjacent in the direction along the source line. That is, for example, in FIG. 21, between pixels connected to the gate line G1 or G2, between pixels connected to the gate line G3 or the gate line G4, between pixels connected to the gate line G5 or the gate line G6, The polarity of the common voltage Vcom is inverted between the pixels connected to the gate line G7 or the gate line G8.

  By the way, in order to invert the polarity of the common electrode Vcom, the polarity of the common voltage Vcom differs between pixels adjacent in the direction along the source line, and also the common voltage Vcom between pixels adjacent in the direction along the gate line. There is also a driving method called dot inversion driving with different polarities. In this case, in order that the polarity of the common voltage Vcom is inverted between the pixels adjacent in the vertical and horizontal directions, the gate line G1 and the gate line G4, the gate line G3 and the gate line G4, and the gate line G5 in FIG. The polarity of the common voltage Vcom is inverted between the gate lines G6 and between the gate lines G7 and G8.

  In both horizontal line inversion driving and dot inversion driving, the polarity of the common voltage Vcom in each pixel is inverted for each field.

  When such dot inversion driving is performed, the results are as shown in FIGS. 27 (A) and 27 (B). Here, in FIG. 27A, the amplitude of the common voltage Vcom in consideration of the inter-pixel parasitic capacitance 204 is 5.0 V, and the write voltage of the pixel F ahead of the G is 2.0 V (halftone) with respect to the common voltage Vcom. FIG. 27B is a diagram showing a pixel potential waveform when the write voltage of the pixel L after R is 4.0 V (black) with respect to the common voltage Vcom, and FIG. In this case, the amplitude of the common voltage Vcom is 5.0 V, the write voltage of the pixel F ahead of G is 2.0 V with respect to the common voltage Vcom, and the write voltage of the pixel L after R is 1.0 V with respect to the common voltage Vcom. It is a figure which shows a pixel electric potential waveform when it is set as (white).

  That is, as shown in FIGS. 27A and 27B, in the case of dot inversion driving, as in the case of the horizontal line inversion driving, the gate line G1 in the G-destination pixel F is performed. The pixel potential written by the selection is shifted by Vc when writing the pixel L after R by the selection of the gate line G2, but the shifting direction is different from the case of performing the horizontal line inversion driving. The direction is closer to the common voltage Vcom (the direction becomes brighter).

  Also in this case, as Vsig (Fn−1) + Vsig (Fn) is larger, the potential variation value Vc is larger and is not dependent on the amplitude of Vcom, as in the case of horizontal line inversion driving. .

  Due to the above-described fluctuation by Vc, the G-th pixel becomes darker than the actual display in the case of horizontal line inversion driving. In the case of dot inversion driving, it becomes brighter than the actual display. On the other hand, a normal voltage is written as the pixel potential of the pixel after G. Therefore, when displaying in the G raster, light and dark green are displayed every other line in the vertical direction in both inversion driving. Will end up.

  Similar fluctuations for Vc also occur in the R and B pixels.

  The above is not limited to the case where the pixels 200 are arranged in a stripe arrangement, but the same applies to a case where the pixels 200 are arranged in a delta arrangement.

  The technique disclosed in Patent Document 1 cannot deal with the problem of display unevenness due to potential fluctuations that occur in pixels written earlier due to such inter-pixel parasitic capacitance 204.

  The present invention has been made in view of the above points, and provides an active matrix display device driving circuit, a driving method, and an active matrix display device capable of reducing display unevenness when inter-pixel parasitic capacitance exists. With the goal.

The drive circuit of the active matrix display device according to claim 1, wherein one signal line is disposed for every two pixels, and two adjacent pixels across the signal line share the signal line and A drive circuit for an active matrix display device connected to different scanning lines via a switching element,
A scanning line driving circuit for selecting the plurality of scanning lines;
A signal line driving circuit for outputting a signal in accordance with information to be displayed to the plurality of signal lines;
Comprising
The scanning line driving circuit includes a first driving for sequentially selecting two scanning lines corresponding to two adjacent pixels connected to different signal lines, and the selection order of the two scanning lines according to the first order. The second driving, which is the reverse of the first driving, is alternately performed at least every one predetermined period.

  The drive circuit of the active matrix display device according to claim 2 is the drive circuit of the active matrix display device according to claim 1, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more). It is characterized by being.

  The drive circuit of the active matrix display device according to claim 3 is the drive circuit of the active matrix display device according to claim 1, wherein the predetermined period includes two periods, and the first period is a 2j scanning period. (J is an integer of 1 or more), and the second period is k field (k: an integer of 1 or more).

  The drive circuit of the active matrix display device according to claim 4 is the drive circuit of the active matrix display device according to claim 1, wherein the predetermined period is every k fields (k is an integer of 1 or more). It is characterized by being.

  The active matrix display device driving circuit according to claim 5 is the active matrix display device driving circuit according to any one of claims 1 to 4, wherein the signal line driving circuit is based on the scanning line driving circuit. A signal corresponding to the selection order of the scanning lines is output to the plurality of signal lines.

  The drive circuit for an active matrix display device according to claim 6 is the drive circuit for an active matrix display device according to any one of claims 1 to 5, wherein the display panel arranges the plurality of pixels in a stripe pattern. The display panel has a stripe arrangement.

  The drive circuit for an active matrix display device according to claim 7 is the drive circuit for an active matrix display device according to any one of claims 1 to 5, wherein the display panel arranges the plurality of pixels in a delta shape. The display panel has a delta arrangement.

The driving method of the active matrix display device according to claim 8, wherein one signal line is arranged for every two pixels, and two adjacent pixels across the signal line share the signal line and A driving method of an active matrix display device connected to different scanning lines via a switching element,
A first drive for sequentially selecting two scanning lines corresponding to two pixels connected to different signal lines and arranged adjacent to each other, and a selection order of the two scanning lines are reversed from the first driving. The second driving is alternately performed at least every predetermined period.

  The driving method of the active matrix display device according to claim 9 is the driving method of the active matrix display device according to claim 8, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more). It is characterized by being.

  The driving method of the active matrix display device according to claim 10 is the driving method of the active matrix display device according to claim 8, wherein the predetermined period includes two periods, and the first period is a 2j scanning period. (J is an integer of 1 or more), and the second period is k field (k: an integer of 1 or more).

  The drive method of the active matrix display device according to claim 11 is the drive method of the active matrix display device according to claim 8, wherein the predetermined period is every k fields (k is an integer of 1 or more). It is characterized by being.

  The drive method for an active matrix display device according to claim 12 is the drive method for an active matrix display device according to any one of claims 8 to 11, wherein information to be displayed is output to the plurality of signal lines. In accordance with the selection order of the scanning lines, the following signals are output.

  The drive method of the active matrix display device according to claim 13 is the drive method of the active matrix display device according to any one of claims 8 to 12, wherein the display panel arranges the plurality of pixels in a stripe shape. The display panel has a stripe arrangement.

  The driving method of the active matrix display device according to claim 14 is the driving method of the active matrix display device according to any one of claims 8 to 12, wherein the display panel arranges the plurality of pixels in a delta shape. The display panel has a delta arrangement.

The active matrix display device according to claim 15,
A display panel in which one signal line is arranged for every two pixels, and two adjacent pixels across the signal line share the signal line and are connected to different scanning lines via switching elements, respectively ,
A scanning line driving circuit for selecting the plurality of scanning lines;
A signal line driving circuit for outputting a signal in accordance with information to be displayed to the plurality of signal lines;
Comprising
The scanning line driving circuit includes a first driving for sequentially selecting two scanning lines corresponding to two adjacent pixels connected to different signal lines, and the selection order of the two scanning lines according to the first order. The second driving, which is the reverse of the first driving, is alternately performed at least every one predetermined period.

  The active matrix display device according to claim 16 is the active matrix display device according to claim 15, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more). To do.

  The active matrix display device according to claim 17 is the active matrix display device according to claim 15, wherein the predetermined period includes two periods, and the first period is a 2j scanning period (j: 1 or more). The second period is a k field (k: an integer of 1 or more).

  The active matrix type display device according to claim 18 is the active matrix type display device according to claim 15, wherein the predetermined period is every k fields (k is an integer of 1 or more). .

  The active matrix display device according to claim 19 is the active matrix display device according to any one of claims 15 to 18, wherein the signal line driving circuit is in the order of selection of the scanning lines by the scanning line driving circuit. A corresponding signal is output to the plurality of signal lines.

  21. The active matrix display device according to claim 20, wherein the display panel is a display panel having a stripe arrangement in which the plurality of pixels are arranged in a stripe shape. It is characterized by being.

  The active matrix display device according to claim 21 is the active matrix display device according to any one of claims 15 to 19, wherein the display panel has a delta arrangement in which the plurality of pixels are arranged in a delta shape. It is characterized by being.

  According to the present invention, when a plurality of scanning lines are sequentially selected, the selection order of two scanning lines corresponding to two pixels connected to different signal lines and adjacently arranged is changed every predetermined period. In addition, it is possible to provide a driving circuit and a driving method for an active matrix display device that can reduce display unevenness, and an active matrix display device using such a driving circuit.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1A is a schematic configuration diagram showing the overall configuration of the active matrix display device according to the first embodiment of the present invention, and FIG. 1B is an LCD panel (liquid crystal display) in FIG. It is the schematic of the pixel connection of a display panel.

  That is, as shown in FIG. 1A, the active matrix display device according to this embodiment drives and controls an LCD panel (display panel) 10 in which a plurality of pixels are arranged and each pixel of the LCD panel 10. And a Vcom circuit 14 for applying a common voltage Vcom to the LCD panel 10.

  As shown in FIG. 1B, the LCD panel 10 has a plurality of pixels arranged in a matrix. A plurality of source lines (signal lines) S1 to S480 and a plurality of gate lines (scanning lines) G1 to G480 are arranged so as to cross each other. Each pixel is connected to one of the source line and one of the gate line via a TFT 18 as a switching element. Here, each pixel is arranged so that two adjacent pixels 16 share one source line. In this case, the TFTs 18 corresponding to the two pixels 16 are connected to different gate lines. For example, in FIG. 1B, the TFT 18 of the upper left R pixel 16 is connected to the gate line G1 and the source line S1, and the TFT 18 of the G pixel 16 adjacent to the right is connected to the gate line G2 and the source line S1. It is connected. Here, the case where the pixels 16 are arranged in a stripe arrangement is shown.

  The plurality of source lines S1 to S480 and the plurality of gate lines G1 to G480 of the LCD panel 10 are electrically connected to the driver circuit 12 by wiring 20 routed on the substrate (not shown) of the LCD panel 10. ing.

  FIG. 2 is a block diagram of the driver circuit 12 in FIG. The driver circuit 12 includes a gate driver block (scanning line driving circuit) 22, a source driver block (signal line driving circuit) 24, a level shifter circuit 26, a timing generator (hereinafter abbreviated as TG), as shown in FIG. The circuit includes a logic circuit 28, a gamma (hereinafter abbreviated as γ) circuit block 30, a charge pump / regulator block 32, an analog block 34, and other blocks.

  Here, the gate driver block 22 selects a plurality of gate lines G1 to G480 of the LCD panel 10, and the source driver block 24 displays information to be displayed on the plurality of signal lines S1 to S480 of the LCD panel 10. The video signal Vsig according to the above is output.

  The level shifter circuit 26 shifts the level of an externally supplied signal to a predetermined level. The TG unit logic circuit 28 generates a necessary timing signal and control signal based on the signal shifted to a predetermined level by the level shifter circuit 26 and a signal supplied from the outside, and supplies it to each unit in the driver circuit 12. To do.

  The γ circuit block 30 is for applying γ correction so that the video signal Vsig output from the source driver block 24 has good gradation characteristics.

  The charge pump / regulator block 32 generates various voltages of a required logic level from an external power supply, and the analog block 34 further generates various voltages from the voltage generated by the charge pump / regulator block 32. Is. The Vcom circuit 14 generates the common voltage Vcom from the voltage VVCOM generated in the analog block 34. Since the other blocks are not directly related to the present invention, the description thereof is omitted.

FIG. 3 shows the output order of the combination of video signals Vsig according to the information to be displayed, which is output to the plurality of source lines S1 to S480 in the first embodiment, and the plurality of gate lines G1 to G480 (in the drawing). It is a figure which shows the timing chart which consists of the selection order of only the gate lines G1-G8 are taken out and shown for simplification. 4A and 4B are diagrams showing the order in which the video signal Vsig is written in each pixel 16. FIG. Here, FIG. 4A shows a 1st field (odd field) and FIG. 4B shows a 2nd field (even field) for convenience. (The 1st field and the 2nd field may be interchanged.)
In the first embodiment, as shown in FIG. 3, the selection order of the plurality of gate lines G1 to G480 is changed for each field.

  That is, in the first field (1st field), the gate driver block 22 sequentially selects the plurality of gate lines G1 to G480 every ½ horizontal period (½H) in the order as in the conventional case ( The first drive is performed. Then, the source driver block 24 outputs a combination of the video signals Vsig to be written to each of the pixels 16 corresponding to the selected gate line to the plurality of source lines S1 to S480 at a half horizontal period. For example, during the ½ horizontal period in which the gate line G1 is selected, the combination of the video signal Vsig “S1-1” is output to the plurality of source lines S1 to S480, and the next gate line G2 is selected. During the half horizontal period, the combination of the video signals Vsig “S1-2” is output to the plurality of source lines S1 to S480.

  In other words, the source driver block 24 outputs data in the order of odd-numbered column data → even-numbered column data in correspondence with the output order of each pair of gate lines.

  Therefore, in the 1st field, in the pixel connection in which the number of source lines is halved as described above, the writing of the video signal Vsig to each pixel 16 is executed in the order of the gate lines as shown in FIG. As shown in FIG. 4A. As a result, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204 exists, which is a portion where there is no source line, and the potential of the pixel 16 written earlier is influenced by the potential of the pixel 16 written later. Will change.

  In the second field (2nd field), as shown in FIG. 3, the gate driver block 22 selects a set of two gate lines corresponding to two pixels 16 connected to different source lines and arranged adjacent to each other. A second drive is performed to reverse the order of the first field. That is, first, two gate lines G1 and G2 corresponding to two adjacent pixels 16 connected to different source lines are selected in the order of the gate line G2 and the gate line G1, which are in reverse order to the 1st field. Next, for the two gate lines G3 and G4 corresponding to the two pixels 16 that are connected to different source lines and are adjacently arranged, the gate line G4 and the gate line G3 are in the reverse order to the 1st field. The selection order is switched in a group of two gate lines each. As the selection order of the gate lines is changed, the source driver block 24 changes the combination of the video signals Vsig to be written to each of the pixels 16 corresponding to the selected gate lines according to the selection order to 1/2. Output to a plurality of source lines S1 to S480 at a time in the horizontal period.

  That is, the source driver block 24 outputs data in the order of even column data → odd column data in correspondence with the output order of each pair of gate lines.

  Accordingly, for example, in the 1st field, the video signal Vsig of “S1-1” → “S1-2” → “S1-3” → “S1-4” → “S1-5” → “S1-6” →. In the 2nd field, S1-2 ”→“ S1-1 ”→“ S1-4 ”→“ S1-3 ”→“ S1-6 ”→“ S1-5 ”→ The video signals Vsig are output in the order of combination.

  Therefore, in the 2nd field, in the pixel connection in which the number of source lines is halved as described above, the writing of the video signal Vsig to each pixel 16 is connected to different source lines as shown in FIG. Since the selection order of the two gate lines corresponding to the two pixels 16 is reversed, the result is as shown in FIG. 4B. As a result, also in the 2nd field, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204, which is a portion without the source line, exists, and the potential of the pixel 16 written earlier becomes the pixel written later. It changes under the influence of 16 potentials.

  However, the pixel 16 whose potential changes in the 2nd field is different from the pixel 16 whose potential changes in the 1st field. That is, in this 2nd field, the writing order of the video signal Vsig is opposite to that of the 1st field, so the writing order to the adjacent pixels 16 is switched between the 1st field and the 2nd field. For this reason, the positions of the pixels in which the potential difference occurs in the 1st field and the 2nd field are reversed, and as a result, the deviation of the pixel potential is averaged over time and display unevenness is reduced.

FIG. 5 is a diagram showing a specific configuration of the gate driver block 22 for performing the driving as described above. For simplification of explanation and illustration, the description here assumes that there are eight gate lines. In this case, the gate driver block 22 includes a 3-bit counter 36, 32 AND gates 38 to 100, 4 NOT gates 102 to 108, and 8 OR gates 110 to 124. . (Here, the countermeasure against the hazard that occurs when the inputs of the logic circuit are switched simultaneously is not essential, and is not described for simplicity. The same applies hereinafter.)
That is, a gate clock and an up / down (hereinafter abbreviated as U / D) signal are supplied from the TG unit logic circuit 28 to the 3-bit counter 36. The U / D signal is “1” at the time of non-inverted shift which is a normal display, and “0” at the time of upside-down inverted shift in which a vertically inverted display is performed. This is because the scanning direction of the gate line is reversed upside down in the non-inversion shift and the upside down shift, and as a result, the pixel written first and the pixel written later are opposite, and the operation is accordingly performed. This is because it is necessary to switch.

  Then, after the timing at which the reset signal is released, the 3-bit counter 36 starts counting in accordance with the gate clock and the up / down signal.

  The Q1 output of the 3-bit counter 36 is supplied to AND gates 40, 44, 48, and 52 for even-numbered lines X2, X4, X6, and X8 to be decoded and decoded through a NOT gate 102. This is applied to AND gates 38, 42, 46, and 50 for odd-numbered lines X1, X3, X5, and X7. The Q2 output of the 3-bit counter 36 is given to the AND gates 42, 44, 50, 52 for the lines X3, X4, X7, X8, and the lines X1, X2, X2 are connected via the NOT gate 104. It is given to AND gates 38, 40, 46, and 48 for X5 and X6. The Q3 output of the 3-bit counter 36 is given to the AND gates 46, 48, 50, 52 for the lines X5, X6, X7, X8, and via the NOT gate 106, the lines X1, X2, It is given to AND gates 38, 40, 42 and 44 for X3 and X4.

  The output of the AND gate 38 for the line X1 is given to the first AND gates 54 and 56 for the gate lines G1 and G2. The first AND gate 54 for the gate line G1 is supplied with a field switching (hereinafter abbreviated as FI) signal from the TG unit logic circuit 28, and the FI signal is NOT sent to the first AND gate 56 for the gate line G2. It is supplied through the gate 108.

  The output of the AND gate 40 for the line X2 is given to the second AND gates 58 and 60 for the gate lines G1 and G2. The second AND gates 58 and 60 for the gate lines G1 and G2 are opposite to the first AND gates 54 and 56 for the gate lines G1 and G2, and the second AND gate 58 for the gate line G1 receives the FI signal. The FI signal is supplied through a NOT gate 108 and supplied to the second AND gate 60 for the gate line G2.

  The output of the first AND gate 54 for the gate line G1 and the output of the second AND gate 58 for the gate line G1 are supplied to the OR gate 110 for the gate line G1, and the output of the OR gate 110 for the gate line G1 is The signal is supplied to the gate line G1 through the third AND gate 86 for the gate line G1 controlled by the gate enable signal from the TG unit logic circuit 28. The output of the first AND gate 56 for the gate line G2 and the output of the second AND gate 60 for the gate line G2 are supplied to the OR gate 112 for the gate line G2, and the output of the OR gate 112 for the gate line G2 is The signal is supplied to the gate line G2 through the third AND gate 88 for the gate line G2 controlled by the gate enable signal.

  Similarly, the outputs of the AND gates 42, 46 and 50 for the lines X3, X5 and X7 are the first AND gates 62 and 64 for the gate lines G3 and G4, and the first AND gates for the gate lines G5 and G6. 70, 72 and the first AND gates 78, 80 for the gate lines G7, G8. The FI signal is supplied to the first AND gates 62, 70, 78 for the gate lines G3, G5, G7, and the gates. The FI signal is supplied to the first AND gates 64, 72, and 80 for the lines G4, G6, and G8 through the NOT gate 108. The outputs 44, 48 and 52 for the lines X4, X6 and X8 are the second AND gates 66 and 68 for the gate lines G3 and G4, the second AND gates 74 and 76 for the gate lines G5 and G6, The FI signal is supplied to the second AND gates 82 and 84 for the gate lines G7 and G8, and the FI signal is supplied to the second AND gates 66, 74 and 82 for the gate lines G3, G5 and G7 via the NOT gate 108. The FI signal is supplied to the second AND gates 68, 76 and 84 for the gate lines G4, G6 and G8. The outputs of the first AND gates 62, 70, 78 for the gate line G3, G5, G7 and the outputs of the second AND gates 66, 74, 82 for the gate line G3, G5, G7 are the gate line G3. , G5, G7 OR gates 114, 118, 122 are supplied to the gate lines G3, G5, G7 OR gates 114, 118, 122 are controlled by the gate enable signal. The signals are supplied to the gate lines G3, G5, and G7 through the third AND gates 90, 94, and 98 for G3, G5, and G7. The outputs of the first AND gates 64, 72, 80 for the gate lines G4, G6, G8 and the outputs of the second AND gates 68, 76, 84 for the gate lines G4, G6, G8 are the gate line G4. , G6, and G8 OR gates 116, 120, and 124. The gate lines G4, G6, and G8 OR gates 116, 120, and 124 are controlled by the gate enable signal. The signals are supplied to the gate lines G3, G5, and G7 through the third AND gates 92, 96, and 100 for G4, G6, and G8.

  FIG. 6A is a diagram showing a timing chart of the 1st field at the time of non-inversion shift in the gate driver block 22 having such a configuration, and FIG. 6B is a diagram showing a timing chart of the 2nd field.

  At the time of non-inversion shift, in the 1st field, as shown in FIG. 6A, H signals are sequentially output to the lines X1 to X8 for a period corresponding to one gate clock. That is, in terms of timing, the line X1 is selected (H signal) → the line X2 is selected → the line X3 is selected → the line X4 is selected → the line X5 is selected → the line X6 is selected → the line X7 is Selection state → line X8 becomes a selection state.

  Here, in the 1st field, an H signal is supplied as the FI signal. Therefore, during the period when the line X1 is in the selected state, only the first AND gate 54 for the gate line G1 is in the selected state, and the G1 OR gate 110 and the gate line G1 controlled by the gate enable signal are selected. Through the third AND gate 86, the gate line G1 is selected. During the period when the line X2 is in the selected state, only the second AND gate 60 for the gate line G2 is in the selected state, and the G2 OR gate 112 and the gate line G2 controlled by the gate enable signal are used. Through the third AND gate 88, the gate line G2 is selected. Thereafter, similarly, the gate lines G3 to G8 are sequentially selected.

  In the 2nd field, as shown in FIG. 6B, the lines X1 to X8 include lines X1 → line X2 → line X3 → line X4 → line X5 → line X6 → line X7 → line as in the 1st field. It becomes a selection state in the order of X8.

  Here, in the 2nd field, an L signal is supplied as the FI signal. Accordingly, only the first AND gate 56 for the gate line G2 is selected during the period in which the line X1 is selected, and the G2 OR gate 112 and the gate line G2 controlled by the gate enable signal are selected. Through the third AND gate 88, the gate line G2 is selected. During the period when the line X2 is in the selected state, only the second AND gate 58 for the gate line G1 is in the selected state, and the G1 OR gate 110 and the gate line G1 controlled by the gate enable signal are used. Through the third AND gate 86, the gate line G1 is selected. Similarly, the gate line G4, the gate line G3, the gate line G6, the gate line G5, the gate line G8, and the gate line G7 are selected in this order.

  FIG. 7A is a diagram showing a timing chart of the 1st field at the time of vertical inversion shift in the gate driver block 22 having the configuration of FIG. 5, and FIG. 7B is a diagram showing a timing chart of the 2nd field. (Note that the reset signal falls one gate clock earlier than that in FIGS. 6A and 6B at the time of the upside down shift.) Also, FIGS. It is a figure which shows the order which writes in video signal Vsig. Here, FIG. 8A shows the 1st field, and FIG. 8B shows the 2nd field.

  At the time of upside down shift, in the 1st field, as shown in FIG. 7A, H signals are sequentially output in the reverse direction to the lines X1 to X8 for a period corresponding to one gate clock. That is, in terms of timing, the line X8 is selected → the line X7 is selected → the line X6 is selected → the line X5 is selected → the line X4 is selected → the line X3 is selected → the line X2 is selected → the line X1 becomes the selected state.

  Here, in the 1st field, an H signal is supplied as the FI signal. Therefore, during the period when the line X8 is in the selected state, only the second AND gate 84 for the gate line G8 is in the selected state, and the G8 OR gate 124 and the gate line G8 controlled by the gate enable signal are used. Through the third AND gate 100, the gate line G8 is selected. During the period when the line X7 is in the selected state, only the first AND gate 78 for the gate line G7 is in the selected state, and the G7 OR gate 122 and the gate line G7 controlled by the gate enable signal are used. Through the third AND gate 98, the gate line G7 is selected. Thereafter, similarly, the gate lines G6 to G1 are sequentially selected.

  Accordingly, in the 1st field, the writing of the video signal Vsig to each pixel 16 is executed in the reverse order of the gate lines as shown in FIG. 7A, and thus is as shown in FIG. 8A. As a result, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204 exists, which is a portion where there is no source line, and the potential of the pixel 16 written earlier is influenced by the potential of the pixel 16 written later. Will change.

  In the 2nd field, as shown in FIG. 7B, the lines X1 to X8 include lines X8 → line X7 → line X6 → line X5 → line X4 → line X3 → line X2 → line as in the 1st field. The selected state is in the order of X1.

  Here, in the 2nd field, an L signal is supplied as the FI signal. Therefore, during the period when the line X8 is in the selected state, only the second AND gate 82 for the gate line G7 is in the selected state, and the G7 OR gate 122 and the gate line G7 controlled by the gate enable signal are used. Through the third AND gate 98, the gate line G7 is selected. During the period when the line X7 is in the selected state, only the first AND gate 80 for the gate line G8 is in the selected state, and the G8 OR gate 124 and the gate line G8 controlled by the gate enable signal are used. Through the third AND gate 100, the gate line G8 is selected. Thereafter, similarly, the gate line G5 → the gate line G6 → the gate line G3 → the gate line G4 → the gate line G1 → the gate line G2 are selected.

  Accordingly, in the 2nd field, in the pixel connection in which the number of source lines is halved as described above, the writing of the video signal Vsig to each pixel 16 is connected to different source lines and adjacently arranged as shown in FIG. 7B. Since the selection order of the two gate lines corresponding to the two pixels 16 is executed in the reverse direction, the result is as shown in FIG. 8B. As a result, also in the 2nd field, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204, which is a portion without the source line, exists, and the potential of the pixel 16 written earlier becomes the pixel written later. It changes under the influence of 16 potentials.

  However, the pixel 16 whose potential changes in the 2nd field is different from the pixel 16 whose potential changes in the 1st field. That is, in this 2nd field, the writing order of the video signal Vsig is opposite to that of the 1st field, so the writing order to the adjacent pixels 16 is switched between the 1st field and the 2nd field. For this reason, the positions of the pixels in which the potential difference occurs in the 1st field and the 2nd field are reversed, and as a result, the deviation of the pixel potential is averaged over time and display unevenness is reduced.

  As described above, according to the first embodiment, when a plurality of gate lines are sequentially selected by the gate driver block 22, two gates corresponding to two pixels connected to different source lines and arranged adjacent to each other are connected. By changing the selection order of the lines for each field, the potential difference of the pixels is averaged over time, so that display unevenness can be reduced.

Then, the combination of the video signals Vsig according to the information to be displayed output from the source driver block 24 to the plurality of source lines is odd in the 2nd field as shown in FIG. Since the order of the data of the column and the even column is switched and output, the display can be performed without any disturbance. The output order of the combination of the video signals Vsig in the 2nd field is not particularly shown in detail in the circuit configuration, but for example, the TG unit logic circuit 28 holds the combination of the video signals Vsig for at least one line, The order of the data in the odd and even columns may be switched and supplied to the source driver block 24, or the order of the data in the odd and even columns in the source driver block 24 may be switched. Alternatively, on the side where the video signal is supplied to the active matrix display device, the data of the odd and even columns of the video signal may be switched in the 2nd field. (This is basically the same as the operation performed during upside down shifting.)
(A field memory is required when up / down inversion shifting is performed, but a line memory can be realized when up / down inversion shifting is not performed.)
[Modification]
In the first embodiment, for each field, the order of sequentially selecting two scanning lines corresponding to two pixels connected to different signal lines and adjacently arranged is switched. However, as shown in FIG. You may make it switch for every gate line (every 1H period, every 2 scanning periods).

  In this way, the video signal Vsig is written to each pixel 16 in the order shown in FIG. 10A for the 1st field and FIG. 10B for the 2nd field, so that even if the pixels affected by the parasitic capacitance are within the same field. Since they do not align vertically, the vertical stripes can be made less noticeable.

  A circuit example for realizing such driving is shown in FIG. This is the same except that an exclusive OR gate 126 is added in FIG. 5 to input the FI signal and the Q2 signal and output the FI ′ signal instead of the FI signal.

  FIGS. 12A and 12B show the circuit operation of FIG. 11 during non-inversion shift.

FIG. 13A and FIG. 13B show the circuit operation of FIG. 11 during the upside down shift. (At the time of upside down shift, the reset signal falls one gate clock earlier than in FIGS. 12A and 12B.)
In this circuit, as a more preferable example, the selection order of scanning lines is switched every two gate lines (every 1H period, every two scanning periods) and every field.

  Such a drive can be realized by making a simple change to the gate driver block of FIG.

  This can also be applied to the LCD panel 10 having a configuration in which pixels and TFTs are connected as shown in FIG.

  Also in this case, the scanning lines are sequentially selected so that the order shown in FIGS. 15A and 15B is obtained. In the case of the connection as shown in FIG. 14, the circuit example for realizing the drive can be the one shown in FIG. 5, which is advantageous in that a conventional gate driver can be used.

  As described above, according to the present modification, by performing such driving, the vertical stripes themselves become zigzag stripes even in the same field, so that the vertical stripes themselves are hardly visible.

  Here, a more preferable example is shown in which the scanning line selection order is switched for each field. However, even in a method in which the scanning line selection order is not switched for each field, vertical stripes themselves become zigzag stripes in the same field. Therefore, there is an effect that it becomes difficult to see the vertical stripes themselves. In that case, the FI signal may be fixed in the circuit of FIG.

  Further, here, switching is performed every two gate lines, but it may be performed every 2j (j is an integer of 2 or more) gate lines (a shorter cycle is preferable).

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

  As shown in FIG. 1B, in the active matrix display device, in addition to the stripe arrangement in which the pixels 16 are arranged vertically and horizontally, a delta arrangement in which three types of RGB pixels are arranged in a delta shape is known.

  FIG. 16 is a schematic diagram of pixel connection of an LCD panel employing such a delta arrangement. In this delta arrangement, the plurality of source lines S1 to S480 are not formed linearly as in the stripe arrangement as shown in FIG. 1B, but are sewn between the pixels 16 as shown in FIG. The pixels corresponding to the odd-numbered rows and the pixels corresponding to the even-numbered rows are arranged so as to be shifted by half the adjacent pixel pitch in the column direction.

  FIG. 17A is a diagram showing the order in which the video signal Vsig is written to each pixel 16 in the 1st field at the time of non-inversion shift in the second embodiment, and FIG. 17B is the same as that in FIG. 17B. It is a figure which shows the order to write.

  Also in the second embodiment, as shown in FIG. 3, the selection order of the plurality of gate lines G1 to G480 is changed for each field.

  That is, in the 1st field, the gate driver block 22 performs the first driving for sequentially selecting the plurality of gate lines G1 to G480 every 1/2 horizontal period in the order. Then, the source driver block 24 outputs a combination of the video signals Vsig to be written to each of the pixels 16 corresponding to the selected gate line to the plurality of source lines S1 to S480 at a half horizontal period. Therefore, in the 1st field, the writing of the video signal Vsig to each pixel 16 is executed in the order of the gate lines as shown in FIG. 3, so that it becomes as shown in FIG. 17A. As a result, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204 exists, which is a portion where there is no source line, and the potential of the pixel 16 written earlier is influenced by the potential of the pixel 16 written later. Will change.

  In the 2nd field, as shown in FIG. 3, the gate driver block 22 sets the selection order of the pair of two gate lines corresponding to the two pixels 16 connected to different source lines and adjacent to each other as the 1st field. Performs the second driving to be reversed. As the selection order of the gate lines is changed, the source driver block 24 changes the combination of the video signals Vsig to be written to each of the pixels 16 corresponding to the selected gate lines according to the selection order to 1/2. Output to a plurality of source lines S1 to S480 at a time in the horizontal period. Therefore, in the 2nd field, the writing of the video signal Vsig to each pixel 16 is performed by selecting two gate lines corresponding to two pixels 16 connected to different source lines and adjacent to each other as shown in FIG. Since the order is executed in the reverse order, the result is as shown in FIG. 17B. As a result, also in the 2nd field, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204, which is a portion without the source line, exists, and the potential of the pixel 16 written earlier becomes the pixel written later. It changes under the influence of 16 potentials.

  However, the pixel 16 whose potential changes in the 2nd field is different from the pixel 16 whose potential changes in the 1st field. That is, in this 2nd field, the writing order of the video signal Vsig is opposite to that of the 1st field, so the writing order to the adjacent pixels 16 is switched between the 1st field and the 2nd field. For this reason, the positions of the pixels in which the potential difference occurs in the 1st field and the 2nd field are reversed, and as a result, the deviation of the pixel potential is averaged over time and display unevenness is reduced.

  FIG. 18A is a diagram showing the order in which the video signal Vsig is written to each pixel 16 in the 1st field at the time of vertical inversion shift in the gate driver block 22 having the configuration of FIG. 5, and FIG. It is a figure which shows the order which writes the video signal Vsig in each pixel 16 in 2nd field.

  At the time of upside down shift, in the 1st field, the writing of the video signal Vsig to each pixel 16 is executed in the reverse order of the gate lines as shown in FIG. 7A, and therefore, as shown in FIG. 18A. . As a result, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204 exists, which is a portion where there is no source line, and the potential of the pixel 16 written earlier is influenced by the potential of the pixel 16 written later. Will change.

  Then, in the 2nd field, the writing of the video signal Vsig to each pixel 16 is performed by selecting two gate lines corresponding to two adjacent pixels 16 connected to different source lines as shown in FIG. 7B. Since the order is executed in the reverse order, the order is as shown in FIG. 18B. As a result, also in the 2nd field, a voltage leak occurs between the pixels where the inter-pixel parasitic capacitance 204, which is a portion without the source line, exists, and the potential of the pixel 16 written earlier becomes the pixel written later. It changes under the influence of 16 potentials.

  However, the pixel 16 whose potential changes in the 2nd field is different from the pixel 16 whose potential changes in the 1st field. That is, in this 2nd field, the writing order of the video signal Vsig is opposite to that of the 1st field, so the writing order to the adjacent pixels 16 is switched between the 1st field and the 2nd field. For this reason, the positions of the pixels in which the potential difference occurs in the 1st field and the 2nd field are reversed, and as a result, the deviation of the pixel potential is averaged over time and display unevenness is reduced.

  As described above, even when the delta arrangement is employed, display unevenness can be similarly reduced by performing the same driving as in the first embodiment.

  Further, when the pixels 16 are arranged in a delta arrangement, display unevenness (for example, vertical stripes corresponding to FIG. 16) meanders compared to the case where the pixels 16 are arranged in a stripe arrangement as in the first embodiment. There is also an effect that it is difficult to stand out.

  Further, by driving as shown in the modification of the first embodiment (FIG. 9), it is possible to make the meandering more complicated and make the vertical stripes less noticeable.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the gist of the present invention. .

  For example, the order of pixel writing may not be the order of the above-described embodiments as long as the order between adjacent pixels is switched for each field.

  In the above-described embodiment, the writing order is switched for each field, but substantially the same effect can be obtained even when switching is performed every two fields (every frame).

  Furthermore, switching may be performed for each k field (k is an integer of 3 or more), but a shorter cycle is preferable.

  Here, the case of a normally white mode liquid crystal display device in which the transmittance decreases (becomes darker) as the voltage applied to the pixel is increased. However, the transmittance increases (becomes brighter) as the voltage applied to the pixel is increased. Needless to say, the present invention can also be applied to a black mode liquid crystal display device.

  In addition, although an example of a color display liquid crystal has been described here, it is needless to say that a monochrome (monochrome) display liquid crystal may be used.

  Furthermore, it goes without saying that the switching element is not limited to a TFT but may be a diode or the like. Of course, the number of gate lines and source lines is not limited to the example of FIG.

  Further, if the pixel of the active matrix display device is not limited to a liquid crystal but a capacitive element, parasitic capacitance between pixels is generated, and thus display unevenness can be similarly reduced by the present invention.

(A) is a schematic block diagram which shows the whole structure of the active matrix type display apparatus which concerns on 1st Embodiment of this invention, (B) is the schematic diagram of the pixel connection of the LCD panel (display panel) in (A). It is. FIG. 2 is a block configuration diagram of a driver circuit in FIG. It is a figure which shows the timing chart which consists of the output order of the combination of the video signal according to the information which should be displayed output to several source lines in 1st Embodiment, and the selection order of several gate lines. It is a figure which shows the order which writes a video signal in each pixel in the 1st field in 1st Embodiment. It is a figure which shows the order which writes a video signal in each pixel in 2nd field in 1st Embodiment. It is a figure which shows the specific structure of the gate driver block in 1st Embodiment in FIG. FIG. 6 is a diagram showing a timing chart of the 1st field at the time of non-inversion shift in the gate driver block of FIG. 5. FIG. 6 is a diagram showing a timing chart of a 2nd field at the time of non-inverting shift in the gate driver block of FIG. 5. FIG. 6 is a diagram showing a timing chart of the 1st field at the time of vertical inversion shift in the gate driver block of FIG. 5. FIG. 6 is a diagram illustrating a timing chart of a 2nd field at the time of vertical inversion shift in the gate driver block of FIG. 5. It is a figure which shows the order which writes a video signal in each pixel in the 1st field at the time of the vertical inversion shift in 1st Embodiment. It is a figure which shows the order which writes a video signal in each pixel in 2nd field at the time of the vertical inversion shift in 1st Embodiment. It is a figure which shows the timing chart which consists of the output order of the combination of the video signal according to the information which should be displayed output to several source lines in the modification of 1st Embodiment, and the selection order of several gate lines. It is a figure which shows the order which writes a video signal in each pixel in the 1st field in the modification of 1st Embodiment. It is a figure which shows the order which writes a video signal in each pixel in 2nd field in the modification of 1st Embodiment. It is a figure which shows the specific structure of the gate driver block in the modification of 1st Embodiment. FIG. 12 is a diagram illustrating a timing chart of the 1st field at the time of non-inversion shift in the gate driver block of FIG. 11. FIG. 12 is a diagram illustrating a timing chart of a 2nd field at the time of non-inverting shift in the gate driver block of FIG. 11. FIG. 12 is a timing chart of the 1st field at the time of vertical inversion shift in the gate driver block of FIG. 11. FIG. 12 is a diagram illustrating a timing chart of a 2nd field at the time of vertical inversion shift in the gate driver block of FIG. 11. It is the schematic of another pixel connection of a LCD panel (display panel). It is a figure which shows the order which writes a video signal in each pixel in the 1st field in the pixel connection of FIG. It is a figure which shows the order which writes a video signal in each pixel in 2nd field in the pixel connection of FIG. It is the schematic of the pixel connection of the LCD panel which employ | adopted the delta arrangement | sequence in 2nd Embodiment of this invention. It is a figure which shows the order which writes a video signal in each pixel in 1st field at the time of the non-inversion shift in 2nd Embodiment of this invention. It is a figure which shows the order which writes a video signal in each pixel in 2nd field at the time of the non-inversion shift in 2nd Embodiment of this invention. It is a figure which shows the order which writes a video signal in each pixel in 1st field at the time of the vertical inversion shift in 2nd Embodiment of this invention. It is a figure which shows the order which writes a video signal in each pixel in 2nd field at the time of vertical inversion shift in 2nd Embodiment of this invention. It is the schematic which shows the pixel connection of the display panel which halved the number of source lines in the conventional active matrix type display apparatus. It is a figure which shows the scanning timing chart in the pixel connection of FIG. It is a figure which shows the order which writes a video signal in each pixel in the pixel connection of FIG. It is a figure which shows the equivalent circuit of the display panel of FIG. It is a figure which shows the example of the display nonuniformity in the display panel of FIG. It is a figure which shows the structure of each pixel at the time of using a display panel as a TFTLCD panel. (A) is a diagram showing a scanning timing chart, and (B) is a diagram showing a pixel potential waveform in horizontal line inversion driving when there is no inter-pixel parasitic capacitance. FIG. 6 is a diagram showing a pixel potential waveform in horizontal line inversion driving in consideration of the inter-pixel parasitic capacitance. In particular, (A) shows that the amplitude of the common voltage is 5.0 V, and the write voltage of the G ahead pixel is relative to the common voltage. FIG. 5B is a diagram illustrating a case where the writing voltage of the pixel after 2.0V is set to 4.0V with respect to the common voltage, and FIG. FIG. 5 is a diagram showing a pixel potential waveform when the common voltage is 2.0 V and the write voltage of the pixel after R is 1.0 V with respect to the common voltage. FIG. 6 is a diagram showing a pixel potential waveform in dot inversion driving in consideration of the inter-pixel parasitic capacitance, and in particular, (A) shows that the amplitude of the common voltage is 5.0 V, and the write voltage of the G-th pixel is relative to the common voltage FIG. 5B is a diagram illustrating a pixel potential waveform when a writing voltage of a pixel after 2.0 V and R is 4.0 V with respect to the common voltage, and FIG. FIG. 6 is a diagram illustrating a pixel potential waveform when the write voltage of 2.0 V is 2.0 V with respect to the common voltage and the write voltage of the pixel after R is 1.0 V with respect to the common voltage.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10 ... LCD panel (display panel), 12 ... Driver circuit, 14 ... Vcom circuit, 16 ... Pixel, 18 ... TFT, 20 ... Wiring, 22 ... Gate driver block (scanning line drive circuit), 24 ... Source driver block (signal) Line driver circuit), 26... Level shifter circuit, 28... Timing generator (TG) logic circuit, 30... Gamma (.gamma.) Circuit block, 32... Regulator block, 34 ... analog block, 36. AND gate, 102-108 ... NOT gate, 110-124 ... OR gate, 126 ... Exclusive OR gate, S1-S480 ... Source line (signal line), G1-G480 ... Gate line (scan line).

Claims (21)

An active matrix type in which one signal line is arranged for every two pixels, and two adjacent pixels across the signal line share the signal line and are connected to different scanning lines via switching elements. A drive circuit for a display device,
A scanning line driving circuit for selecting the plurality of scanning lines;
A signal line driving circuit for outputting a signal in accordance with information to be displayed to the plurality of signal lines;
Comprising
The scanning line driving circuit includes a first driving for sequentially selecting two scanning lines corresponding to two adjacent pixels connected to different signal lines, and the selection order of the two scanning lines according to the first order. A drive circuit for an active matrix display device, wherein a second drive that is opposite to the drive of 1 is alternately performed at least for each predetermined period.   2. The drive circuit for an active matrix display device according to claim 1, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more).   The predetermined period includes two periods, the first period is a 2j scanning period (j is an integer of 1 or more), and the second period is a k field (k: an integer of 1 or more). A drive circuit for an active matrix display device according to claim 1.   2. The drive circuit for an active matrix display device according to claim 1, wherein the predetermined period is every k fields (k: an integer of 1 or more).   5. The active matrix type according to claim 1, wherein the signal line driving circuit outputs a signal corresponding to the selection order of the scanning lines by the scanning line driving circuit to the plurality of signal lines. 6. A driving circuit of a display device.   6. The drive circuit for an active matrix display device according to claim 1, wherein the display panel is a display panel having a stripe arrangement in which the plurality of pixels are arranged in a stripe pattern.   6. The drive circuit for an active matrix display device according to claim 1, wherein the display panel is a display panel having a delta arrangement in which the plurality of pixels are arranged in a delta shape. An active matrix type in which one signal line is arranged for every two pixels, and two adjacent pixels across the signal line share the signal line and are connected to different scanning lines via switching elements. A driving method of a display device,
A first drive for sequentially selecting two scanning lines corresponding to two pixels connected to different signal lines and arranged adjacent to each other, and a selection order of the two scanning lines are reversed from the first driving. A driving method of an active matrix display device, wherein the second driving and the second driving are alternately performed at least every predetermined period.   9. The method of driving an active matrix display device according to claim 8, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more).   The predetermined period includes two periods, the first period is a 2j scanning period (j is an integer of 1 or more), and the second period is a k field (k: an integer of 1 or more). The method for driving an active matrix display device according to claim 8.   9. The method of driving an active matrix display device according to claim 8, wherein the predetermined period is every k fields (k: an integer of 1 or more).   12. The active matrix display device according to claim 8, wherein a signal according to information to be displayed output to the plurality of signal lines is output in accordance with a selection order of the scanning lines. Driving method.   13. The method for driving an active matrix display device according to claim 8, wherein the display panel is a display panel having a stripe arrangement in which the plurality of pixels are arranged in a stripe pattern.   The method of driving an active matrix display device according to claim 8, wherein the display panel is a display panel having a delta arrangement in which the plurality of pixels are arranged in a delta shape. A display panel in which one signal line is arranged for every two pixels, and two adjacent pixels across the signal line share the signal line and are connected to different scanning lines via switching elements, respectively ,
A scanning line driving circuit for selecting the plurality of scanning lines;
A signal line driving circuit for outputting a signal in accordance with information to be displayed to the plurality of signal lines;
Comprising
The scanning line driving circuit includes a first driving for sequentially selecting two scanning lines corresponding to two adjacent pixels connected to different signal lines, and the selection order of the two scanning lines according to the first order. 2. An active matrix display device characterized in that the second driving, which is opposite to the driving of 1, is alternately performed at least every predetermined period.   16. The active matrix display device according to claim 15, wherein the predetermined period is every 2j scanning periods (j is an integer of 1 or more).   The predetermined period includes two periods, the first period is a 2j scanning period (j is an integer of 1 or more), and the second period is a k field (k: an integer of 1 or more). The active matrix display device according to claim 15.   16. The active matrix display device according to claim 15, wherein the predetermined period is every k fields (k is an integer of 1 or more).   The active matrix type according to any one of claims 15 to 18, wherein the signal line driving circuit outputs a signal corresponding to the selection order of the scanning lines by the scanning line driving circuit to the plurality of signal lines. Display device.   The active matrix display device according to claim 15, wherein the display panel is a display panel having a stripe arrangement in which the plurality of pixels are arranged in a stripe pattern.   20. The active matrix display device according to claim 15, wherein the display panel is a delta arrangement display panel in which the plurality of pixels are arranged in a delta shape.

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